Lines Matching +full:synquacer +full:- +full:pre +full:- +full:its
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 atf-sram@0 {
21 scm_conf: scm-conf@100000 {
22 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
24 #address-cells = <1>;
25 #size-cells = <1>;
28 serdes_ln_ctrl: serdes-ln-ctrl@4080 {
29 compatible = "mmio-mux";
30 #mux-control-cells = <1>;
31 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
35 usb_serdes_mux: mux-controller@4000 {
36 compatible = "mmio-mux";
37 #mux-control-cells = <1>;
38 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
42 gic500: interrupt-controller@1800000 {
43 compatible = "arm,gic-v3";
44 #address-cells = <2>;
45 #size-cells = <2>;
47 #interrupt-cells = <3>;
48 interrupt-controller;
55 gic_its: msi-controller@1820000 {
56 compatible = "arm,gic-v3-its";
58 socionext,synquacer-pre-its = <0x1000000 0x400000>;
59 msi-controller;
60 #msi-cells = <1>;
64 main_gpio_intr: interrupt-controller0 {
65 compatible = "ti,sci-intr";
66 ti,intr-trigger-type = <1>;
67 interrupt-controller;
68 interrupt-parent = <&gic500>;
69 #interrupt-cells = <1>;
71 ti,sci-dev-id = <131>;
72 ti,interrupt-ranges = <8 392 56>;
76 compatible = "simple-mfd";
77 #address-cells = <2>;
78 #size-cells = <2>;
80 ti,sci-dev-id = <199>;
82 main_navss_intr: interrupt-controller1 {
83 compatible = "ti,sci-intr";
84 ti,intr-trigger-type = <4>;
85 interrupt-controller;
86 interrupt-parent = <&gic500>;
87 #interrupt-cells = <1>;
89 ti,sci-dev-id = <213>;
90 ti,interrupt-ranges = <0 64 64>,
95 main_udmass_inta: msi-controller@33d00000 {
96 compatible = "ti,sci-inta";
98 interrupt-controller;
99 #interrupt-cells = <0>;
100 interrupt-parent = <&main_navss_intr>;
101 msi-controller;
103 ti,sci-dev-id = <209>;
104 ti,interrupt-ranges = <0 0 256>;
108 compatible = "ti,am654-secure-proxy";
109 #mbox-cells = <1>;
110 reg-names = "target_data", "rt", "scfg";
114 interrupt-names = "rx_011";
119 compatible = "ti,am654-navss-ringacc";
124 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
125 ti,num-rings = <1024>;
126 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
128 ti,sci-dev-id = <211>;
129 msi-parent = <&main_udmass_inta>;
132 main_udmap: dma-controller@31150000 {
133 compatible = "ti,j721e-navss-main-udmap";
137 reg-names = "gcfg", "rchanrt", "tchanrt";
138 msi-parent = <&main_udmass_inta>;
139 #dma-cells = <1>;
142 ti,sci-dev-id = <212>;
145 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
148 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
151 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
155 compatible = "ti,j721e-cpts";
157 reg-names = "cpts";
159 clock-names = "cpts";
160 interrupts-extended = <&main_navss_intr 391>;
161 interrupt-names = "cpts";
162 ti,cpts-periodic-outputs = <6>;
163 ti,cpts-ext-ts-inputs = <8>;
168 compatible = "pinctrl-single";
171 #pinctrl-cells = <1>;
172 pinctrl-single,register-width = <32>;
173 pinctrl-single,function-mask = <0xffffffff>;
177 compatible = "ti,j721e-uart", "ti,am654-uart";
179 reg-shift = <2>;
180 reg-io-width = <4>;
182 clock-frequency = <48000000>;
183 current-speed = <115200>;
184 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
186 clock-names = "fclk";
190 compatible = "ti,j721e-uart", "ti,am654-uart";
192 reg-shift = <2>;
193 reg-io-width = <4>;
195 clock-frequency = <48000000>;
196 current-speed = <115200>;
197 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
199 clock-names = "fclk";
203 compatible = "ti,j721e-uart", "ti,am654-uart";
205 reg-shift = <2>;
206 reg-io-width = <4>;
208 clock-frequency = <48000000>;
209 current-speed = <115200>;
210 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
212 clock-names = "fclk";
216 compatible = "ti,j721e-uart", "ti,am654-uart";
218 reg-shift = <2>;
219 reg-io-width = <4>;
221 clock-frequency = <48000000>;
222 current-speed = <115200>;
223 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
225 clock-names = "fclk";
229 compatible = "ti,j721e-uart", "ti,am654-uart";
231 reg-shift = <2>;
232 reg-io-width = <4>;
234 clock-frequency = <48000000>;
235 current-speed = <115200>;
236 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
238 clock-names = "fclk";
242 compatible = "ti,j721e-uart", "ti,am654-uart";
244 reg-shift = <2>;
245 reg-io-width = <4>;
247 clock-frequency = <48000000>;
248 current-speed = <115200>;
249 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
251 clock-names = "fclk";
255 compatible = "ti,j721e-uart", "ti,am654-uart";
257 reg-shift = <2>;
258 reg-io-width = <4>;
260 clock-frequency = <48000000>;
261 current-speed = <115200>;
262 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
264 clock-names = "fclk";
268 compatible = "ti,j721e-uart", "ti,am654-uart";
270 reg-shift = <2>;
271 reg-io-width = <4>;
273 clock-frequency = <48000000>;
274 current-speed = <115200>;
275 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
277 clock-names = "fclk";
281 compatible = "ti,j721e-uart", "ti,am654-uart";
283 reg-shift = <2>;
284 reg-io-width = <4>;
286 clock-frequency = <48000000>;
287 current-speed = <115200>;
288 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
290 clock-names = "fclk";
294 compatible = "ti,j721e-uart", "ti,am654-uart";
296 reg-shift = <2>;
297 reg-io-width = <4>;
299 clock-frequency = <48000000>;
300 current-speed = <115200>;
301 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
303 clock-names = "fclk";
307 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
310 #address-cells = <1>;
311 #size-cells = <0>;
312 clock-names = "fck";
314 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
318 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
321 #address-cells = <1>;
322 #size-cells = <0>;
323 clock-names = "fck";
325 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
329 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
332 #address-cells = <1>;
333 #size-cells = <0>;
334 clock-names = "fck";
336 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
340 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
343 #address-cells = <1>;
344 #size-cells = <0>;
345 clock-names = "fck";
347 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
351 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
354 #address-cells = <1>;
355 #size-cells = <0>;
356 clock-names = "fck";
358 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
362 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
365 #address-cells = <1>;
366 #size-cells = <0>;
367 clock-names = "fck";
369 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
373 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
376 #address-cells = <1>;
377 #size-cells = <0>;
378 clock-names = "fck";
380 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
384 compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit";
387 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
388 clock-names = "clk_xin", "clk_ahb";
390 ti,otap-del-sel-legacy = <0x0>;
391 ti,otap-del-sel-mmc-hs = <0x0>;
392 ti,otap-del-sel-ddr52 = <0x6>;
393 ti,otap-del-sel-hs200 = <0x8>;
394 ti,otap-del-sel-hs400 = <0x0>;
395 ti,strobe-sel = <0x77>;
396 ti,trm-icp = <0x8>;
397 bus-width = <8>;
398 mmc-ddr-1_8v;
399 dma-coherent;
403 compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit";
406 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
407 clock-names = "clk_xin", "clk_ahb";
409 ti,otap-del-sel-legacy = <0x0>;
410 ti,otap-del-sel-sd-hs = <0x0>;
411 ti,otap-del-sel-sdr12 = <0xf>;
412 ti,otap-del-sel-sdr25 = <0xf>;
413 ti,otap-del-sel-sdr50 = <0xc>;
414 ti,otap-del-sel-sdr104 = <0x5>;
415 ti,otap-del-sel-ddr50 = <0xc>;
416 no-1-8-v;
417 dma-coherent;
420 usbss0: cdns-usb@4104000 {
421 compatible = "ti,j721e-usb";
423 dma-coherent;
424 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
426 clock-names = "ref", "lpm";
427 assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */
428 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */
429 #address-cells = <2>;
430 #size-cells = <2>;
438 reg-names = "otg", "xhci", "dev";
442 interrupt-names = "host",
445 maximum-speed = "super-speed";