Lines Matching +full:io +full:- +full:channel +full:- +full:ranges
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
9 mcu_conf: scm-conf@40f00000 {
10 compatible = "syscon", "simple-mfd";
12 #address-cells = <1>;
13 #size-cells = <1>;
14 ranges = <0x0 0x0 0x40f00000 0x20000>;
17 compatible = "ti,am654-phy-gmii-sel";
19 #phy-cells = <1>;
24 compatible = "ti,am654-uart";
26 reg-shift = <2>;
27 reg-io-width = <4>;
29 clock-frequency = <96000000>;
30 current-speed = <115200>;
31 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
35 compatible = "mmio-sram";
37 ranges = <0x0 0x00 0x41c00000 0x80000>;
38 #address-cells = <1>;
39 #size-cells = <1>;
43 compatible = "ti,am654-i2c", "ti,omap4-i2c";
46 #address-cells = <1>;
47 #size-cells = <0>;
48 clock-names = "fck";
50 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
54 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
58 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
59 #address-cells = <1>;
60 #size-cells = <0>;
64 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
68 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
69 #address-cells = <1>;
70 #size-cells = <0>;
74 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
78 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
79 #address-cells = <1>;
80 #size-cells = <0>;
84 compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
88 assigned-clocks = <&k3_clks 0 2>;
89 assigned-clock-rates = <60000000>;
90 clock-names = "adc_tsc_fck";
93 dma-names = "fifo0", "fifo1";
96 #io-channel-cells = <1>;
97 compatible = "ti,am654-adc", "ti,am3359-adc";
102 compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
106 assigned-clocks = <&k3_clks 1 2>;
107 assigned-clock-rates = <60000000>;
108 clock-names = "adc_tsc_fck";
111 dma-names = "fifo0", "fifo1";
114 #io-channel-cells = <1>;
115 compatible = "ti,am654-adc", "ti,am3359-adc";
119 mcu-navss {
120 compatible = "simple-mfd";
121 #address-cells = <2>;
122 #size-cells = <2>;
123 ranges;
124 dma-coherent;
125 dma-ranges;
127 ti,sci-dev-id = <119>;
130 compatible = "ti,am654-navss-ringacc";
135 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
136 ti,num-rings = <286>;
137 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
138 ti,dma-ring-reset-quirk;
140 ti,sci-dev-id = <195>;
141 msi-parent = <&inta_main_udmass>;
144 mcu_udmap: dma-controller@285c0000 {
145 compatible = "ti,am654-navss-mcu-udmap";
149 reg-names = "gcfg", "rchanrt", "tchanrt";
150 msi-parent = <&inta_main_udmass>;
151 #dma-cells = <1>;
154 ti,sci-dev-id = <194>;
157 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
159 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
161 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
166 compatible = "simple-bus";
167 #address-cells = <2>;
168 #size-cells = <2>;
169 ranges;
172 compatible = "ti,am654-ospi", "cdns,qspi-nor";
176 cdns,fifo-depth = <256>;
177 cdns,fifo-width = <4>;
178 cdns,trigger-address = <0x0>;
180 assigned-clocks = <&k3_clks 248 0>;
181 assigned-clock-parents = <&k3_clks 248 2>;
182 assigned-clock-rates = <166666666>;
183 power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
184 #address-cells = <1>;
185 #size-cells = <0>;
189 compatible = "ti,am654-ospi", "cdns,qspi-nor";
193 cdns,fifo-depth = <256>;
194 cdns,fifo-width = <4>;
195 cdns,trigger-address = <0x0>;
197 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
198 #address-cells = <1>;
199 #size-cells = <0>;
204 compatible = "ti,am654-cpsw-nuss";
205 #address-cells = <2>;
206 #size-cells = <2>;
208 reg-names = "cpsw_nuss";
209 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
210 dma-coherent;
212 clock-names = "fck";
213 power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
224 dma-names = "tx0", "tx1", "tx2", "tx3",
228 ethernet-ports {
229 #address-cells = <1>;
230 #size-cells = <0>;
234 ti,mac-only;
236 ti,syscon-efuse = <&mcu_conf 0x200>;
242 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
244 #address-cells = <1>;
245 #size-cells = <0>;
247 clock-names = "fck";
252 compatible = "ti,am65-cpts";
255 clock-names = "cpts";
256 interrupts-extended = <&gic500 GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>;
257 interrupt-names = "cpts";
258 ti,cpts-ext-ts-inputs = <4>;
259 ti,cpts-periodic-outputs = <2>;
261 mcu_cpsw_cpts_mux: refclk-mux {
262 #clock-cells = <0>;
267 assigned-clocks = <&mcu_cpsw_cpts_mux>;
268 assigned-clock-parents = <&k3_clks 118 5>;