Lines Matching +full:synquacer +full:- +full:pre +full:- +full:its
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
31 compatible = "arm,gic-v3";
32 #address-cells = <2>;
33 #size-cells = <2>;
35 #interrupt-cells = <3>;
36 interrupt-controller;
45 gic_its: msi-controller@1820000 {
46 compatible = "arm,gic-v3-its";
48 socionext,synquacer-pre-its = <0x1000000 0x400000>;
49 msi-controller;
50 #msi-cells = <1>;
55 compatible = "ti,phy-am654-serdes";
57 reg-names = "serdes";
58 #phy-cells = <2>;
59 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
61 clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
62 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
63 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
64 ti,serdes-clk = <&serdes0_clk>;
65 #clock-cells = <1>;
66 mux-controls = <&serdes_mux 0>;
70 compatible = "ti,phy-am654-serdes";
72 reg-names = "serdes";
73 #phy-cells = <2>;
74 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
76 clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
77 assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
78 assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
79 ti,serdes-clk = <&serdes1_clk>;
80 #clock-cells = <1>;
81 mux-controls = <&serdes_mux 1>;
85 compatible = "ti,am654-uart";
87 reg-shift = <2>;
88 reg-io-width = <4>;
90 clock-frequency = <48000000>;
91 current-speed = <115200>;
92 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
96 compatible = "ti,am654-uart";
98 reg-shift = <2>;
99 reg-io-width = <4>;
101 clock-frequency = <48000000>;
102 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
106 compatible = "ti,am654-uart";
108 reg-shift = <2>;
109 reg-io-width = <4>;
111 clock-frequency = <48000000>;
112 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
116 compatible = "ti,am654-sa2ul";
118 power-domains = <&k3_pds 136 TI_SCI_PD_EXCLUSIVE>;
119 #address-cells = <2>;
120 #size-cells = <2>;
126 dma-names = "tx", "rx1", "rx2";
127 dma-coherent;
130 compatible = "inside-secure,safexcel-eip76";
138 compatible = "pinctrl-single";
140 #pinctrl-cells = <1>;
141 pinctrl-single,register-width = <32>;
142 pinctrl-single,function-mask = <0xffffffff>;
146 compatible = "pinctrl-single";
148 #pinctrl-cells = <1>;
149 pinctrl-single,register-width = <32>;
150 pinctrl-single,function-mask = <0xffffffff>;
154 compatible = "ti,am654-i2c", "ti,omap4-i2c";
157 #address-cells = <1>;
158 #size-cells = <0>;
159 clock-names = "fck";
161 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
165 compatible = "ti,am654-i2c", "ti,omap4-i2c";
168 #address-cells = <1>;
169 #size-cells = <0>;
170 clock-names = "fck";
172 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
176 compatible = "ti,am654-i2c", "ti,omap4-i2c";
179 #address-cells = <1>;
180 #size-cells = <0>;
181 clock-names = "fck";
183 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
187 compatible = "ti,am654-i2c", "ti,omap4-i2c";
190 #address-cells = <1>;
191 #size-cells = <0>;
192 clock-names = "fck";
194 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
198 compatible = "ti,am654-ecap", "ti,am3352-ecap";
199 #pwm-cells = <3>;
201 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
203 clock-names = "fck";
207 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
211 power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
212 #address-cells = <1>;
213 #size-cells = <0>;
215 dma-names = "tx0", "rx0";
219 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
223 power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>;
224 #address-cells = <1>;
225 #size-cells = <0>;
226 assigned-clocks = <&k3_clks 137 1>;
227 assigned-clock-rates = <48000000>;
231 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
235 power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
236 #address-cells = <1>;
237 #size-cells = <0>;
241 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
245 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
246 #address-cells = <1>;
247 #size-cells = <0>;
251 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
255 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
256 #address-cells = <1>;
257 #size-cells = <0>;
261 compatible = "ti,am654-sdhci-5.1";
263 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
265 clock-names = "clk_ahb", "clk_xin";
267 mmc-ddr-1_8v;
268 mmc-hs200-1_8v;
269 ti,otap-del-sel-legacy = <0x0>;
270 ti,otap-del-sel-mmc-hs = <0x0>;
271 ti,otap-del-sel-sd-hs = <0x0>;
272 ti,otap-del-sel-sdr12 = <0x0>;
273 ti,otap-del-sel-sdr25 = <0x0>;
274 ti,otap-del-sel-sdr50 = <0x8>;
275 ti,otap-del-sel-sdr104 = <0x7>;
276 ti,otap-del-sel-ddr50 = <0x5>;
277 ti,otap-del-sel-ddr52 = <0x5>;
278 ti,otap-del-sel-hs200 = <0x5>;
279 ti,otap-del-sel-hs400 = <0x0>;
280 ti,trm-icp = <0x8>;
281 dma-coherent;
285 compatible = "ti,am654-sdhci-5.1";
287 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
289 clock-names = "clk_ahb", "clk_xin";
291 ti,otap-del-sel-legacy = <0x0>;
292 ti,otap-del-sel-mmc-hs = <0x0>;
293 ti,otap-del-sel-sd-hs = <0x0>;
294 ti,otap-del-sel-sdr12 = <0x0>;
295 ti,otap-del-sel-sdr25 = <0x0>;
296 ti,otap-del-sel-sdr50 = <0x8>;
297 ti,otap-del-sel-sdr104 = <0x7>;
298 ti,otap-del-sel-ddr50 = <0x4>;
299 ti,otap-del-sel-ddr52 = <0x4>;
300 ti,otap-del-sel-hs200 = <0x7>;
301 ti,clkbuf-sel = <0x7>;
302 ti,otap-del-sel = <0x2>;
303 ti,trm-icp = <0x8>;
304 dma-coherent;
305 no-1-8-v;
308 scm_conf: scm-conf@100000 {
309 compatible = "syscon", "simple-mfd";
311 #address-cells = <1>;
312 #size-cells = <1>;
315 pcie0_mode: pcie-mode@4060 {
320 pcie1_mode: pcie-mode@4070 {
325 pcie_devid: pcie-devid@210 {
340 serdes_mux: mux-controller {
341 compatible = "mmio-mux";
342 #mux-control-cells = <1>;
343 mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
347 dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 {
353 compatible = "ti,am654-ehrpwm-tbclk", "syscon";
355 #clock-cells = <1>;
360 compatible = "ti,am654-dwc3";
362 #address-cells = <1>;
363 #size-cells = <1>;
366 dma-coherent;
367 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
369 assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
370 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
379 interrupt-names = "peripheral",
382 maximum-speed = "high-speed";
385 phy-names = "usb2-phy";
391 compatible = "ti,am654-usb2", "ti,omap-usb2";
393 syscon-phy-power = <&scm_conf 0x4000>;
395 clock-names = "wkupclk", "refclk";
396 #phy-cells = <0>;
400 compatible = "ti,am654-dwc3";
402 #address-cells = <1>;
403 #size-cells = <1>;
406 dma-coherent;
407 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
409 assigned-clocks = <&k3_clks 152 2>;
410 assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
418 interrupt-names = "peripheral",
421 maximum-speed = "high-speed";
424 phy-names = "usb2-phy";
429 compatible = "ti,am654-usb2", "ti,omap-usb2";
431 syscon-phy-power = <&scm_conf 0x4020>;
433 clock-names = "wkupclk", "refclk";
434 #phy-cells = <0>;
437 intr_main_gpio: interrupt-controller0 {
438 compatible = "ti,sci-intr";
439 ti,intr-trigger-type = <1>;
440 interrupt-controller;
441 interrupt-parent = <&gic500>;
442 #interrupt-cells = <1>;
444 ti,sci-dev-id = <100>;
445 ti,interrupt-ranges = <0 392 32>;
448 main-navss {
449 compatible = "simple-mfd";
450 #address-cells = <2>;
451 #size-cells = <2>;
453 dma-coherent;
454 dma-ranges;
456 ti,sci-dev-id = <118>;
458 intr_main_navss: interrupt-controller1 {
459 compatible = "ti,sci-intr";
460 ti,intr-trigger-type = <4>;
461 interrupt-controller;
462 interrupt-parent = <&gic500>;
463 #interrupt-cells = <1>;
465 ti,sci-dev-id = <182>;
466 ti,interrupt-ranges = <0 64 64>,
470 inta_main_udmass: interrupt-controller@33d00000 {
471 compatible = "ti,sci-inta";
473 interrupt-controller;
474 interrupt-parent = <&intr_main_navss>;
475 msi-controller;
477 ti,sci-dev-id = <179>;
478 ti,interrupt-ranges = <0 0 256>;
482 compatible = "ti,am654-secure-proxy";
483 #mbox-cells = <1>;
484 reg-names = "target_data", "rt", "scfg";
488 interrupt-names = "rx_011";
493 compatible = "ti,am654-hwspinlock";
495 #hwlock-cells = <1>;
499 compatible = "ti,am654-mailbox";
501 #mbox-cells = <1>;
502 ti,mbox-num-users = <4>;
503 ti,mbox-num-fifos = <16>;
504 interrupt-parent = <&intr_main_navss>;
508 compatible = "ti,am654-mailbox";
510 #mbox-cells = <1>;
511 ti,mbox-num-users = <4>;
512 ti,mbox-num-fifos = <16>;
513 interrupt-parent = <&intr_main_navss>;
517 compatible = "ti,am654-mailbox";
519 #mbox-cells = <1>;
520 ti,mbox-num-users = <4>;
521 ti,mbox-num-fifos = <16>;
522 interrupt-parent = <&intr_main_navss>;
526 compatible = "ti,am654-mailbox";
528 #mbox-cells = <1>;
529 ti,mbox-num-users = <4>;
530 ti,mbox-num-fifos = <16>;
531 interrupt-parent = <&intr_main_navss>;
535 compatible = "ti,am654-mailbox";
537 #mbox-cells = <1>;
538 ti,mbox-num-users = <4>;
539 ti,mbox-num-fifos = <16>;
540 interrupt-parent = <&intr_main_navss>;
544 compatible = "ti,am654-mailbox";
546 #mbox-cells = <1>;
547 ti,mbox-num-users = <4>;
548 ti,mbox-num-fifos = <16>;
549 interrupt-parent = <&intr_main_navss>;
553 compatible = "ti,am654-mailbox";
555 #mbox-cells = <1>;
556 ti,mbox-num-users = <4>;
557 ti,mbox-num-fifos = <16>;
558 interrupt-parent = <&intr_main_navss>;
562 compatible = "ti,am654-mailbox";
564 #mbox-cells = <1>;
565 ti,mbox-num-users = <4>;
566 ti,mbox-num-fifos = <16>;
567 interrupt-parent = <&intr_main_navss>;
571 compatible = "ti,am654-mailbox";
573 #mbox-cells = <1>;
574 ti,mbox-num-users = <4>;
575 ti,mbox-num-fifos = <16>;
576 interrupt-parent = <&intr_main_navss>;
580 compatible = "ti,am654-mailbox";
582 #mbox-cells = <1>;
583 ti,mbox-num-users = <4>;
584 ti,mbox-num-fifos = <16>;
585 interrupt-parent = <&intr_main_navss>;
589 compatible = "ti,am654-mailbox";
591 #mbox-cells = <1>;
592 ti,mbox-num-users = <4>;
593 ti,mbox-num-fifos = <16>;
594 interrupt-parent = <&intr_main_navss>;
598 compatible = "ti,am654-mailbox";
600 #mbox-cells = <1>;
601 ti,mbox-num-users = <4>;
602 ti,mbox-num-fifos = <16>;
603 interrupt-parent = <&intr_main_navss>;
607 compatible = "ti,am654-navss-ringacc";
612 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
613 ti,num-rings = <818>;
614 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
615 ti,dma-ring-reset-quirk;
617 ti,sci-dev-id = <187>;
618 msi-parent = <&inta_main_udmass>;
621 main_udmap: dma-controller@31150000 {
622 compatible = "ti,am654-navss-main-udmap";
626 reg-names = "gcfg", "rchanrt", "tchanrt";
627 msi-parent = <&inta_main_udmass>;
628 #dma-cells = <1>;
631 ti,sci-dev-id = <188>;
634 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
636 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
638 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
642 compatible = "ti,am65-cpts";
644 reg-names = "cpts";
646 clock-names = "cpts";
647 interrupts-extended = <&intr_main_navss 391>;
648 interrupt-names = "cpts";
649 ti,cpts-periodic-outputs = <6>;
650 ti,cpts-ext-ts-inputs = <8>;
652 main_cpts_mux: refclk-mux {
653 #clock-cells = <0>;
658 assigned-clocks = <&main_cpts_mux>;
659 assigned-clock-parents = <&k3_clks 118 5>;
665 compatible = "ti,am654-gpio", "ti,keystone-gpio";
667 gpio-controller;
668 #gpio-cells = <2>;
669 interrupt-parent = <&intr_main_gpio>;
671 interrupt-controller;
672 #interrupt-cells = <2>;
674 ti,davinci-gpio-unbanked = <0>;
676 clock-names = "gpio";
680 compatible = "ti,am654-gpio", "ti,keystone-gpio";
682 gpio-controller;
683 #gpio-cells = <2>;
684 interrupt-parent = <&intr_main_gpio>;
686 interrupt-controller;
687 #interrupt-cells = <2>;
689 ti,davinci-gpio-unbanked = <0>;
691 clock-names = "gpio";
695 compatible = "ti,am654-pcie-rc";
697 reg-names = "app", "dbics", "config", "atu";
698 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
699 #address-cells = <3>;
700 #size-cells = <2>;
703 ti,syscon-pcie-id = <&pcie_devid>;
704 ti,syscon-pcie-mode = <&pcie0_mode>;
705 bus-range = <0x0 0xff>;
706 num-viewport = <16>;
707 max-link-speed = <2>;
708 dma-coherent;
710 msi-map = <0x0 &gic_its 0x0 0x10000>;
713 pcie0_ep: pcie-ep@5500000 {
714 compatible = "ti,am654-pcie-ep";
716 reg-names = "app", "dbics", "addr_space", "atu";
717 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
718 ti,syscon-pcie-mode = <&pcie0_mode>;
719 num-ib-windows = <16>;
720 num-ob-windows = <16>;
721 max-link-speed = <2>;
722 dma-coherent;
727 compatible = "ti,am654-pcie-rc";
729 reg-names = "app", "dbics", "config", "atu";
730 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
731 #address-cells = <3>;
732 #size-cells = <2>;
735 ti,syscon-pcie-id = <&pcie_devid>;
736 ti,syscon-pcie-mode = <&pcie1_mode>;
737 bus-range = <0x0 0xff>;
738 num-viewport = <16>;
739 max-link-speed = <2>;
740 dma-coherent;
742 msi-map = <0x0 &gic_its 0x10000 0x10000>;
745 pcie1_ep: pcie-ep@5600000 {
746 compatible = "ti,am654-pcie-ep";
748 reg-names = "app", "dbics", "addr_space", "atu";
749 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
750 ti,syscon-pcie-mode = <&pcie1_mode>;
751 num-ib-windows = <16>;
752 num-ob-windows = <16>;
753 max-link-speed = <2>;
754 dma-coherent;
759 compatible = "ti,am33xx-mcasp-audio";
762 reg-names = "mpu","dat";
765 interrupt-names = "tx", "rx";
768 dma-names = "tx", "rx";
771 clock-names = "fck";
772 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
778 compatible = "ti,am33xx-mcasp-audio";
781 reg-names = "mpu","dat";
784 interrupt-names = "tx", "rx";
787 dma-names = "tx", "rx";
790 clock-names = "fck";
791 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
797 compatible = "ti,am33xx-mcasp-audio";
800 reg-names = "mpu","dat";
803 interrupt-names = "tx", "rx";
806 dma-names = "tx", "rx";
809 clock-names = "fck";
810 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
816 compatible = "ti,am654-cal";
819 reg-names = "cal_top",
822 ti,camerrx-control = <&scm_conf 0x40c0>;
823 clock-names = "fck";
825 power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>;
828 #address-cells = <1>;
829 #size-cells = <0>;
838 compatible = "ti,am65x-dss";
846 reg-names = "common", "vidl1", "vid",
849 ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
851 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
856 clock-names = "fck", "vp1", "vp2";
860 * DIV1. See "Figure 12-3365. DSS Integration"
863 assigned-clocks = <&k3_clks 67 2>;
864 assigned-clock-parents = <&k3_clks 67 5>;
871 #address-cells = <1>;
872 #size-cells = <0>;
877 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
878 #pwm-cells = <3>;
880 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
882 clock-names = "tbclk", "fck";
886 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
887 #pwm-cells = <3>;
889 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
891 clock-names = "tbclk", "fck";
895 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
896 #pwm-cells = <3>;
898 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
900 clock-names = "tbclk", "fck";
904 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
905 #pwm-cells = <3>;
907 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
909 clock-names = "tbclk", "fck";
913 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
914 #pwm-cells = <3>;
916 power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
918 clock-names = "tbclk", "fck";
922 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
923 #pwm-cells = <3>;
925 power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
927 clock-names = "tbclk", "fck";