Lines Matching +full:phy +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/thermal/thermal.h>
13 compatible = "socionext,uniphier-pxs3";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <0>;
22 cpu-map {
41 compatible = "arm,cortex-a53";
44 enable-method = "psci";
45 operating-points-v2 = <&cluster0_opp>;
46 #cooling-cells = <2>;
51 compatible = "arm,cortex-a53";
54 enable-method = "psci";
55 operating-points-v2 = <&cluster0_opp>;
56 #cooling-cells = <2>;
61 compatible = "arm,cortex-a53";
64 enable-method = "psci";
65 operating-points-v2 = <&cluster0_opp>;
66 #cooling-cells = <2>;
71 compatible = "arm,cortex-a53";
74 enable-method = "psci";
75 operating-points-v2 = <&cluster0_opp>;
76 #cooling-cells = <2>;
80 cluster0_opp: opp-table {
81 compatible = "operating-points-v2";
82 opp-shared;
84 opp-250000000 {
85 opp-hz = /bits/ 64 <250000000>;
86 clock-latency-ns = <300>;
88 opp-325000000 {
89 opp-hz = /bits/ 64 <325000000>;
90 clock-latency-ns = <300>;
92 opp-500000000 {
93 opp-hz = /bits/ 64 <500000000>;
94 clock-latency-ns = <300>;
96 opp-650000000 {
97 opp-hz = /bits/ 64 <650000000>;
98 clock-latency-ns = <300>;
100 opp-666667000 {
101 opp-hz = /bits/ 64 <666667000>;
102 clock-latency-ns = <300>;
104 opp-866667000 {
105 opp-hz = /bits/ 64 <866667000>;
106 clock-latency-ns = <300>;
108 opp-1000000000 {
109 opp-hz = /bits/ 64 <1000000000>;
110 clock-latency-ns = <300>;
112 opp-1300000000 {
113 opp-hz = /bits/ 64 <1300000000>;
114 clock-latency-ns = <300>;
119 compatible = "arm,psci-1.0";
125 compatible = "fixed-clock";
126 #clock-cells = <0>;
127 clock-frequency = <25000000>;
131 emmc_pwrseq: emmc-pwrseq {
132 compatible = "mmc-pwrseq-emmc";
133 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>;
137 compatible = "arm,armv8-timer";
144 thermal-zones {
145 cpu-thermal {
146 polling-delay-passive = <250>; /* 250ms */
147 polling-delay = <1000>; /* 1000ms */
148 thermal-sensors = <&pvtctl>;
151 cpu_crit: cpu-crit {
156 cpu_alert: cpu-alert {
163 cooling-maps {
166 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
175 reserved-memory {
176 #address-cells = <2>;
177 #size-cells = <2>;
180 secure-memory@81000000 {
182 no-map;
187 compatible = "simple-bus";
188 #address-cells = <1>;
189 #size-cells = <1>;
193 compatible = "socionext,uniphier-scssi";
196 #address-cells = <1>;
197 #size-cells = <0>;
199 pinctrl-names = "default";
200 pinctrl-0 = <&pinctrl_spi0>;
206 compatible = "socionext,uniphier-scssi";
209 #address-cells = <1>;
210 #size-cells = <0>;
212 pinctrl-names = "default";
213 pinctrl-0 = <&pinctrl_spi1>;
219 compatible = "socionext,uniphier-uart";
223 pinctrl-names = "default";
224 pinctrl-0 = <&pinctrl_uart0>;
230 compatible = "socionext,uniphier-uart";
234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_uart1>;
241 compatible = "socionext,uniphier-uart";
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_uart2>;
252 compatible = "socionext,uniphier-uart";
256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_uart3>;
263 compatible = "socionext,uniphier-gpio";
265 interrupt-parent = <&aidet>;
266 interrupt-controller;
267 #interrupt-cells = <2>;
268 gpio-controller;
269 #gpio-cells = <2>;
270 gpio-ranges = <&pinctrl 0 0 0>,
273 gpio-ranges-group-names = "gpio_range0",
277 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
282 compatible = "socionext,uniphier-fi2c";
285 #address-cells = <1>;
286 #size-cells = <0>;
288 pinctrl-names = "default";
289 pinctrl-0 = <&pinctrl_i2c0>;
292 clock-frequency = <100000>;
296 compatible = "socionext,uniphier-fi2c";
299 #address-cells = <1>;
300 #size-cells = <0>;
302 pinctrl-names = "default";
303 pinctrl-0 = <&pinctrl_i2c1>;
306 clock-frequency = <100000>;
310 compatible = "socionext,uniphier-fi2c";
313 #address-cells = <1>;
314 #size-cells = <0>;
316 pinctrl-names = "default";
317 pinctrl-0 = <&pinctrl_i2c2>;
320 clock-frequency = <100000>;
324 compatible = "socionext,uniphier-fi2c";
327 #address-cells = <1>;
328 #size-cells = <0>;
330 pinctrl-names = "default";
331 pinctrl-0 = <&pinctrl_i2c3>;
334 clock-frequency = <100000>;
337 /* chip-internal connection for HDMI */
339 compatible = "socionext,uniphier-fi2c";
341 #address-cells = <1>;
342 #size-cells = <0>;
346 clock-frequency = <400000>;
349 system_bus: system-bus@58c00000 {
350 compatible = "socionext,uniphier-system-bus";
353 #address-cells = <2>;
354 #size-cells = <1>;
355 pinctrl-names = "default";
356 pinctrl-0 = <&pinctrl_system_bus>;
360 compatible = "socionext,uniphier-smpctrl";
365 compatible = "socionext,uniphier-pxs3-sdctrl",
366 "simple-mfd", "syscon";
370 compatible = "socionext,uniphier-pxs3-sd-clock";
371 #clock-cells = <1>;
375 compatible = "socionext,uniphier-pxs3-sd-reset";
376 #reset-cells = <1>;
381 compatible = "socionext,uniphier-pxs3-perictrl",
382 "simple-mfd", "syscon";
386 compatible = "socionext,uniphier-pxs3-peri-clock";
387 #clock-cells = <1>;
391 compatible = "socionext,uniphier-pxs3-peri-reset";
392 #reset-cells = <1>;
397 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
400 pinctrl-names = "default";
401 pinctrl-0 = <&pinctrl_emmc>;
404 bus-width = <8>;
405 mmc-ddr-1_8v;
406 mmc-hs200-1_8v;
407 mmc-pwrseq = <&emmc_pwrseq>;
408 cdns,phy-input-delay-legacy = <9>;
409 cdns,phy-input-delay-mmc-highspeed = <2>;
410 cdns,phy-input-delay-mmc-ddr = <3>;
411 cdns,phy-dll-delay-sdclk = <21>;
412 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
416 compatible = "socionext,uniphier-sd-v3.1.1";
420 pinctrl-names = "default", "uhs";
421 pinctrl-0 = <&pinctrl_sd>;
422 pinctrl-1 = <&pinctrl_sd_uhs>;
424 reset-names = "host";
426 bus-width = <4>;
427 cap-sd-highspeed;
428 sd-uhs-sdr12;
429 sd-uhs-sdr25;
430 sd-uhs-sdr50;
433 soc_glue: soc-glue@5f800000 {
434 compatible = "socionext,uniphier-pxs3-soc-glue",
435 "simple-mfd", "syscon";
439 compatible = "socionext,uniphier-pxs3-pinctrl";
443 soc-glue@5f900000 {
444 compatible = "socionext,uniphier-pxs3-soc-glue-debug",
445 "simple-mfd";
446 #address-cells = <1>;
447 #size-cells = <1>;
451 compatible = "socionext,uniphier-efuse";
456 compatible = "socionext,uniphier-efuse";
458 #address-cells = <1>;
459 #size-cells = <1>;
505 xdmac: dma-controller@5fc10000 {
506 compatible = "socionext,uniphier-xdmac";
509 dma-channels = <16>;
510 #dma-cells = <2>;
513 aidet: interrupt-controller@5fc20000 {
514 compatible = "socionext,uniphier-pxs3-aidet";
516 interrupt-controller;
517 #interrupt-cells = <2>;
520 gic: interrupt-controller@5fe00000 {
521 compatible = "arm,gic-v3";
524 interrupt-controller;
525 #interrupt-cells = <3>;
530 compatible = "socionext,uniphier-pxs3-sysctrl",
531 "simple-mfd", "syscon";
535 compatible = "socionext,uniphier-pxs3-clock";
536 #clock-cells = <1>;
540 compatible = "socionext,uniphier-pxs3-reset";
541 #reset-cells = <1>;
545 compatible = "socionext,uniphier-wdt";
549 compatible = "socionext,uniphier-pxs3-thermal";
551 #thermal-sensor-cells = <0>;
552 socionext,tmod-calibration = <0x0f22 0x68ee>;
557 compatible = "socionext,uniphier-pxs3-ave4";
561 pinctrl-names = "default";
562 pinctrl-0 = <&pinctrl_ether_rgmii>;
563 clock-names = "ether";
565 reset-names = "ether";
567 phy-mode = "rgmii";
568 local-mac-address = [00 00 00 00 00 00];
569 socionext,syscon-phy-mode = <&soc_glue 0>;
572 #address-cells = <1>;
573 #size-cells = <0>;
578 compatible = "socionext,uniphier-pxs3-ave4";
582 pinctrl-names = "default";
583 pinctrl-0 = <&pinctrl_ether1_rgmii>;
584 clock-names = "ether";
586 reset-names = "ether";
588 phy-mode = "rgmii";
589 local-mac-address = [00 00 00 00 00 00];
590 socionext,syscon-phy-mode = <&soc_glue 1>;
593 #address-cells = <1>;
594 #size-cells = <0>;
599 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
602 interrupt-names = "host", "peripheral";
604 pinctrl-names = "default";
605 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
606 clock-names = "ref", "bus_early", "suspend";
614 usb-glue@65b00000 {
615 compatible = "socionext,uniphier-pxs3-dwc3-glue",
616 "simple-mfd";
617 #address-cells = <1>;
618 #size-cells = <1>;
622 compatible = "socionext,uniphier-pxs3-usb3-reset";
624 #reset-cells = <1>;
625 clock-names = "link";
627 reset-names = "link";
632 compatible = "socionext,uniphier-pxs3-usb3-regulator";
634 clock-names = "link";
636 reset-names = "link";
641 compatible = "socionext,uniphier-pxs3-usb3-regulator";
643 clock-names = "link";
645 reset-names = "link";
649 usb0_hsphy0: hs-phy@200 {
650 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
652 #phy-cells = <0>;
653 clock-names = "link", "phy";
655 reset-names = "link", "phy";
657 vbus-supply = <&usb0_vbus0>;
658 nvmem-cell-names = "rterm", "sel_t", "hs_i";
659 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
663 usb0_hsphy1: hs-phy@210 {
664 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
666 #phy-cells = <0>;
667 clock-names = "link", "phy";
669 reset-names = "link", "phy";
671 vbus-supply = <&usb0_vbus1>;
672 nvmem-cell-names = "rterm", "sel_t", "hs_i";
673 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
677 usb0_ssphy0: ss-phy@300 {
678 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
680 #phy-cells = <0>;
681 clock-names = "link", "phy";
683 reset-names = "link", "phy";
685 vbus-supply = <&usb0_vbus0>;
688 usb0_ssphy1: ss-phy@310 {
689 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
691 #phy-cells = <0>;
692 clock-names = "link", "phy";
694 reset-names = "link", "phy";
696 vbus-supply = <&usb0_vbus1>;
701 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
704 interrupt-names = "host", "peripheral";
706 pinctrl-names = "default";
707 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
708 clock-names = "ref", "bus_early", "suspend";
716 usb-glue@65d00000 {
717 compatible = "socionext,uniphier-pxs3-dwc3-glue",
718 "simple-mfd";
719 #address-cells = <1>;
720 #size-cells = <1>;
724 compatible = "socionext,uniphier-pxs3-usb3-reset";
726 #reset-cells = <1>;
727 clock-names = "link";
729 reset-names = "link";
734 compatible = "socionext,uniphier-pxs3-usb3-regulator";
736 clock-names = "link";
738 reset-names = "link";
743 compatible = "socionext,uniphier-pxs3-usb3-regulator";
745 clock-names = "link";
747 reset-names = "link";
751 usb1_hsphy0: hs-phy@200 {
752 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
754 #phy-cells = <0>;
755 clock-names = "link", "phy", "phy-ext";
758 reset-names = "link", "phy";
760 vbus-supply = <&usb1_vbus0>;
761 nvmem-cell-names = "rterm", "sel_t", "hs_i";
762 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
766 usb1_hsphy1: hs-phy@210 {
767 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
769 #phy-cells = <0>;
770 clock-names = "link", "phy", "phy-ext";
773 reset-names = "link", "phy";
775 vbus-supply = <&usb1_vbus1>;
776 nvmem-cell-names = "rterm", "sel_t", "hs_i";
777 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
781 usb1_ssphy0: ss-phy@300 {
782 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
784 #phy-cells = <0>;
785 clock-names = "link", "phy", "phy-ext";
788 reset-names = "link", "phy";
790 vbus-supply = <&usb1_vbus0>;
795 compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
797 reg-names = "dbi", "link", "config";
800 #address-cells = <3>;
801 #size-cells = <2>;
804 num-lanes = <1>;
805 num-viewport = <1>;
806 bus-range = <0x0 0xff>;
811 /* non-prefetchable memory */
813 #interrupt-cells = <1>;
814 interrupt-names = "dma", "msi";
816 interrupt-map-mask = <0 0 0 7>;
817 interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
821 phy-names = "pcie-phy";
824 pcie_intc: legacy-interrupt-controller {
825 interrupt-controller;
826 #interrupt-cells = <1>;
827 interrupt-parent = <&gic>;
832 pcie_phy: phy@66038000 {
833 compatible = "socionext,uniphier-pxs3-pcie-phy";
835 #phy-cells = <0>;
836 clock-names = "link";
838 reset-names = "link";
843 nand: nand-controller@68000000 {
844 compatible = "socionext,uniphier-denali-nand-v5b";
846 reg-names = "nand_data", "denali_reg";
848 #address-cells = <1>;
849 #size-cells = <0>;
851 pinctrl-names = "default";
852 pinctrl-0 = <&pinctrl_nand>;
853 clock-names = "nand", "nand_x", "ecc";
855 reset-names = "nand", "reg";
861 #include "uniphier-pinctrl.dtsi"