Lines Matching +full:uniphier +full:- +full:uart
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD20 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/thermal/thermal.h>
13 compatible = "socionext,uniphier-ld20";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <0>;
22 cpu-map {
44 compatible = "arm,cortex-a72";
47 enable-method = "psci";
48 operating-points-v2 = <&cluster0_opp>;
49 #cooling-cells = <2>;
54 compatible = "arm,cortex-a72";
57 enable-method = "psci";
58 operating-points-v2 = <&cluster0_opp>;
59 #cooling-cells = <2>;
64 compatible = "arm,cortex-a53";
67 enable-method = "psci";
68 operating-points-v2 = <&cluster1_opp>;
69 #cooling-cells = <2>;
74 compatible = "arm,cortex-a53";
77 enable-method = "psci";
78 operating-points-v2 = <&cluster1_opp>;
79 #cooling-cells = <2>;
83 cluster0_opp: opp-table0 {
84 compatible = "operating-points-v2";
85 opp-shared;
87 opp-250000000 {
88 opp-hz = /bits/ 64 <250000000>;
89 clock-latency-ns = <300>;
91 opp-275000000 {
92 opp-hz = /bits/ 64 <275000000>;
93 clock-latency-ns = <300>;
95 opp-500000000 {
96 opp-hz = /bits/ 64 <500000000>;
97 clock-latency-ns = <300>;
99 opp-550000000 {
100 opp-hz = /bits/ 64 <550000000>;
101 clock-latency-ns = <300>;
103 opp-666667000 {
104 opp-hz = /bits/ 64 <666667000>;
105 clock-latency-ns = <300>;
107 opp-733334000 {
108 opp-hz = /bits/ 64 <733334000>;
109 clock-latency-ns = <300>;
111 opp-1000000000 {
112 opp-hz = /bits/ 64 <1000000000>;
113 clock-latency-ns = <300>;
115 opp-1100000000 {
116 opp-hz = /bits/ 64 <1100000000>;
117 clock-latency-ns = <300>;
121 cluster1_opp: opp-table1 {
122 compatible = "operating-points-v2";
123 opp-shared;
125 opp-250000000 {
126 opp-hz = /bits/ 64 <250000000>;
127 clock-latency-ns = <300>;
129 opp-275000000 {
130 opp-hz = /bits/ 64 <275000000>;
131 clock-latency-ns = <300>;
133 opp-500000000 {
134 opp-hz = /bits/ 64 <500000000>;
135 clock-latency-ns = <300>;
137 opp-550000000 {
138 opp-hz = /bits/ 64 <550000000>;
139 clock-latency-ns = <300>;
141 opp-666667000 {
142 opp-hz = /bits/ 64 <666667000>;
143 clock-latency-ns = <300>;
145 opp-733334000 {
146 opp-hz = /bits/ 64 <733334000>;
147 clock-latency-ns = <300>;
149 opp-1000000000 {
150 opp-hz = /bits/ 64 <1000000000>;
151 clock-latency-ns = <300>;
153 opp-1100000000 {
154 opp-hz = /bits/ 64 <1100000000>;
155 clock-latency-ns = <300>;
160 compatible = "arm,psci-1.0";
166 compatible = "fixed-clock";
167 #clock-cells = <0>;
168 clock-frequency = <25000000>;
172 emmc_pwrseq: emmc-pwrseq {
173 compatible = "mmc-pwrseq-emmc";
174 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
178 compatible = "arm,armv8-timer";
185 thermal-zones {
186 cpu-thermal {
187 polling-delay-passive = <250>; /* 250ms */
188 polling-delay = <1000>; /* 1000ms */
189 thermal-sensors = <&pvtctl>;
192 cpu_crit: cpu-crit {
197 cpu_alert: cpu-alert {
204 cooling-maps {
207 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
216 reserved-memory {
217 #address-cells = <2>;
218 #size-cells = <2>;
221 secure-memory@81000000 {
223 no-map;
228 compatible = "simple-bus";
229 #address-cells = <1>;
230 #size-cells = <1>;
234 compatible = "socionext,uniphier-scssi";
237 #address-cells = <1>;
238 #size-cells = <0>;
240 pinctrl-names = "default";
241 pinctrl-0 = <&pinctrl_spi0>;
247 compatible = "socionext,uniphier-scssi";
250 #address-cells = <1>;
251 #size-cells = <0>;
253 pinctrl-names = "default";
254 pinctrl-0 = <&pinctrl_spi1>;
260 compatible = "socionext,uniphier-scssi";
263 #address-cells = <1>;
264 #size-cells = <0>;
266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_spi2>;
273 compatible = "socionext,uniphier-scssi";
276 #address-cells = <1>;
277 #size-cells = <0>;
279 pinctrl-names = "default";
280 pinctrl-0 = <&pinctrl_spi3>;
286 compatible = "socionext,uniphier-uart";
290 pinctrl-names = "default";
291 pinctrl-0 = <&pinctrl_uart0>;
297 compatible = "socionext,uniphier-uart";
301 pinctrl-names = "default";
302 pinctrl-0 = <&pinctrl_uart1>;
308 compatible = "socionext,uniphier-uart";
312 pinctrl-names = "default";
313 pinctrl-0 = <&pinctrl_uart2>;
319 compatible = "socionext,uniphier-uart";
323 pinctrl-names = "default";
324 pinctrl-0 = <&pinctrl_uart3>;
330 compatible = "socionext,uniphier-gpio";
332 interrupt-parent = <&aidet>;
333 interrupt-controller;
334 #interrupt-cells = <2>;
335 gpio-controller;
336 #gpio-cells = <2>;
337 gpio-ranges = <&pinctrl 0 0 0>,
340 gpio-ranges-group-names = "gpio_range0",
344 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
349 compatible = "socionext,uniphier-ld20-aio";
352 pinctrl-names = "default";
353 pinctrl-0 = <&pinctrl_aout1>,
355 clock-names = "aio";
357 reset-names = "aio";
359 #sound-dai-cells = <1>;
374 dai-format = "i2s";
375 remote-endpoint = <&evea_line>;
386 dai-format = "i2s";
387 remote-endpoint = <&evea_hp>;
413 compatible = "socionext,uniphier-evea";
415 clock-names = "evea", "exiv";
417 reset-names = "evea", "exiv", "adamv";
419 #sound-dai-cells = <1>;
423 remote-endpoint = <&i2s_line>;
429 remote-endpoint = <&i2s_hp>;
435 compatible = "socionext,uniphier-ld20-adamv",
436 "simple-mfd", "syscon";
440 compatible = "socionext,uniphier-ld20-adamv-reset";
441 #reset-cells = <1>;
446 compatible = "socionext,uniphier-fi2c";
449 #address-cells = <1>;
450 #size-cells = <0>;
452 pinctrl-names = "default";
453 pinctrl-0 = <&pinctrl_i2c0>;
456 clock-frequency = <100000>;
460 compatible = "socionext,uniphier-fi2c";
463 #address-cells = <1>;
464 #size-cells = <0>;
466 pinctrl-names = "default";
467 pinctrl-0 = <&pinctrl_i2c1>;
470 clock-frequency = <100000>;
474 compatible = "socionext,uniphier-fi2c";
476 #address-cells = <1>;
477 #size-cells = <0>;
481 clock-frequency = <400000>;
485 compatible = "socionext,uniphier-fi2c";
488 #address-cells = <1>;
489 #size-cells = <0>;
491 pinctrl-names = "default";
492 pinctrl-0 = <&pinctrl_i2c3>;
495 clock-frequency = <100000>;
499 compatible = "socionext,uniphier-fi2c";
502 #address-cells = <1>;
503 #size-cells = <0>;
505 pinctrl-names = "default";
506 pinctrl-0 = <&pinctrl_i2c4>;
509 clock-frequency = <100000>;
513 compatible = "socionext,uniphier-fi2c";
515 #address-cells = <1>;
516 #size-cells = <0>;
520 clock-frequency = <400000>;
523 system_bus: system-bus@58c00000 {
524 compatible = "socionext,uniphier-system-bus";
527 #address-cells = <2>;
528 #size-cells = <1>;
529 pinctrl-names = "default";
530 pinctrl-0 = <&pinctrl_system_bus>;
534 compatible = "socionext,uniphier-smpctrl";
539 compatible = "socionext,uniphier-ld20-sdctrl",
540 "simple-mfd", "syscon";
544 compatible = "socionext,uniphier-ld20-sd-clock";
545 #clock-cells = <1>;
549 compatible = "socionext,uniphier-ld20-sd-reset";
550 #reset-cells = <1>;
555 compatible = "socionext,uniphier-ld20-perictrl",
556 "simple-mfd", "syscon";
560 compatible = "socionext,uniphier-ld20-peri-clock";
561 #clock-cells = <1>;
565 compatible = "socionext,uniphier-ld20-peri-reset";
566 #reset-cells = <1>;
571 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
574 pinctrl-names = "default";
575 pinctrl-0 = <&pinctrl_emmc>;
578 bus-width = <8>;
579 mmc-ddr-1_8v;
580 mmc-hs200-1_8v;
581 mmc-pwrseq = <&emmc_pwrseq>;
582 cdns,phy-input-delay-legacy = <9>;
583 cdns,phy-input-delay-mmc-highspeed = <2>;
584 cdns,phy-input-delay-mmc-ddr = <3>;
585 cdns,phy-dll-delay-sdclk = <21>;
586 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
590 compatible = "socionext,uniphier-sd-v3.1.1";
594 pinctrl-names = "default";
595 pinctrl-0 = <&pinctrl_sd>;
597 reset-names = "host";
599 bus-width = <4>;
600 cap-sd-highspeed;
603 soc_glue: soc-glue@5f800000 {
604 compatible = "socionext,uniphier-ld20-soc-glue",
605 "simple-mfd", "syscon";
609 compatible = "socionext,uniphier-ld20-pinctrl";
613 soc-glue@5f900000 {
614 compatible = "socionext,uniphier-ld20-soc-glue-debug",
615 "simple-mfd";
616 #address-cells = <1>;
617 #size-cells = <1>;
621 compatible = "socionext,uniphier-efuse";
626 compatible = "socionext,uniphier-efuse";
628 #address-cells = <1>;
629 #size-cells = <1>;
675 xdmac: dma-controller@5fc10000 {
676 compatible = "socionext,uniphier-xdmac";
679 dma-channels = <16>;
680 #dma-cells = <2>;
683 aidet: interrupt-controller@5fc20000 {
684 compatible = "socionext,uniphier-ld20-aidet";
686 interrupt-controller;
687 #interrupt-cells = <2>;
690 gic: interrupt-controller@5fe00000 {
691 compatible = "arm,gic-v3";
694 interrupt-controller;
695 #interrupt-cells = <3>;
700 compatible = "socionext,uniphier-ld20-sysctrl",
701 "simple-mfd", "syscon";
705 compatible = "socionext,uniphier-ld20-clock";
706 #clock-cells = <1>;
710 compatible = "socionext,uniphier-ld20-reset";
711 #reset-cells = <1>;
715 compatible = "socionext,uniphier-wdt";
719 compatible = "socionext,uniphier-ld20-thermal";
721 #thermal-sensor-cells = <0>;
722 socionext,tmod-calibration = <0x0f22 0x68ee>;
727 compatible = "socionext,uniphier-ld20-ave4";
731 pinctrl-names = "default";
732 pinctrl-0 = <&pinctrl_ether_rgmii>;
733 clock-names = "ether";
735 reset-names = "ether";
737 phy-mode = "rgmii";
738 local-mac-address = [00 00 00 00 00 00];
739 socionext,syscon-phy-mode = <&soc_glue 0>;
742 #address-cells = <1>;
743 #size-cells = <0>;
748 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
751 interrupt-names = "host";
753 pinctrl-names = "default";
754 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
756 clock-names = "ref", "bus_early", "suspend";
765 usb-glue@65b00000 {
766 compatible = "socionext,uniphier-ld20-dwc3-glue",
767 "simple-mfd";
768 #address-cells = <1>;
769 #size-cells = <1>;
773 compatible = "socionext,uniphier-ld20-usb3-reset";
775 #reset-cells = <1>;
776 clock-names = "link";
778 reset-names = "link";
783 compatible = "socionext,uniphier-ld20-usb3-regulator";
785 clock-names = "link";
787 reset-names = "link";
792 compatible = "socionext,uniphier-ld20-usb3-regulator";
794 clock-names = "link";
796 reset-names = "link";
801 compatible = "socionext,uniphier-ld20-usb3-regulator";
803 clock-names = "link";
805 reset-names = "link";
810 compatible = "socionext,uniphier-ld20-usb3-regulator";
812 clock-names = "link";
814 reset-names = "link";
818 usb_hsphy0: hs-phy@200 {
819 compatible = "socionext,uniphier-ld20-usb3-hsphy";
821 #phy-cells = <0>;
822 clock-names = "link", "phy";
824 reset-names = "link", "phy";
826 vbus-supply = <&usb_vbus0>;
827 nvmem-cell-names = "rterm", "sel_t", "hs_i";
828 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
832 usb_hsphy1: hs-phy@210 {
833 compatible = "socionext,uniphier-ld20-usb3-hsphy";
835 #phy-cells = <0>;
836 clock-names = "link", "phy";
838 reset-names = "link", "phy";
840 vbus-supply = <&usb_vbus1>;
841 nvmem-cell-names = "rterm", "sel_t", "hs_i";
842 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
846 usb_hsphy2: hs-phy@220 {
847 compatible = "socionext,uniphier-ld20-usb3-hsphy";
849 #phy-cells = <0>;
850 clock-names = "link", "phy";
852 reset-names = "link", "phy";
854 vbus-supply = <&usb_vbus2>;
855 nvmem-cell-names = "rterm", "sel_t", "hs_i";
856 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
860 usb_hsphy3: hs-phy@230 {
861 compatible = "socionext,uniphier-ld20-usb3-hsphy";
863 #phy-cells = <0>;
864 clock-names = "link", "phy";
866 reset-names = "link", "phy";
868 vbus-supply = <&usb_vbus3>;
869 nvmem-cell-names = "rterm", "sel_t", "hs_i";
870 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
874 usb_ssphy0: ss-phy@300 {
875 compatible = "socionext,uniphier-ld20-usb3-ssphy";
877 #phy-cells = <0>;
878 clock-names = "link", "phy";
880 reset-names = "link", "phy";
882 vbus-supply = <&usb_vbus0>;
885 usb_ssphy1: ss-phy@310 {
886 compatible = "socionext,uniphier-ld20-usb3-ssphy";
888 #phy-cells = <0>;
889 clock-names = "link", "phy";
891 reset-names = "link", "phy";
893 vbus-supply = <&usb_vbus1>;
898 compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
900 reg-names = "dbi", "link", "config";
903 #address-cells = <3>;
904 #size-cells = <2>;
907 num-lanes = <1>;
908 num-viewport = <1>;
909 bus-range = <0x0 0xff>;
914 /* non-prefetchable memory */
916 #interrupt-cells = <1>;
917 interrupt-names = "dma", "msi";
919 interrupt-map-mask = <0 0 0 7>;
920 interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
924 phy-names = "pcie-phy";
927 pcie_intc: legacy-interrupt-controller {
928 interrupt-controller;
929 #interrupt-cells = <1>;
930 interrupt-parent = <&gic>;
936 compatible = "socionext,uniphier-ld20-pcie-phy";
938 #phy-cells = <0>;
939 clock-names = "link";
941 reset-names = "link";
946 nand: nand-controller@68000000 {
947 compatible = "socionext,uniphier-denali-nand-v5b";
949 reg-names = "nand_data", "denali_reg";
951 #address-cells = <1>;
952 #size-cells = <0>;
954 pinctrl-names = "default";
955 pinctrl-0 = <&pinctrl_nand>;
956 clock-names = "nand", "nand_x", "ecc";
958 reset-names = "nand", "reg";
964 #include "uniphier-pinctrl.dtsi"
967 drive-strength = <4>; /* default: 3.5mA */
971 drive-strength = <5>; /* 5mA */
976 drive-strength = <4>; /* default: 3.5mA */
980 drive-strength = <11>; /* 11mA */