Lines Matching +full:uniphier +full:- +full:uart
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD11 SoC
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
12 compatible = "socionext,uniphier-ld11";
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <0>;
21 cpu-map {
34 compatible = "arm,cortex-a53";
37 enable-method = "psci";
38 operating-points-v2 = <&cluster0_opp>;
43 compatible = "arm,cortex-a53";
46 enable-method = "psci";
47 operating-points-v2 = <&cluster0_opp>;
51 cluster0_opp: opp-table {
52 compatible = "operating-points-v2";
53 opp-shared;
55 opp-245000000 {
56 opp-hz = /bits/ 64 <245000000>;
57 clock-latency-ns = <300>;
59 opp-250000000 {
60 opp-hz = /bits/ 64 <250000000>;
61 clock-latency-ns = <300>;
63 opp-490000000 {
64 opp-hz = /bits/ 64 <490000000>;
65 clock-latency-ns = <300>;
67 opp-500000000 {
68 opp-hz = /bits/ 64 <500000000>;
69 clock-latency-ns = <300>;
71 opp-653334000 {
72 opp-hz = /bits/ 64 <653334000>;
73 clock-latency-ns = <300>;
75 opp-666667000 {
76 opp-hz = /bits/ 64 <666667000>;
77 clock-latency-ns = <300>;
79 opp-980000000 {
80 opp-hz = /bits/ 64 <980000000>;
81 clock-latency-ns = <300>;
86 compatible = "arm,psci-1.0";
92 compatible = "fixed-clock";
93 #clock-cells = <0>;
94 clock-frequency = <25000000>;
98 emmc_pwrseq: emmc-pwrseq {
99 compatible = "mmc-pwrseq-emmc";
100 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
104 compatible = "arm,armv8-timer";
111 reserved-memory {
112 #address-cells = <2>;
113 #size-cells = <2>;
116 secure-memory@81000000 {
118 no-map;
123 compatible = "simple-bus";
124 #address-cells = <1>;
125 #size-cells = <1>;
129 compatible = "socionext,uniphier-scssi";
132 #address-cells = <1>;
133 #size-cells = <0>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_spi0>;
142 compatible = "socionext,uniphier-scssi";
145 #address-cells = <1>;
146 #size-cells = <0>;
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_spi1>;
155 compatible = "socionext,uniphier-uart";
159 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_uart0>;
166 compatible = "socionext,uniphier-uart";
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_uart1>;
177 compatible = "socionext,uniphier-uart";
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_uart2>;
188 compatible = "socionext,uniphier-uart";
192 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_uart3>;
199 compatible = "socionext,uniphier-gpio";
201 interrupt-parent = <&aidet>;
202 interrupt-controller;
203 #interrupt-cells = <2>;
204 gpio-controller;
205 #gpio-cells = <2>;
206 gpio-ranges = <&pinctrl 0 0 0>,
212 gpio-ranges-group-names = "gpio_range0",
219 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
224 compatible = "socionext,uniphier-ld11-aio";
227 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_aout1>,
230 clock-names = "aio";
232 reset-names = "aio";
234 #sound-dai-cells = <1>;
249 dai-format = "i2s";
250 remote-endpoint = <&evea_line>;
261 dai-format = "i2s";
262 remote-endpoint = <&evea_hp>;
288 compatible = "socionext,uniphier-evea";
290 clock-names = "evea", "exiv";
292 reset-names = "evea", "exiv", "adamv";
294 #sound-dai-cells = <1>;
298 remote-endpoint = <&i2s_line>;
304 remote-endpoint = <&i2s_hp>;
310 compatible = "socionext,uniphier-ld11-adamv",
311 "simple-mfd", "syscon";
315 compatible = "socionext,uniphier-ld11-adamv-reset";
316 #reset-cells = <1>;
321 compatible = "socionext,uniphier-fi2c";
324 #address-cells = <1>;
325 #size-cells = <0>;
327 pinctrl-names = "default";
328 pinctrl-0 = <&pinctrl_i2c0>;
331 clock-frequency = <100000>;
335 compatible = "socionext,uniphier-fi2c";
338 #address-cells = <1>;
339 #size-cells = <0>;
341 pinctrl-names = "default";
342 pinctrl-0 = <&pinctrl_i2c1>;
345 clock-frequency = <100000>;
349 compatible = "socionext,uniphier-fi2c";
351 #address-cells = <1>;
352 #size-cells = <0>;
356 clock-frequency = <400000>;
360 compatible = "socionext,uniphier-fi2c";
363 #address-cells = <1>;
364 #size-cells = <0>;
366 pinctrl-names = "default";
367 pinctrl-0 = <&pinctrl_i2c3>;
370 clock-frequency = <100000>;
374 compatible = "socionext,uniphier-fi2c";
377 #address-cells = <1>;
378 #size-cells = <0>;
380 pinctrl-names = "default";
381 pinctrl-0 = <&pinctrl_i2c4>;
384 clock-frequency = <100000>;
388 compatible = "socionext,uniphier-fi2c";
390 #address-cells = <1>;
391 #size-cells = <0>;
395 clock-frequency = <400000>;
398 system_bus: system-bus@58c00000 {
399 compatible = "socionext,uniphier-system-bus";
402 #address-cells = <2>;
403 #size-cells = <1>;
404 pinctrl-names = "default";
405 pinctrl-0 = <&pinctrl_system_bus>;
409 compatible = "socionext,uniphier-smpctrl";
414 compatible = "socionext,uniphier-ld11-sdctrl",
415 "simple-mfd", "syscon";
419 compatible = "socionext,uniphier-ld11-sd-reset";
420 #reset-cells = <1>;
425 compatible = "socionext,uniphier-ld11-perictrl",
426 "simple-mfd", "syscon";
430 compatible = "socionext,uniphier-ld11-peri-clock";
431 #clock-cells = <1>;
435 compatible = "socionext,uniphier-ld11-peri-reset";
436 #reset-cells = <1>;
441 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
444 pinctrl-names = "default";
445 pinctrl-0 = <&pinctrl_emmc>;
448 bus-width = <8>;
449 mmc-ddr-1_8v;
450 mmc-hs200-1_8v;
451 mmc-pwrseq = <&emmc_pwrseq>;
452 cdns,phy-input-delay-legacy = <9>;
453 cdns,phy-input-delay-mmc-highspeed = <2>;
454 cdns,phy-input-delay-mmc-ddr = <3>;
455 cdns,phy-dll-delay-sdclk = <21>;
456 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
460 compatible = "socionext,uniphier-ehci", "generic-ehci";
464 pinctrl-names = "default";
465 pinctrl-0 = <&pinctrl_usb0>;
470 phy-names = "usb";
472 has-transaction-translator;
476 compatible = "socionext,uniphier-ehci", "generic-ehci";
480 pinctrl-names = "default";
481 pinctrl-0 = <&pinctrl_usb1>;
486 phy-names = "usb";
488 has-transaction-translator;
492 compatible = "socionext,uniphier-ehci", "generic-ehci";
496 pinctrl-names = "default";
497 pinctrl-0 = <&pinctrl_usb2>;
502 phy-names = "usb";
504 has-transaction-translator;
508 compatible = "socionext,uniphier-ld11-mioctrl",
509 "simple-mfd", "syscon";
513 compatible = "socionext,uniphier-ld11-mio-clock";
514 #clock-cells = <1>;
518 compatible = "socionext,uniphier-ld11-mio-reset";
519 #reset-cells = <1>;
524 soc_glue: soc-glue@5f800000 {
525 compatible = "socionext,uniphier-ld11-soc-glue",
526 "simple-mfd", "syscon";
530 compatible = "socionext,uniphier-ld11-pinctrl";
533 usb-phy {
534 compatible = "socionext,uniphier-ld11-usb2-phy";
535 #address-cells = <1>;
536 #size-cells = <0>;
540 #phy-cells = <0>;
545 #phy-cells = <0>;
550 #phy-cells = <0>;
555 soc-glue@5f900000 {
556 compatible = "socionext,uniphier-ld11-soc-glue-debug",
557 "simple-mfd";
558 #address-cells = <1>;
559 #size-cells = <1>;
563 compatible = "socionext,uniphier-efuse";
568 compatible = "socionext,uniphier-efuse";
573 xdmac: dma-controller@5fc10000 {
574 compatible = "socionext,uniphier-xdmac";
577 dma-channels = <16>;
578 #dma-cells = <2>;
581 aidet: interrupt-controller@5fc20000 {
582 compatible = "socionext,uniphier-ld11-aidet";
584 interrupt-controller;
585 #interrupt-cells = <2>;
588 gic: interrupt-controller@5fe00000 {
589 compatible = "arm,gic-v3";
592 interrupt-controller;
593 #interrupt-cells = <3>;
598 compatible = "socionext,uniphier-ld11-sysctrl",
599 "simple-mfd", "syscon";
603 compatible = "socionext,uniphier-ld11-clock";
604 #clock-cells = <1>;
608 compatible = "socionext,uniphier-ld11-reset";
609 #reset-cells = <1>;
613 compatible = "socionext,uniphier-wdt";
618 compatible = "socionext,uniphier-ld11-ave4";
622 clock-names = "ether";
624 reset-names = "ether";
626 phy-mode = "internal";
627 local-mac-address = [00 00 00 00 00 00];
628 socionext,syscon-phy-mode = <&soc_glue 0>;
631 #address-cells = <1>;
632 #size-cells = <0>;
636 nand: nand-controller@68000000 {
637 compatible = "socionext,uniphier-denali-nand-v5b";
639 reg-names = "nand_data", "denali_reg";
641 #address-cells = <1>;
642 #size-cells = <0>;
644 pinctrl-names = "default";
645 pinctrl-0 = <&pinctrl_nand>;
646 clock-names = "nand", "nand_x", "ecc";
648 reset-names = "nand", "reg";
654 #include "uniphier-pinctrl.dtsi"
657 drive-strength = <4>; /* default: 4mA */
661 drive-strength = <8>; /* 8mA */