Lines Matching +full:ppi +full:- +full:partitions
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
43 #address-cells = <2>;
44 #size-cells = <0>;
46 cpu-map {
74 compatible = "arm,cortex-a53";
76 enable-method = "psci";
77 capacity-dmips-mhz = <485>;
79 #cooling-cells = <2>; /* min followed by max */
80 dynamic-power-coefficient = <100>;
81 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
86 compatible = "arm,cortex-a53";
88 enable-method = "psci";
89 capacity-dmips-mhz = <485>;
91 #cooling-cells = <2>; /* min followed by max */
92 dynamic-power-coefficient = <100>;
93 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
98 compatible = "arm,cortex-a53";
100 enable-method = "psci";
101 capacity-dmips-mhz = <485>;
103 #cooling-cells = <2>; /* min followed by max */
104 dynamic-power-coefficient = <100>;
105 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
110 compatible = "arm,cortex-a53";
112 enable-method = "psci";
113 capacity-dmips-mhz = <485>;
115 #cooling-cells = <2>; /* min followed by max */
116 dynamic-power-coefficient = <100>;
117 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
122 compatible = "arm,cortex-a72";
124 enable-method = "psci";
125 capacity-dmips-mhz = <1024>;
127 #cooling-cells = <2>; /* min followed by max */
128 dynamic-power-coefficient = <436>;
129 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
134 compatible = "arm,cortex-a72";
136 enable-method = "psci";
137 capacity-dmips-mhz = <1024>;
139 #cooling-cells = <2>; /* min followed by max */
140 dynamic-power-coefficient = <436>;
141 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
144 idle-states {
145 entry-method = "psci";
147 CPU_SLEEP: cpu-sleep {
148 compatible = "arm,idle-state";
149 local-timer-stop;
150 arm,psci-suspend-param = <0x0010000>;
151 entry-latency-us = <120>;
152 exit-latency-us = <250>;
153 min-residency-us = <900>;
156 CLUSTER_SLEEP: cluster-sleep {
157 compatible = "arm,idle-state";
158 local-timer-stop;
159 arm,psci-suspend-param = <0x1010000>;
160 entry-latency-us = <400>;
161 exit-latency-us = <500>;
162 min-residency-us = <2000>;
167 display-subsystem {
168 compatible = "rockchip,display-subsystem";
173 compatible = "arm,cortex-a53-pmu";
178 compatible = "arm,cortex-a72-pmu";
183 compatible = "arm,psci-1.0";
188 compatible = "arm,armv8-timer";
193 arm,no-tick-in-suspend;
197 compatible = "fixed-clock";
198 clock-frequency = <24000000>;
199 clock-output-names = "xin24m";
200 #clock-cells = <0>;
204 compatible = "simple-bus";
205 #address-cells = <2>;
206 #size-cells = <2>;
209 dmac_bus: dma-controller@ff6d0000 {
214 #dma-cells = <1>;
215 arm,pl330-periph-burst;
217 clock-names = "apb_pclk";
220 dmac_peri: dma-controller@ff6e0000 {
225 #dma-cells = <1>;
226 arm,pl330-periph-burst;
228 clock-names = "apb_pclk";
233 compatible = "rockchip,rk3399-pcie";
236 reg-names = "axi-base", "apb-base";
237 #address-cells = <3>;
238 #size-cells = <2>;
239 #interrupt-cells = <1>;
240 aspm-no-l0s;
241 bus-range = <0x0 0x1f>;
244 clock-names = "aclk", "aclk-perf",
249 interrupt-names = "sys", "legacy", "client";
250 interrupt-map-mask = <0 0 0 7>;
251 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
255 linux,pci-domain = <0>;
256 max-link-speed = <1>;
257 msi-map = <0x0 &its 0x0 0x1000>;
260 phy-names = "pcie-phy-0", "pcie-phy-1",
261 "pcie-phy-2", "pcie-phy-3";
268 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
272 pcie0_intc: interrupt-controller {
273 interrupt-controller;
274 #address-cells = <0>;
275 #interrupt-cells = <1>;
280 compatible = "rockchip,rk3399-gmac";
283 interrupt-names = "macirq";
288 clock-names = "stmmaceth", "mac_clk_rx",
292 power-domains = <&power RK3399_PD_GMAC>;
294 reset-names = "stmmaceth";
301 compatible = "rockchip,rk3399-dw-mshc",
302 "rockchip,rk3288-dw-mshc";
305 max-frequency = <150000000>;
308 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
309 fifo-depth = <0x100>;
310 power-domains = <&power RK3399_PD_SDIOAUDIO>;
312 reset-names = "reset";
317 compatible = "rockchip,rk3399-dw-mshc",
318 "rockchip,rk3288-dw-mshc";
321 max-frequency = <150000000>;
322 assigned-clocks = <&cru HCLK_SD>;
323 assigned-clock-rates = <200000000>;
326 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
327 fifo-depth = <0x100>;
328 power-domains = <&power RK3399_PD_SD>;
330 reset-names = "reset";
335 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
338 arasan,soc-ctl-syscon = <&grf>;
339 assigned-clocks = <&cru SCLK_EMMC>;
340 assigned-clock-rates = <200000000>;
342 clock-names = "clk_xin", "clk_ahb";
343 clock-output-names = "emmc_cardclock";
344 #clock-cells = <0>;
346 phy-names = "phy_arasan";
347 power-domains = <&power RK3399_PD_EMMC>;
348 disable-cqe-dcmd;
353 compatible = "generic-ehci";
359 phy-names = "usb";
364 compatible = "generic-ohci";
370 phy-names = "usb";
375 compatible = "generic-ehci";
381 phy-names = "usb";
386 compatible = "generic-ohci";
392 phy-names = "usb";
397 compatible = "rockchip,rk3399-dwc3";
398 #address-cells = <2>;
399 #size-cells = <2>;
404 clock-names = "ref_clk", "suspend_clk",
408 reset-names = "usb3-otg";
417 clock-names = "ref", "bus_early", "suspend";
420 phy-names = "usb2-phy", "usb3-phy";
423 snps,dis-u2-freeclk-exists-quirk;
425 snps,dis-del-phy-power-chg-quirk;
426 snps,dis-tx-ipgap-linecheck-quirk;
427 power-domains = <&power RK3399_PD_USB3>;
433 compatible = "rockchip,rk3399-dwc3";
434 #address-cells = <2>;
435 #size-cells = <2>;
440 clock-names = "ref_clk", "suspend_clk",
444 reset-names = "usb3-otg";
453 clock-names = "ref", "bus_early", "suspend";
456 phy-names = "usb2-phy", "usb3-phy";
459 snps,dis-u2-freeclk-exists-quirk;
461 snps,dis-del-phy-power-chg-quirk;
462 snps,dis-tx-ipgap-linecheck-quirk;
463 power-domains = <&power RK3399_PD_USB3>;
469 compatible = "rockchip,rk3399-cdn-dp";
472 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
473 assigned-clock-rates = <100000000>, <200000000>;
476 clock-names = "core-clk", "pclk", "spdif", "grf";
478 power-domains = <&power RK3399_PD_HDCP>;
481 reset-names = "spdif", "dptx", "apb", "core";
483 #sound-dai-cells = <1>;
488 #address-cells = <1>;
489 #size-cells = <0>;
493 remote-endpoint = <&vopb_out_dp>;
498 remote-endpoint = <&vopl_out_dp>;
504 gic: interrupt-controller@fee00000 {
505 compatible = "arm,gic-v3";
506 #interrupt-cells = <4>;
507 #address-cells = <2>;
508 #size-cells = <2>;
510 interrupt-controller;
518 its: interrupt-controller@fee20000 {
519 compatible = "arm,gic-v3-its";
520 msi-controller;
521 #msi-cells = <1>;
525 ppi-partitions {
526 ppi_cluster0: interrupt-partition-0 {
530 ppi_cluster1: interrupt-partition-1 {
537 compatible = "rockchip,rk3399-saradc";
540 #io-channel-cells = <1>;
542 clock-names = "saradc", "apb_pclk";
544 reset-names = "saradc-apb";
549 compatible = "rockchip,rk3399-i2c";
551 assigned-clocks = <&cru SCLK_I2C1>;
552 assigned-clock-rates = <200000000>;
554 clock-names = "i2c", "pclk";
556 pinctrl-names = "default";
557 pinctrl-0 = <&i2c1_xfer>;
558 #address-cells = <1>;
559 #size-cells = <0>;
564 compatible = "rockchip,rk3399-i2c";
566 assigned-clocks = <&cru SCLK_I2C2>;
567 assigned-clock-rates = <200000000>;
569 clock-names = "i2c", "pclk";
571 pinctrl-names = "default";
572 pinctrl-0 = <&i2c2_xfer>;
573 #address-cells = <1>;
574 #size-cells = <0>;
579 compatible = "rockchip,rk3399-i2c";
581 assigned-clocks = <&cru SCLK_I2C3>;
582 assigned-clock-rates = <200000000>;
584 clock-names = "i2c", "pclk";
586 pinctrl-names = "default";
587 pinctrl-0 = <&i2c3_xfer>;
588 #address-cells = <1>;
589 #size-cells = <0>;
594 compatible = "rockchip,rk3399-i2c";
596 assigned-clocks = <&cru SCLK_I2C5>;
597 assigned-clock-rates = <200000000>;
599 clock-names = "i2c", "pclk";
601 pinctrl-names = "default";
602 pinctrl-0 = <&i2c5_xfer>;
603 #address-cells = <1>;
604 #size-cells = <0>;
609 compatible = "rockchip,rk3399-i2c";
611 assigned-clocks = <&cru SCLK_I2C6>;
612 assigned-clock-rates = <200000000>;
614 clock-names = "i2c", "pclk";
616 pinctrl-names = "default";
617 pinctrl-0 = <&i2c6_xfer>;
618 #address-cells = <1>;
619 #size-cells = <0>;
624 compatible = "rockchip,rk3399-i2c";
626 assigned-clocks = <&cru SCLK_I2C7>;
627 assigned-clock-rates = <200000000>;
629 clock-names = "i2c", "pclk";
631 pinctrl-names = "default";
632 pinctrl-0 = <&i2c7_xfer>;
633 #address-cells = <1>;
634 #size-cells = <0>;
639 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
642 clock-names = "baudclk", "apb_pclk";
644 reg-shift = <2>;
645 reg-io-width = <4>;
646 pinctrl-names = "default";
647 pinctrl-0 = <&uart0_xfer>;
652 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
655 clock-names = "baudclk", "apb_pclk";
657 reg-shift = <2>;
658 reg-io-width = <4>;
659 pinctrl-names = "default";
660 pinctrl-0 = <&uart1_xfer>;
665 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
668 clock-names = "baudclk", "apb_pclk";
670 reg-shift = <2>;
671 reg-io-width = <4>;
672 pinctrl-names = "default";
673 pinctrl-0 = <&uart2c_xfer>;
678 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
681 clock-names = "baudclk", "apb_pclk";
683 reg-shift = <2>;
684 reg-io-width = <4>;
685 pinctrl-names = "default";
686 pinctrl-0 = <&uart3_xfer>;
691 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
694 clock-names = "spiclk", "apb_pclk";
697 dma-names = "tx", "rx";
698 pinctrl-names = "default";
699 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
700 #address-cells = <1>;
701 #size-cells = <0>;
706 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
709 clock-names = "spiclk", "apb_pclk";
712 dma-names = "tx", "rx";
713 pinctrl-names = "default";
714 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
715 #address-cells = <1>;
716 #size-cells = <0>;
721 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
724 clock-names = "spiclk", "apb_pclk";
727 dma-names = "tx", "rx";
728 pinctrl-names = "default";
729 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
730 #address-cells = <1>;
731 #size-cells = <0>;
736 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
739 clock-names = "spiclk", "apb_pclk";
742 dma-names = "tx", "rx";
743 pinctrl-names = "default";
744 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
745 #address-cells = <1>;
746 #size-cells = <0>;
751 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
754 clock-names = "spiclk", "apb_pclk";
757 dma-names = "tx", "rx";
758 pinctrl-names = "default";
759 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
760 power-domains = <&power RK3399_PD_SDIOAUDIO>;
761 #address-cells = <1>;
762 #size-cells = <0>;
766 thermal_zones: thermal-zones {
768 polling-delay-passive = <100>;
769 polling-delay = <1000>;
771 thermal-sensors = <&tsadc 0>;
791 cooling-maps {
794 cooling-device =
800 cooling-device =
812 polling-delay-passive = <100>;
813 polling-delay = <1000>;
815 thermal-sensors = <&tsadc 1>;
830 cooling-maps {
833 cooling-device =
841 compatible = "rockchip,rk3399-tsadc";
844 assigned-clocks = <&cru SCLK_TSADC>;
845 assigned-clock-rates = <750000>;
847 clock-names = "tsadc", "apb_pclk";
849 reset-names = "tsadc-apb";
851 rockchip,hw-tshut-temp = <95000>;
852 pinctrl-names = "init", "default", "sleep";
853 pinctrl-0 = <&otp_pin>;
854 pinctrl-1 = <&otp_out>;
855 pinctrl-2 = <&otp_pin>;
856 #thermal-sensor-cells = <1>;
985 pmu: power-management@ff310000 {
986 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
996 power: power-controller {
997 compatible = "rockchip,rk3399-power-controller";
998 #power-domain-cells = <1>;
999 #address-cells = <1>;
1000 #size-cells = <0>;
1082 #address-cells = <1>;
1083 #size-cells = <0>;
1108 #address-cells = <1>;
1109 #size-cells = <0>;
1130 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1133 pmu_io_domains: io-domains {
1134 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1140 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1143 clock-names = "spiclk", "apb_pclk";
1145 pinctrl-names = "default";
1146 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1147 #address-cells = <1>;
1148 #size-cells = <0>;
1153 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1156 clock-names = "baudclk", "apb_pclk";
1158 reg-shift = <2>;
1159 reg-io-width = <4>;
1160 pinctrl-names = "default";
1161 pinctrl-0 = <&uart4_xfer>;
1166 compatible = "rockchip,rk3399-i2c";
1168 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1169 assigned-clock-rates = <200000000>;
1171 clock-names = "i2c", "pclk";
1173 pinctrl-names = "default";
1174 pinctrl-0 = <&i2c0_xfer>;
1175 #address-cells = <1>;
1176 #size-cells = <0>;
1181 compatible = "rockchip,rk3399-i2c";
1183 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1184 assigned-clock-rates = <200000000>;
1186 clock-names = "i2c", "pclk";
1188 pinctrl-names = "default";
1189 pinctrl-0 = <&i2c4_xfer>;
1190 #address-cells = <1>;
1191 #size-cells = <0>;
1196 compatible = "rockchip,rk3399-i2c";
1198 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1199 assigned-clock-rates = <200000000>;
1201 clock-names = "i2c", "pclk";
1203 pinctrl-names = "default";
1204 pinctrl-0 = <&i2c8_xfer>;
1205 #address-cells = <1>;
1206 #size-cells = <0>;
1211 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1213 #pwm-cells = <3>;
1214 pinctrl-names = "default";
1215 pinctrl-0 = <&pwm0_pin>;
1217 clock-names = "pwm";
1222 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1224 #pwm-cells = <3>;
1225 pinctrl-names = "default";
1226 pinctrl-0 = <&pwm1_pin>;
1228 clock-names = "pwm";
1233 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1235 #pwm-cells = <3>;
1236 pinctrl-names = "default";
1237 pinctrl-0 = <&pwm2_pin>;
1239 clock-names = "pwm";
1244 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1246 #pwm-cells = <3>;
1247 pinctrl-names = "default";
1248 pinctrl-0 = <&pwm3a_pin>;
1250 clock-names = "pwm";
1254 vpu: video-codec@ff650000 {
1255 compatible = "rockchip,rk3399-vpu";
1259 interrupt-names = "vepu", "vdpu";
1261 clock-names = "aclk", "hclk";
1263 power-domains = <&power RK3399_PD_VCODEC>;
1270 interrupt-names = "vpu_mmu";
1272 clock-names = "aclk", "iface";
1273 #iommu-cells = <0>;
1274 power-domains = <&power RK3399_PD_VCODEC>;
1277 vdec: video-codec@ff660000 {
1278 compatible = "rockchip,rk3399-vdec";
1281 interrupt-names = "vdpu";
1284 clock-names = "axi", "ahb", "cabac", "core";
1286 power-domains = <&power RK3399_PD_VDU>;
1293 interrupt-names = "vdec_mmu";
1295 clock-names = "aclk", "iface";
1296 power-domains = <&power RK3399_PD_VDU>;
1297 #iommu-cells = <0>;
1304 interrupt-names = "iep_mmu";
1306 clock-names = "aclk", "iface";
1307 #iommu-cells = <0>;
1312 compatible = "rockchip,rk3399-rga";
1316 clock-names = "aclk", "hclk", "sclk";
1318 reset-names = "core", "axi", "ahb";
1319 power-domains = <&power RK3399_PD_RGA>;
1323 compatible = "rockchip,rk3399-efuse";
1325 #address-cells = <1>;
1326 #size-cells = <1>;
1328 clock-names = "pclk_efuse";
1331 cpu_id: cpu-id@7 {
1334 cpub_leakage: cpu-leakage@17 {
1337 gpu_leakage: gpu-leakage@18 {
1340 center_leakage: center-leakage@19 {
1343 cpul_leakage: cpu-leakage@1a {
1346 logic_leakage: logic-leakage@1b {
1349 wafer_info: wafer-info@1c {
1354 pmucru: pmu-clock-controller@ff750000 {
1355 compatible = "rockchip,rk3399-pmucru";
1358 #clock-cells = <1>;
1359 #reset-cells = <1>;
1360 assigned-clocks = <&pmucru PLL_PPLL>;
1361 assigned-clock-rates = <676000000>;
1364 cru: clock-controller@ff760000 {
1365 compatible = "rockchip,rk3399-cru";
1368 #clock-cells = <1>;
1369 #reset-cells = <1>;
1370 assigned-clocks =
1381 assigned-clock-rates =
1395 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1397 #address-cells = <1>;
1398 #size-cells = <1>;
1400 io_domains: io-domains {
1401 compatible = "rockchip,rk3399-io-voltage-domain";
1405 mipi_dphy_rx0: mipi-dphy-rx0 {
1406 compatible = "rockchip,rk3399-mipi-dphy-rx0";
1410 clock-names = "dphy-ref", "dphy-cfg", "grf";
1411 power-domains = <&power RK3399_PD_VIO>;
1412 #phy-cells = <0>;
1416 u2phy0: usb2-phy@e450 {
1417 compatible = "rockchip,rk3399-usb2phy";
1420 clock-names = "phyclk";
1421 #clock-cells = <0>;
1422 clock-output-names = "clk_usbphy0_480m";
1425 u2phy0_host: host-port {
1426 #phy-cells = <0>;
1428 interrupt-names = "linestate";
1432 u2phy0_otg: otg-port {
1433 #phy-cells = <0>;
1437 interrupt-names = "otg-bvalid", "otg-id",
1443 u2phy1: usb2-phy@e460 {
1444 compatible = "rockchip,rk3399-usb2phy";
1447 clock-names = "phyclk";
1448 #clock-cells = <0>;
1449 clock-output-names = "clk_usbphy1_480m";
1452 u2phy1_host: host-port {
1453 #phy-cells = <0>;
1455 interrupt-names = "linestate";
1459 u2phy1_otg: otg-port {
1460 #phy-cells = <0>;
1464 interrupt-names = "otg-bvalid", "otg-id",
1471 compatible = "rockchip,rk3399-emmc-phy";
1474 clock-names = "emmcclk";
1475 #phy-cells = <0>;
1479 pcie_phy: pcie-phy {
1480 compatible = "rockchip,rk3399-pcie-phy";
1482 clock-names = "refclk";
1483 #phy-cells = <1>;
1485 drive-impedance-ohm = <50>;
1486 reset-names = "phy";
1492 compatible = "rockchip,rk3399-typec-phy";
1496 clock-names = "tcpdcore", "tcpdphy-ref";
1497 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1498 assigned-clock-rates = <50000000>;
1499 power-domains = <&power RK3399_PD_TCPD0>;
1503 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1507 tcphy0_dp: dp-port {
1508 #phy-cells = <0>;
1511 tcphy0_usb3: usb3-port {
1512 #phy-cells = <0>;
1517 compatible = "rockchip,rk3399-typec-phy";
1521 clock-names = "tcpdcore", "tcpdphy-ref";
1522 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1523 assigned-clock-rates = <50000000>;
1524 power-domains = <&power RK3399_PD_TCPD1>;
1528 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1532 tcphy1_dp: dp-port {
1533 #phy-cells = <0>;
1536 tcphy1_usb3: usb3-port {
1537 #phy-cells = <0>;
1542 compatible = "snps,dw-wdt";
1549 compatible = "rockchip,rk3399-timer";
1553 clock-names = "pclk", "timer";
1557 compatible = "rockchip,rk3399-spdif";
1561 dma-names = "tx";
1562 clock-names = "mclk", "hclk";
1564 pinctrl-names = "default";
1565 pinctrl-0 = <&spdif_bus>;
1566 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1567 #sound-dai-cells = <0>;
1572 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1577 dma-names = "tx", "rx";
1578 clock-names = "i2s_clk", "i2s_hclk";
1580 pinctrl-names = "default";
1581 pinctrl-0 = <&i2s0_8ch_bus>;
1582 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1583 #sound-dai-cells = <0>;
1588 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1592 dma-names = "tx", "rx";
1593 clock-names = "i2s_clk", "i2s_hclk";
1595 pinctrl-names = "default";
1596 pinctrl-0 = <&i2s1_2ch_bus>;
1597 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1598 #sound-dai-cells = <0>;
1603 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1607 dma-names = "tx", "rx";
1608 clock-names = "i2s_clk", "i2s_hclk";
1610 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1611 #sound-dai-cells = <0>;
1616 compatible = "rockchip,rk3399-vop-lit";
1619 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1620 assigned-clock-rates = <400000000>, <100000000>;
1622 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1624 power-domains = <&power RK3399_PD_VOPL>;
1626 reset-names = "axi", "ahb", "dclk";
1630 #address-cells = <1>;
1631 #size-cells = <0>;
1635 remote-endpoint = <&mipi_in_vopl>;
1640 remote-endpoint = <&edp_in_vopl>;
1645 remote-endpoint = <&hdmi_in_vopl>;
1650 remote-endpoint = <&mipi1_in_vopl>;
1655 remote-endpoint = <&dp_in_vopl>;
1664 interrupt-names = "vopl_mmu";
1666 clock-names = "aclk", "iface";
1667 power-domains = <&power RK3399_PD_VOPL>;
1668 #iommu-cells = <0>;
1673 compatible = "rockchip,rk3399-vop-big";
1676 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1677 assigned-clock-rates = <400000000>, <100000000>;
1679 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1681 power-domains = <&power RK3399_PD_VOPB>;
1683 reset-names = "axi", "ahb", "dclk";
1687 #address-cells = <1>;
1688 #size-cells = <0>;
1692 remote-endpoint = <&edp_in_vopb>;
1697 remote-endpoint = <&mipi_in_vopb>;
1702 remote-endpoint = <&hdmi_in_vopb>;
1707 remote-endpoint = <&mipi1_in_vopb>;
1712 remote-endpoint = <&dp_in_vopb>;
1721 interrupt-names = "vopb_mmu";
1723 clock-names = "aclk", "iface";
1724 power-domains = <&power RK3399_PD_VOPB>;
1725 #iommu-cells = <0>;
1733 interrupt-names = "isp0_mmu";
1735 clock-names = "aclk", "iface";
1736 #iommu-cells = <0>;
1737 power-domains = <&power RK3399_PD_ISP0>;
1738 rockchip,disable-mmu-reset;
1745 interrupt-names = "isp1_mmu";
1747 clock-names = "aclk", "iface";
1748 #iommu-cells = <0>;
1749 power-domains = <&power RK3399_PD_ISP1>;
1750 rockchip,disable-mmu-reset;
1753 hdmi_sound: hdmi-sound {
1754 compatible = "simple-audio-card";
1755 simple-audio-card,format = "i2s";
1756 simple-audio-card,mclk-fs = <256>;
1757 simple-audio-card,name = "hdmi-sound";
1760 simple-audio-card,cpu {
1761 sound-dai = <&i2s2>;
1763 simple-audio-card,codec {
1764 sound-dai = <&hdmi>;
1769 compatible = "rockchip,rk3399-dw-hdmi";
1777 clock-names = "iahb", "isfr", "vpll", "grf", "cec";
1778 power-domains = <&power RK3399_PD_HDCP>;
1779 reg-io-width = <4>;
1781 #sound-dai-cells = <0>;
1786 #address-cells = <1>;
1787 #size-cells = <0>;
1791 remote-endpoint = <&vopb_out_hdmi>;
1795 remote-endpoint = <&vopl_out_hdmi>;
1802 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1807 clock-names = "ref", "pclk", "phy_cfg", "grf";
1808 power-domains = <&power RK3399_PD_VIO>;
1810 reset-names = "apb";
1812 #address-cells = <1>;
1813 #size-cells = <0>;
1817 #address-cells = <1>;
1818 #size-cells = <0>;
1822 #address-cells = <1>;
1823 #size-cells = <0>;
1827 remote-endpoint = <&vopb_out_mipi>;
1831 remote-endpoint = <&vopl_out_mipi>;
1838 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1843 clock-names = "ref", "pclk", "phy_cfg", "grf";
1844 power-domains = <&power RK3399_PD_VIO>;
1846 reset-names = "apb";
1848 #address-cells = <1>;
1849 #size-cells = <0>;
1853 #address-cells = <1>;
1854 #size-cells = <0>;
1858 #address-cells = <1>;
1859 #size-cells = <0>;
1863 remote-endpoint = <&vopb_out_mipi1>;
1868 remote-endpoint = <&vopl_out_mipi1>;
1875 compatible = "rockchip,rk3399-edp";
1879 clock-names = "dp", "pclk", "grf";
1880 pinctrl-names = "default";
1881 pinctrl-0 = <&edp_hpd>;
1882 power-domains = <&power RK3399_PD_EDP>;
1884 reset-names = "dp";
1889 #address-cells = <1>;
1890 #size-cells = <0>;
1893 #address-cells = <1>;
1894 #size-cells = <0>;
1898 remote-endpoint = <&vopb_out_edp>;
1903 remote-endpoint = <&vopl_out_edp>;
1910 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
1915 interrupt-names = "job", "mmu", "gpu";
1917 #cooling-cells = <2>;
1918 power-domains = <&power RK3399_PD_GPU>;
1923 compatible = "rockchip,rk3399-pinctrl";
1926 #address-cells = <2>;
1927 #size-cells = <2>;
1931 compatible = "rockchip,gpio-bank";
1936 gpio-controller;
1937 #gpio-cells = <0x2>;
1939 interrupt-controller;
1940 #interrupt-cells = <0x2>;
1944 compatible = "rockchip,gpio-bank";
1949 gpio-controller;
1950 #gpio-cells = <0x2>;
1952 interrupt-controller;
1953 #interrupt-cells = <0x2>;
1957 compatible = "rockchip,gpio-bank";
1962 gpio-controller;
1963 #gpio-cells = <0x2>;
1965 interrupt-controller;
1966 #interrupt-cells = <0x2>;
1970 compatible = "rockchip,gpio-bank";
1975 gpio-controller;
1976 #gpio-cells = <0x2>;
1978 interrupt-controller;
1979 #interrupt-cells = <0x2>;
1983 compatible = "rockchip,gpio-bank";
1988 gpio-controller;
1989 #gpio-cells = <0x2>;
1991 interrupt-controller;
1992 #interrupt-cells = <0x2>;
1995 pcfg_pull_up: pcfg-pull-up {
1996 bias-pull-up;
1999 pcfg_pull_down: pcfg-pull-down {
2000 bias-pull-down;
2003 pcfg_pull_none: pcfg-pull-none {
2004 bias-disable;
2007 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2008 bias-disable;
2009 drive-strength = <12>;
2012 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
2013 bias-disable;
2014 drive-strength = <13>;
2017 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
2018 bias-disable;
2019 drive-strength = <18>;
2022 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
2023 bias-disable;
2024 drive-strength = <20>;
2027 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2028 bias-pull-up;
2029 drive-strength = <2>;
2032 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2033 bias-pull-up;
2034 drive-strength = <8>;
2037 pcfg_pull_up_18ma: pcfg-pull-up-18ma {
2038 bias-pull-up;
2039 drive-strength = <18>;
2042 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2043 bias-pull-up;
2044 drive-strength = <20>;
2047 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2048 bias-pull-down;
2049 drive-strength = <4>;
2052 pcfg_pull_down_8ma: pcfg-pull-down-8ma {
2053 bias-pull-down;
2054 drive-strength = <8>;
2057 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2058 bias-pull-down;
2059 drive-strength = <12>;
2062 pcfg_pull_down_18ma: pcfg-pull-down-18ma {
2063 bias-pull-down;
2064 drive-strength = <18>;
2067 pcfg_pull_down_20ma: pcfg-pull-down-20ma {
2068 bias-pull-down;
2069 drive-strength = <20>;
2072 pcfg_output_high: pcfg-output-high {
2073 output-high;
2076 pcfg_output_low: pcfg-output-low {
2077 output-low;
2081 clk_32k: clk-32k {
2087 edp_hpd: edp-hpd {
2094 rgmii_pins: rgmii-pins {
2128 rmii_pins: rmii-pins {
2154 i2c0_xfer: i2c0-xfer {
2162 i2c1_xfer: i2c1-xfer {
2170 i2c2_xfer: i2c2-xfer {
2178 i2c3_xfer: i2c3-xfer {
2186 i2c4_xfer: i2c4-xfer {
2194 i2c5_xfer: i2c5-xfer {
2202 i2c6_xfer: i2c6-xfer {
2210 i2c7_xfer: i2c7-xfer {
2218 i2c8_xfer: i2c8-xfer {
2226 i2s0_2ch_bus: i2s0-2ch-bus {
2236 i2s0_8ch_bus: i2s0-8ch-bus {
2251 i2s1_2ch_bus: i2s1-2ch-bus {
2262 sdio0_bus1: sdio0-bus1 {
2267 sdio0_bus4: sdio0-bus4 {
2275 sdio0_cmd: sdio0-cmd {
2280 sdio0_clk: sdio0-clk {
2285 sdio0_cd: sdio0-cd {
2290 sdio0_pwr: sdio0-pwr {
2295 sdio0_bkpwr: sdio0-bkpwr {
2300 sdio0_wp: sdio0-wp {
2305 sdio0_int: sdio0-int {
2312 sdmmc_bus1: sdmmc-bus1 {
2317 sdmmc_bus4: sdmmc-bus4 {
2325 sdmmc_clk: sdmmc-clk {
2330 sdmmc_cmd: sdmmc-cmd {
2335 sdmmc_cd: sdmmc-cd {
2340 sdmmc_wp: sdmmc-wp {
2347 ap_pwroff: ap-pwroff {
2351 ddrio_pwroff: ddrio-pwroff {
2357 spdif_bus: spdif-bus {
2362 spdif_bus_1: spdif-bus-1 {
2369 spi0_clk: spi0-clk {
2373 spi0_cs0: spi0-cs0 {
2377 spi0_cs1: spi0-cs1 {
2381 spi0_tx: spi0-tx {
2385 spi0_rx: spi0-rx {
2392 spi1_clk: spi1-clk {
2396 spi1_cs0: spi1-cs0 {
2400 spi1_rx: spi1-rx {
2404 spi1_tx: spi1-tx {
2411 spi2_clk: spi2-clk {
2415 spi2_cs0: spi2-cs0 {
2419 spi2_rx: spi2-rx {
2423 spi2_tx: spi2-tx {
2430 spi3_clk: spi3-clk {
2434 spi3_cs0: spi3-cs0 {
2438 spi3_rx: spi3-rx {
2442 spi3_tx: spi3-tx {
2449 spi4_clk: spi4-clk {
2453 spi4_cs0: spi4-cs0 {
2457 spi4_rx: spi4-rx {
2461 spi4_tx: spi4-tx {
2468 spi5_clk: spi5-clk {
2472 spi5_cs0: spi5-cs0 {
2476 spi5_rx: spi5-rx {
2480 spi5_tx: spi5-tx {
2487 test_clkout0: test-clkout0 {
2492 test_clkout1: test-clkout1 {
2497 test_clkout2: test-clkout2 {
2504 otp_pin: otp-pin {
2508 otp_out: otp-out {
2514 uart0_xfer: uart0-xfer {
2520 uart0_cts: uart0-cts {
2525 uart0_rts: uart0-rts {
2532 uart1_xfer: uart1-xfer {
2540 uart2a_xfer: uart2a-xfer {
2548 uart2b_xfer: uart2b-xfer {
2556 uart2c_xfer: uart2c-xfer {
2564 uart3_xfer: uart3-xfer {
2570 uart3_cts: uart3-cts {
2575 uart3_rts: uart3-rts {
2582 uart4_xfer: uart4-xfer {
2590 uarthdcp_xfer: uarthdcp-xfer {
2598 pwm0_pin: pwm0-pin {
2603 pwm0_pin_pull_down: pwm0-pin-pull-down {
2608 vop0_pwm_pin: vop0-pwm-pin {
2613 vop1_pwm_pin: vop1-pwm-pin {
2620 pwm1_pin: pwm1-pin {
2625 pwm1_pin_pull_down: pwm1-pin-pull-down {
2632 pwm2_pin: pwm2-pin {
2637 pwm2_pin_pull_down: pwm2-pin-pull-down {
2644 pwm3a_pin: pwm3a-pin {
2651 pwm3b_pin: pwm3b-pin {
2658 hdmi_i2c_xfer: hdmi-i2c-xfer {
2664 hdmi_cec: hdmi-cec {
2671 pcie_clkreqn_cpm: pci-clkreqn-cpm {
2676 pcie_clkreqnb_cpm: pci-clkreqnb-cpm {