Lines Matching full:cru
6 #include <dt-bindings/clock/rk3399-cru.h>
78 clocks = <&cru ARMCLKL>;
90 clocks = <&cru ARMCLKL>;
102 clocks = <&cru ARMCLKL>;
114 clocks = <&cru ARMCLKL>;
126 clocks = <&cru ARMCLKB>;
138 clocks = <&cru ARMCLKB>;
216 clocks = <&cru ACLK_DMAC0_PERILP>;
227 clocks = <&cru ACLK_DMAC1_PERILP>;
242 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
243 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
264 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
265 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
266 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
267 <&cru SRST_A_PCIE>;
284 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
285 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
286 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
287 <&cru PCLK_GMAC>;
293 resets = <&cru SRST_A_GMAC>;
306 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
307 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
311 resets = <&cru SRST_SDIO0>;
322 assigned-clocks = <&cru HCLK_SD>;
324 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
325 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
329 resets = <&cru SRST_SDMMC>;
339 assigned-clocks = <&cru SCLK_EMMC>;
341 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
356 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
367 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
378 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
389 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
401 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
402 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
403 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
407 resets = <&cru SRST_A_USB3_OTG0>;
415 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
416 <&cru SCLK_USB3OTG0_SUSPEND>;
437 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
438 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
439 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
443 resets = <&cru SRST_A_USB3_OTG1>;
451 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>,
452 <&cru SCLK_USB3OTG1_SUSPEND>;
472 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
474 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
475 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
479 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
480 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
541 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
543 resets = <&cru SRST_P_SARADC>;
551 assigned-clocks = <&cru SCLK_I2C1>;
553 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
566 assigned-clocks = <&cru SCLK_I2C2>;
568 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
581 assigned-clocks = <&cru SCLK_I2C3>;
583 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
596 assigned-clocks = <&cru SCLK_I2C5>;
598 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
611 assigned-clocks = <&cru SCLK_I2C6>;
613 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
626 assigned-clocks = <&cru SCLK_I2C7>;
628 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
641 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
654 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
667 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
680 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
693 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
708 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
723 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
738 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
753 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
844 assigned-clocks = <&cru SCLK_TSADC>;
846 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
848 resets = <&cru SRST_TSADC>;
1005 clocks = <&cru ACLK_IEP>,
1006 <&cru HCLK_IEP>;
1011 clocks = <&cru ACLK_RGA>,
1012 <&cru HCLK_RGA>;
1018 clocks = <&cru ACLK_VCODEC>,
1019 <&cru HCLK_VCODEC>;
1024 clocks = <&cru ACLK_VDU>,
1025 <&cru HCLK_VDU>;
1033 clocks = <&cru ACLK_GPU>;
1040 clocks = <&cru PCLK_EDP_CTRL>;
1044 clocks = <&cru ACLK_EMMC>;
1049 clocks = <&cru ACLK_GMAC>,
1050 <&cru PCLK_GMAC>;
1055 clocks = <&cru HCLK_SDMMC>,
1056 <&cru SCLK_SDMMC>;
1061 clocks = <&cru HCLK_SDIO>;
1066 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1067 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1071 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1072 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1076 clocks = <&cru ACLK_USB3>;
1087 clocks = <&cru ACLK_HDCP>,
1088 <&cru HCLK_HDCP>,
1089 <&cru PCLK_HDCP>;
1094 clocks = <&cru ACLK_ISP0>,
1095 <&cru HCLK_ISP0>;
1101 clocks = <&cru ACLK_ISP1>,
1102 <&cru HCLK_ISP1>;
1113 clocks = <&cru ACLK_VOP0>,
1114 <&cru HCLK_VOP0>;
1120 clocks = <&cru ACLK_VOP1>,
1121 <&cru HCLK_VOP1>;
1260 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1271 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1282 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
1283 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
1294 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1305 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1315 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1317 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1327 clocks = <&cru PCLK_EFUSE1024NS>;
1364 cru: clock-controller@ff760000 { label
1365 compatible = "rockchip,rk3399-cru";
1371 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1372 <&cru PLL_NPLL>,
1373 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1374 <&cru PCLK_PERIHP>,
1375 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1376 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1377 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
1378 <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
1379 <&cru ACLK_GIC_PRE>,
1380 <&cru PCLK_DDR>;
1407 clocks = <&cru SCLK_MIPIDPHY_REF>,
1408 <&cru SCLK_DPHY_RX0_CFG>,
1409 <&cru PCLK_VIO_GRF>;
1419 clocks = <&cru SCLK_USB2PHY0_REF>;
1446 clocks = <&cru SCLK_USB2PHY1_REF>;
1481 clocks = <&cru SCLK_PCIEPHY_REF>;
1484 resets = <&cru SRST_PCIEPHY>;
1494 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1495 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1497 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1500 resets = <&cru SRST_UPHY0>,
1501 <&cru SRST_UPHY0_PIPE_L00>,
1502 <&cru SRST_P_UPHY0_TCPHY>;
1519 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1520 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1522 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1525 resets = <&cru SRST_UPHY1>,
1526 <&cru SRST_UPHY1_PIPE_L00>,
1527 <&cru SRST_P_UPHY1_TCPHY>;
1544 clocks = <&cru PCLK_WDT>;
1552 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1563 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1579 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1594 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1609 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1619 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1621 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1625 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1665 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1676 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1678 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1682 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1722 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1734 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
1746 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
1772 clocks = <&cru PCLK_HDMI_CTRL>,
1773 <&cru SCLK_HDMI_SFR>,
1774 <&cru PLL_VPLL>,
1775 <&cru PCLK_VIO_GRF>,
1776 <&cru SCLK_HDMI_CEC>;
1805 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
1806 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
1809 resets = <&cru SRST_P_MIPI_DSI0>;
1841 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
1842 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
1845 resets = <&cru SRST_P_MIPI_DSI1>;
1878 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
1883 resets = <&cru SRST_P_EDP_CTRL>;
1916 clocks = <&cru ACLK_GPU>;
1959 clocks = <&cru PCLK_GPIO2>;
1972 clocks = <&cru PCLK_GPIO3>;
1985 clocks = <&cru PCLK_GPIO4>;