Lines Matching +full:en +full:- +full:active +full:- +full:lanes

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3  * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
7 /dts-v1/;
8 #include "rk3399-roc-pc.dtsi"
11 	model = "Firefly ROC-RK3399-PC Mezzanine Board";
12 	compatible = "firefly,roc-rk3399-pc-mezzanine", "rockchip,rk3399";
15 	poe_12v: poe-12v {
16 		compatible = "regulator-fixed";
17 		regulator-name = "poe_12v";
18 		regulator-always-on;
19 		regulator-boot-on;
20 		regulator-min-microvolt = <12000000>;
21 		regulator-max-microvolt = <12000000>;
24 	vcc3v3_ngff: vcc3v3-ngff {
25 		compatible = "regulator-fixed";
26 		regulator-name = "vcc3v3_ngff";
27 		enable-active-high;
29 		pinctrl-names = "default";
30 		pinctrl-0 = <&vcc3v3_ngff_en>;
31 		regulator-always-on;
32 		regulator-boot-on;
33 		regulator-min-microvolt = <3300000>;
34 		regulator-max-microvolt = <3300000>;
35 		vin-supply = <&sys_12v>;
38 	vcc3v3_pcie: vcc3v3-pcie {
39 		compatible = "regulator-fixed";
40 		regulator-name = "vcc3v3_pcie";
41 		enable-active-high;
43 		pinctrl-names = "default";
44 		pinctrl-0 = <&vcc3v3_pcie_en>;
45 		regulator-min-microvolt = <3300000>;
46 		regulator-max-microvolt = <3300000>;
47 		vin-supply = <&sys_12v>;
52 	vin-supply = <&poe_12v>;
60 	ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
61 	num-lanes = <4>;
62 	pinctrl-names = "default";
63 	pinctrl-0 = <&pcie_perst>;
64 	vpcie3v3-supply = <&vcc3v3_pcie>;
65 	vpcie1v8-supply = <&vcc1v8_pmu>;
66 	vpcie0v9-supply = <&vcca_0v9>;
72 		vcc3v3_ngff_en: vcc3v3-ngff-en {
78 		vcc3v3_pcie_en: vcc3v3-pcie-en {
82 		pcie_perst: pcie-perst {
89 	bus-width = <4>;
90 	cap-sd-highspeed;
91 	cap-sdio-irq;
92 	keep-power-in-suspend;
93 	mmc-pwrseq = <&sdio_pwrseq>;
94 	non-removable;
95 	pinctrl-names = "default";
96 	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
97 	sd-uhs-sdr104;
98 	vmmc-supply = <&vcc3v3_ngff>;
99 	vqmmc-supply = <&vcc_1v8>;
104 	pinctrl-names = "default";
105 	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;