Lines Matching +full:0 +full:xff680000
39 #address-cells = <0x2>;
40 #size-cells = <0x0>;
74 cpu_l0: cpu@0 {
77 reg = <0x0 0x0>;
85 reg = <0x0 0x1>;
93 reg = <0x0 0x2>;
101 reg = <0x0 0x3>;
109 reg = <0x0 0x100>;
117 reg = <0x0 0x101>;
125 reg = <0x0 0x102>;
133 reg = <0x0 0x103>;
147 reg = <0x0 0xff250000 0x0 0x4000>;
159 reg = <0x0 0xff600000 0x0 0x4000>;
160 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
206 #clock-cells = <0>;
211 reg = <0x0 0xff0c0000 0x0 0x4000>;
216 fifo-depth = <0x100>;
225 reg = <0x0 0xff0d0000 0x0 0x4000>;
230 fifo-depth = <0x100>;
239 reg = <0x0 0xff0f0000 0x0 0x4000>;
244 fifo-depth = <0x100>;
253 reg = <0x0 0xff100000 0x0 0x100>;
265 reg = <0x0 0xff110000 0x0 0x1000>;
270 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
272 #size-cells = <0>;
278 reg = <0x0 0xff120000 0x0 0x1000>;
283 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
285 #size-cells = <0>;
291 reg = <0x0 0xff130000 0x0 0x1000>;
296 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
298 #size-cells = <0>;
304 reg = <0x0 0xff140000 0x0 0x1000>;
307 #size-cells = <0>;
311 pinctrl-0 = <&i2c2_xfer>;
317 reg = <0x0 0xff150000 0x0 0x1000>;
320 #size-cells = <0>;
324 pinctrl-0 = <&i2c3_xfer>;
330 reg = <0x0 0xff160000 0x0 0x1000>;
333 #size-cells = <0>;
337 pinctrl-0 = <&i2c4_xfer>;
343 reg = <0x0 0xff170000 0x0 0x1000>;
346 #size-cells = <0>;
350 pinctrl-0 = <&i2c5_xfer>;
356 reg = <0x0 0xff180000 0x0 0x100>;
368 reg = <0x0 0xff190000 0x0 0x100>;
380 reg = <0x0 0xff1b0000 0x0 0x100>;
392 reg = <0x0 0xff1c0000 0x0 0x100>;
407 thermal-sensors = <&tsadc 0>;
481 reg = <0x0 0xff280000 0x0 0x100>;
488 pinctrl-0 = <&otp_pin>;
498 reg = <0x0 0xff290000 0x0 0x10000>;
515 reg = <0x0 0xff500000 0x0 0x100>;
524 reg = <0x0 0xff580000 0x0 0x40000>;
537 reg = <0x0 0xff650000 0x0 0x1000>;
542 pinctrl-0 = <&i2c0_xfer>;
544 #size-cells = <0>;
550 reg = <0x0 0xff660000 0x0 0x1000>;
553 #size-cells = <0>;
557 pinctrl-0 = <&i2c1_xfer>;
563 reg = <0x0 0xff680000 0x0 0x10>;
566 pinctrl-0 = <&pwm0_pin>;
574 reg = <0x0 0xff680010 0x0 0x10>;
577 pinctrl-0 = <&pwm1_pin>;
585 reg = <0x0 0xff680020 0x0 0x10>;
594 reg = <0x0 0xff680030 0x0 0x10>;
597 pinctrl-0 = <&pwm3_pin>;
605 reg = <0x0 0xff690000 0x0 0x100>;
610 pinctrl-0 = <&uart2_xfer>;
618 reg = <0x0 0xff6b0000 0x0 0x1000>;
631 reg = <0x0 0xff738000 0x0 0x1000>;
640 offset = <0x200>;
650 reg = <0x0 0xff760000 0x0 0x1000>;
658 reg = <0x0 0xff770000 0x0 0x1000>;
668 reg = <0x0 0xff800000 0x0 0x100>;
676 reg = <0x0 0xff810000 0x0 0x20>;
682 reg = <0x0 0xff880000 0x0 0x1000>;
689 pinctrl-0 = <&spdif_tx>;
695 reg = <0x0 0xff890000 0x0 0x1000>;
706 reg = <0x0 0xff898000 0x0 0x1000>;
710 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
713 pinctrl-0 = <&i2s_8ch_bus>;
719 reg = <0x0 0xff900800 0x0 0x100>;
724 #iommu-cells = <0>;
730 reg = <0x0 0xff914000 0x0 0x100>,
731 <0x0 0xff915000 0x0 0x100>;
736 #iommu-cells = <0>;
743 reg = <0x0 0xff930300 0x0 0x100>;
748 #iommu-cells = <0>;
754 reg = <0x0 0xff9a0440 0x0 0x40>,
755 <0x0 0xff9a0480 0x0 0x40>;
760 #iommu-cells = <0>;
766 reg = <0x0 0xff9a0800 0x0 0x100>;
772 #iommu-cells = <0>;
778 reg = <0x0 0xffb00000 0x0 0x20>;
785 reg = <0x17 0x1>;
788 reg = <0x1f 0x1>;
796 #address-cells = <0>;
798 reg = <0x0 0xffb71000 0x0 0x1000>,
799 <0x0 0xffb72000 0x0 0x2000>,
800 <0x0 0xffb74000 0x0 0x2000>,
801 <0x0 0xffb76000 0x0 0x2000>;
810 #address-cells = <0x2>;
811 #size-cells = <0x2>;
816 reg = <0x0 0xff750000 0x0 0x100>;
818 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
821 #gpio-cells = <0x2>;
824 #interrupt-cells = <0x2>;
829 reg = <0x0 0xff780000 0x0 0x100>;
831 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
834 #gpio-cells = <0x2>;
837 #interrupt-cells = <0x2>;
842 reg = <0x0 0xff790000 0x0 0x100>;
844 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
847 #gpio-cells = <0x2>;
850 #interrupt-cells = <0x2>;
855 reg = <0x0 0xff7a0000 0x0 0x100>;
857 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
860 #gpio-cells = <0x2>;
863 #interrupt-cells = <0x2>;
954 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
955 <0 RK_PA7 1 &pcfg_pull_none>;
968 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_none>,
1016 rockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>;
1136 rockchip,pins = <0 RK_PB4 2 &pcfg_pull_up>;
1139 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
1142 rockchip,pins = <0 RK_PB2 2 &pcfg_pull_up>;
1145 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
1151 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
1155 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1176 rockchip,pins = <0 RK_PC4 3 &pcfg_pull_up>,
1177 <0 RK_PC5 3 &pcfg_pull_none>;
1181 rockchip,pins = <0 RK_PC6 3 &pcfg_pull_none>;
1185 rockchip,pins = <0 RK_PC7 3 &pcfg_pull_none>;
1214 rockchip,pins = <0 RK_PD3 3 &pcfg_pull_up>,
1215 <0 RK_PD2 3 &pcfg_pull_none>;
1219 rockchip,pins = <0 RK_PD0 3 &pcfg_pull_none>;
1223 rockchip,pins = <0 RK_PD1 3 &pcfg_pull_none>;