Lines Matching full:cru
6 #include <dt-bindings/clock/rk3328-cru.h>
42 clocks = <&cru ARMCLK>;
55 clocks = <&cru ARMCLK>;
68 clocks = <&cru ARMCLK>;
81 clocks = <&cru ARMCLK>;
157 clocks = <&cru ACLK_DMAC>;
233 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
245 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
257 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
269 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
282 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
329 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
347 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
362 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
377 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
394 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
407 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
420 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
433 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
446 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
459 clocks = <&cru PCLK_WDT>;
465 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
476 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
487 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
499 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
551 assigned-clocks = <&cru SCLK_TSADC>;
553 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
559 resets = <&cru SRST_TSADC>;
572 clocks = <&cru SCLK_EFUSE>;
597 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
599 resets = <&cru SRST_SARADC_P>;
621 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
623 resets = <&cru SRST_GPU_A>;
631 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
642 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
653 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
664 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
675 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
685 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
687 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
708 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
720 clocks = <&cru PCLK_HDMI>,
721 <&cru SCLK_HDMI_SFC>,
722 <&cru SCLK_RTC32K>;
746 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
757 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
767 cru: clock-controller@ff440000 { label
768 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
780 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
781 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
782 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
783 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
784 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
785 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
786 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
787 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
788 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
789 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
790 <&cru SCLK_WIFI>, <&cru ARMCLK>,
791 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
792 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
793 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
794 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
795 <&cru SCLK_RTC32K>;
797 <&cru HDMIPHY>, <&cru PLL_APLL>,
798 <&cru PLL_GPLL>, <&xin24m>,
833 assigned-clocks = <&cru USB480M>;
860 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
861 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
872 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
873 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
884 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
885 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
897 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
898 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
899 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
900 <&cru PCLK_MAC2IO>;
905 resets = <&cru SRST_GMAC2IO_A>;
918 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
919 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
920 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
921 <&cru SCLK_MAC2PHY_OUT>;
926 resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;
941 clocks = <&cru SCLK_MAC2PHY_OUT>;
942 resets = <&cru SRST_MACPHY>;
955 clocks = <&cru HCLK_OTG>;
970 clocks = <&cru HCLK_HOST0>, <&u2phy>;
980 clocks = <&cru HCLK_HOST0>, <&u2phy>;
1010 clocks = <&cru PCLK_GPIO0>;
1023 clocks = <&cru PCLK_GPIO1>;
1036 clocks = <&cru PCLK_GPIO2>;
1049 clocks = <&cru PCLK_GPIO3>;