Lines Matching +full:sclk +full:- +full:strength
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/clock/rk3308-cru.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
38 #address-cells = <2>;
39 #size-cells = <0>;
43 compatible = "arm,cortex-a35";
45 enable-method = "psci";
47 #cooling-cells = <2>;
48 dynamic-power-coefficient = <90>;
49 operating-points-v2 = <&cpu0_opp_table>;
50 cpu-idle-states = <&CPU_SLEEP>;
51 next-level-cache = <&l2>;
56 compatible = "arm,cortex-a35";
58 enable-method = "psci";
59 operating-points-v2 = <&cpu0_opp_table>;
60 cpu-idle-states = <&CPU_SLEEP>;
61 next-level-cache = <&l2>;
66 compatible = "arm,cortex-a35";
68 enable-method = "psci";
69 operating-points-v2 = <&cpu0_opp_table>;
70 cpu-idle-states = <&CPU_SLEEP>;
71 next-level-cache = <&l2>;
76 compatible = "arm,cortex-a35";
78 enable-method = "psci";
79 operating-points-v2 = <&cpu0_opp_table>;
80 cpu-idle-states = <&CPU_SLEEP>;
81 next-level-cache = <&l2>;
84 idle-states {
85 entry-method = "psci";
87 CPU_SLEEP: cpu-sleep {
88 compatible = "arm,idle-state";
89 local-timer-stop;
90 arm,psci-suspend-param = <0x0010000>;
91 entry-latency-us = <120>;
92 exit-latency-us = <250>;
93 min-residency-us = <900>;
97 l2: l2-cache {
102 cpu0_opp_table: cpu0-opp-table {
103 compatible = "operating-points-v2";
104 opp-shared;
106 opp-408000000 {
107 opp-hz = /bits/ 64 <408000000>;
108 opp-microvolt = <950000 950000 1340000>;
109 clock-latency-ns = <40000>;
110 opp-suspend;
112 opp-600000000 {
113 opp-hz = /bits/ 64 <600000000>;
114 opp-microvolt = <950000 950000 1340000>;
115 clock-latency-ns = <40000>;
117 opp-816000000 {
118 opp-hz = /bits/ 64 <816000000>;
119 opp-microvolt = <1025000 1025000 1340000>;
120 clock-latency-ns = <40000>;
122 opp-1008000000 {
123 opp-hz = /bits/ 64 <1008000000>;
124 opp-microvolt = <1125000 1125000 1340000>;
125 clock-latency-ns = <40000>;
129 arm-pmu {
130 compatible = "arm,cortex-a35-pmu";
135 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
138 mac_clkin: external-mac-clock {
139 compatible = "fixed-clock";
140 clock-frequency = <50000000>;
141 clock-output-names = "mac_clkin";
142 #clock-cells = <0>;
146 compatible = "arm,psci-1.0";
151 compatible = "arm,armv8-timer";
159 compatible = "fixed-clock";
160 #clock-cells = <0>;
161 clock-frequency = <24000000>;
162 clock-output-names = "xin24m";
166 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd";
169 reboot-mode {
170 compatible = "syscon-reboot-mode";
172 mode-bootloader = <BOOT_BL_DOWNLOAD>;
173 mode-loader = <BOOT_BL_DOWNLOAD>;
174 mode-normal = <BOOT_NORMAL>;
175 mode-recovery = <BOOT_RECOVERY>;
176 mode-fastboot = <BOOT_FASTBOOT>;
181 compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd";
183 #address-cells = <1>;
184 #size-cells = <1>;
188 compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd";
190 #address-cells = <1>;
191 #size-cells = <1>;
195 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
198 clock-names = "i2c", "pclk";
200 pinctrl-names = "default";
201 pinctrl-0 = <&i2c0_xfer>;
202 #address-cells = <1>;
203 #size-cells = <0>;
208 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
211 clock-names = "i2c", "pclk";
213 pinctrl-names = "default";
214 pinctrl-0 = <&i2c1_xfer>;
215 #address-cells = <1>;
216 #size-cells = <0>;
221 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
224 clock-names = "i2c", "pclk";
226 pinctrl-names = "default";
227 pinctrl-0 = <&i2c2_xfer>;
228 #address-cells = <1>;
229 #size-cells = <0>;
234 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
237 clock-names = "i2c", "pclk";
239 pinctrl-names = "default";
240 pinctrl-0 = <&i2c3m0_xfer>;
241 #address-cells = <1>;
242 #size-cells = <0>;
247 compatible = "snps,dw-wdt";
255 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
259 clock-names = "baudclk", "apb_pclk";
260 reg-shift = <2>;
261 reg-io-width = <4>;
262 pinctrl-names = "default";
263 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
268 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
272 clock-names = "baudclk", "apb_pclk";
273 reg-shift = <2>;
274 reg-io-width = <4>;
275 pinctrl-names = "default";
276 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
281 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
285 clock-names = "baudclk", "apb_pclk";
286 reg-shift = <2>;
287 reg-io-width = <4>;
288 pinctrl-names = "default";
289 pinctrl-0 = <&uart2m0_xfer>;
294 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
298 clock-names = "baudclk", "apb_pclk";
299 reg-shift = <2>;
300 reg-io-width = <4>;
301 pinctrl-names = "default";
302 pinctrl-0 = <&uart3_xfer>;
307 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
311 clock-names = "baudclk", "apb_pclk";
312 reg-shift = <2>;
313 reg-io-width = <4>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
320 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
323 #address-cells = <1>;
324 #size-cells = <0>;
326 clock-names = "spiclk", "apb_pclk";
328 dma-names = "tx", "rx";
329 pinctrl-names = "default";
330 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>;
335 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
338 #address-cells = <1>;
339 #size-cells = <0>;
341 clock-names = "spiclk", "apb_pclk";
343 dma-names = "tx", "rx";
344 pinctrl-names = "default";
345 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>;
350 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
353 #address-cells = <1>;
354 #size-cells = <0>;
356 clock-names = "spiclk", "apb_pclk";
358 dma-names = "tx", "rx";
359 pinctrl-names = "default";
360 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>;
365 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
368 clock-names = "pwm", "pclk";
369 pinctrl-names = "default";
370 pinctrl-0 = <&pwm8_pin>;
371 #pwm-cells = <3>;
376 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
379 clock-names = "pwm", "pclk";
380 pinctrl-names = "default";
381 pinctrl-0 = <&pwm9_pin>;
382 #pwm-cells = <3>;
387 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
390 clock-names = "pwm", "pclk";
391 pinctrl-names = "default";
392 pinctrl-0 = <&pwm10_pin>;
393 #pwm-cells = <3>;
398 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
401 clock-names = "pwm", "pclk";
402 pinctrl-names = "default";
403 pinctrl-0 = <&pwm11_pin>;
404 #pwm-cells = <3>;
409 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
412 clock-names = "pwm", "pclk";
413 pinctrl-names = "default";
414 pinctrl-0 = <&pwm4_pin>;
415 #pwm-cells = <3>;
420 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
423 clock-names = "pwm", "pclk";
424 pinctrl-names = "default";
425 pinctrl-0 = <&pwm5_pin>;
426 #pwm-cells = <3>;
431 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
434 clock-names = "pwm", "pclk";
435 pinctrl-names = "default";
436 pinctrl-0 = <&pwm6_pin>;
437 #pwm-cells = <3>;
442 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
445 clock-names = "pwm", "pclk";
446 pinctrl-names = "default";
447 pinctrl-0 = <&pwm7_pin>;
448 #pwm-cells = <3>;
453 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
456 clock-names = "pwm", "pclk";
457 pinctrl-names = "default";
458 pinctrl-0 = <&pwm0_pin>;
459 #pwm-cells = <3>;
464 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
467 clock-names = "pwm", "pclk";
468 pinctrl-names = "default";
469 pinctrl-0 = <&pwm1_pin>;
470 #pwm-cells = <3>;
475 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
478 clock-names = "pwm", "pclk";
479 pinctrl-names = "default";
480 pinctrl-0 = <&pwm2_pin>;
481 #pwm-cells = <3>;
486 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
489 clock-names = "pwm", "pclk";
490 pinctrl-names = "default";
491 pinctrl-0 = <&pwm3_pin>;
492 #pwm-cells = <3>;
497 compatible = "rockchip,rk3288-timer";
501 clock-names = "pclk", "timer";
505 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc";
509 clock-names = "saradc", "apb_pclk";
510 #io-channel-cells = <1>;
512 reset-names = "saradc-apb";
517 compatible = "simple-bus";
518 #address-cells = <2>;
519 #size-cells = <2>;
522 dmac0: dma-controller@ff2c0000 {
527 arm,pl330-periph-burst;
529 clock-names = "apb_pclk";
530 #dma-cells = <1>;
533 dmac1: dma-controller@ff2d0000 {
538 arm,pl330-periph-burst;
540 clock-names = "apb_pclk";
541 #dma-cells = <1>;
546 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
550 clock-names = "i2s_clk", "i2s_hclk";
552 dma-names = "tx", "rx";
554 reset-names = "reset-m", "reset-h";
555 pinctrl-names = "default";
556 pinctrl-0 = <&i2s_2ch_0_sclk
564 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
568 clock-names = "i2s_clk", "i2s_hclk";
570 dma-names = "rx";
572 reset-names = "reset-m", "reset-h";
576 spdif_tx: spdif-tx@ff3a0000 {
577 compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif";
581 clock-names = "mclk", "hclk";
583 dma-names = "tx";
584 pinctrl-names = "default";
585 pinctrl-0 = <&spdif_out>;
590 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
593 bus-width = <4>;
596 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
597 fifo-depth = <0x100>;
598 max-frequency = <150000000>;
599 pinctrl-names = "default";
600 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
605 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
608 bus-width = <8>;
611 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
612 fifo-depth = <0x100>;
613 max-frequency = <150000000>;
618 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
621 bus-width = <4>;
624 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
625 fifo-depth = <0x100>;
626 max-frequency = <150000000>;
627 pinctrl-names = "default";
628 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
632 cru: clock-controller@ff500000 {
633 compatible = "rockchip,rk3308-cru";
635 #clock-cells = <1>;
636 #reset-cells = <1>;
639 assigned-clocks = <&cru SCLK_RTC32K>;
640 assigned-clock-rates = <32768>;
643 gic: interrupt-controller@ff580000 {
644 compatible = "arm,gic-400";
650 #interrupt-cells = <3>;
651 interrupt-controller;
652 #address-cells = <0>;
656 compatible = "mmio-sram";
659 #address-cells = <1>;
660 #size-cells = <1>;
663 ddr-sram@0 {
668 vad_sram: vad-sram@8000 {
674 compatible = "rockchip,rk3308-pinctrl";
676 #address-cells = <2>;
677 #size-cells = <2>;
681 compatible = "rockchip,gpio-bank";
685 gpio-controller;
686 #gpio-cells = <2>;
687 interrupt-controller;
688 #interrupt-cells = <2>;
692 compatible = "rockchip,gpio-bank";
696 gpio-controller;
697 #gpio-cells = <2>;
698 interrupt-controller;
699 #interrupt-cells = <2>;
703 compatible = "rockchip,gpio-bank";
707 gpio-controller;
708 #gpio-cells = <2>;
709 interrupt-controller;
710 #interrupt-cells = <2>;
714 compatible = "rockchip,gpio-bank";
718 gpio-controller;
719 #gpio-cells = <2>;
720 interrupt-controller;
721 #interrupt-cells = <2>;
725 compatible = "rockchip,gpio-bank";
729 gpio-controller;
730 #gpio-cells = <2>;
731 interrupt-controller;
732 #interrupt-cells = <2>;
735 pcfg_pull_up: pcfg-pull-up {
736 bias-pull-up;
739 pcfg_pull_down: pcfg-pull-down {
740 bias-pull-down;
743 pcfg_pull_none: pcfg-pull-none {
744 bias-disable;
747 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
748 bias-disable;
749 drive-strength = <2>;
752 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
753 bias-pull-up;
754 drive-strength = <2>;
757 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
758 bias-pull-up;
759 drive-strength = <4>;
762 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
763 bias-disable;
764 drive-strength = <4>;
767 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
768 bias-pull-down;
769 drive-strength = <4>;
772 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
773 bias-disable;
774 drive-strength = <8>;
777 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
778 bias-pull-up;
779 drive-strength = <8>;
782 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
783 bias-disable;
784 drive-strength = <12>;
787 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
788 bias-pull-up;
789 drive-strength = <12>;
792 pcfg_pull_none_smt: pcfg-pull-none-smt {
793 bias-disable;
794 input-schmitt-enable;
797 pcfg_output_high: pcfg-output-high {
798 output-high;
801 pcfg_output_low: pcfg-output-low {
802 output-low;
805 pcfg_input_high: pcfg-input-high {
806 bias-pull-up;
807 input-enable;
810 pcfg_input: pcfg-input {
811 input-enable;
815 emmc_clk: emmc-clk {
820 emmc_cmd: emmc-cmd {
825 emmc_pwren: emmc-pwren {
830 emmc_rstn: emmc-rstn {
835 emmc_bus1: emmc-bus1 {
840 emmc_bus4: emmc-bus4 {
848 emmc_bus8: emmc-bus8 {
862 flash_csn0: flash-csn0 {
867 flash_rdy: flash-rdy {
872 flash_ale: flash-ale {
877 flash_cle: flash-cle {
882 flash_wrn: flash-wrn {
887 flash_rdn: flash-rdn {
892 flash_bus8: flash-bus8 {
906 rmii_pins: rmii-pins {
928 mac_refclk_12ma: mac-refclk-12ma {
933 mac_refclk: mac-refclk {
939 gmac-m1 {
940 rmiim1_pins: rmiim1-pins {
962 macm1_refclk_12ma: macm1-refclk-12ma {
967 macm1_refclk: macm1-refclk {
974 i2c0_xfer: i2c0-xfer {
982 i2c1_xfer: i2c1-xfer {
990 i2c2_xfer: i2c2-xfer {
997 i2c3-m0 {
998 i2c3m0_xfer: i2c3m0-xfer {
1005 i2c3-m1 {
1006 i2c3m1_xfer: i2c3m1-xfer {
1013 i2c3-m2 {
1014 i2c3m2_xfer: i2c3m2-xfer {
1022 i2s_2ch_0_mclk: i2s-2ch-0-mclk {
1027 i2s_2ch_0_sclk: i2s-2ch-0-sclk {
1032 i2s_2ch_0_lrck: i2s-2ch-0-lrck {
1037 i2s_2ch_0_sdo: i2s-2ch-0-sdo {
1042 i2s_2ch_0_sdi: i2s-2ch-0-sdi {
1049 i2s_8ch_0_mclk: i2s-8ch-0-mclk {
1054 i2s_8ch_0_sclktx: i2s-8ch-0-sclktx {
1059 i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx {
1064 i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx {
1069 i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx {
1074 i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 {
1079 i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 {
1084 i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 {
1089 i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 {
1094 i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 {
1099 i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 {
1104 i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 {
1109 i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 {
1116 i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk {
1121 i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx {
1126 i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx {
1131 i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx {
1136 i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx {
1141 i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 {
1146 i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 {
1151 i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 {
1156 i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 {
1161 i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 {
1168 i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk {
1173 i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx {
1178 i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx {
1183 i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx {
1188 i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx {
1193 i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 {
1198 i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 {
1203 i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 {
1208 i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 {
1213 i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 {
1220 pdm_m0_clk: pdm-m0-clk {
1225 pdm_m0_sdi0: pdm-m0-sdi0 {
1230 pdm_m0_sdi1: pdm-m0-sdi1 {
1235 pdm_m0_sdi2: pdm-m0-sdi2 {
1240 pdm_m0_sdi3: pdm-m0-sdi3 {
1247 pdm_m1_clk: pdm-m1-clk {
1252 pdm_m1_sdi0: pdm-m1-sdi0 {
1257 pdm_m1_sdi1: pdm-m1-sdi1 {
1262 pdm_m1_sdi2: pdm-m1-sdi2 {
1267 pdm_m1_sdi3: pdm-m1-sdi3 {
1274 pdm_m2_clkm: pdm-m2-clkm {
1279 pdm_m2_clk: pdm-m2-clk {
1284 pdm_m2_sdi0: pdm-m2-sdi0 {
1289 pdm_m2_sdi1: pdm-m2-sdi1 {
1294 pdm_m2_sdi2: pdm-m2-sdi2 {
1299 pdm_m2_sdi3: pdm-m2-sdi3 {
1306 pwm0_pin: pwm0-pin {
1311 pwm0_pin_pull_down: pwm0-pin-pull-down {
1318 pwm1_pin: pwm1-pin {
1323 pwm1_pin_pull_down: pwm1-pin-pull-down {
1330 pwm2_pin: pwm2-pin {
1335 pwm2_pin_pull_down: pwm2-pin-pull-down {
1342 pwm3_pin: pwm3-pin {
1347 pwm3_pin_pull_down: pwm3-pin-pull-down {
1354 pwm4_pin: pwm4-pin {
1359 pwm4_pin_pull_down: pwm4-pin-pull-down {
1366 pwm5_pin: pwm5-pin {
1371 pwm5_pin_pull_down: pwm5-pin-pull-down {
1378 pwm6_pin: pwm6-pin {
1383 pwm6_pin_pull_down: pwm6-pin-pull-down {
1390 pwm7_pin: pwm7-pin {
1395 pwm7_pin_pull_down: pwm7-pin-pull-down {
1402 pwm8_pin: pwm8-pin {
1407 pwm8_pin_pull_down: pwm8-pin-pull-down {
1414 pwm9_pin: pwm9-pin {
1419 pwm9_pin_pull_down: pwm9-pin-pull-down {
1426 pwm10_pin: pwm10-pin {
1431 pwm10_pin_pull_down: pwm10-pin-pull-down {
1438 pwm11_pin: pwm11-pin {
1443 pwm11_pin_pull_down: pwm11-pin-pull-down {
1450 rtc_32k: rtc-32k {
1457 sdmmc_clk: sdmmc-clk {
1462 sdmmc_cmd: sdmmc-cmd {
1467 sdmmc_det: sdmmc-det {
1472 sdmmc_pwren: sdmmc-pwren {
1477 sdmmc_bus1: sdmmc-bus1 {
1482 sdmmc_bus4: sdmmc-bus4 {
1492 sdio_clk: sdio-clk {
1497 sdio_cmd: sdio-cmd {
1502 sdio_pwren: sdio-pwren {
1507 sdio_wrpt: sdio-wrpt {
1512 sdio_intn: sdio-intn {
1517 sdio_bus1: sdio-bus1 {
1522 sdio_bus4: sdio-bus4 {
1532 spdif_in: spdif-in {
1539 spdif_out: spdif-out {
1546 spi0_clk: spi0-clk {
1551 spi0_csn0: spi0-csn0 {
1556 spi0_miso: spi0-miso {
1561 spi0_mosi: spi0-mosi {
1568 spi1_clk: spi1-clk {
1573 spi1_csn0: spi1-csn0 {
1578 spi1_miso: spi1-miso {
1583 spi1_mosi: spi1-mosi {
1589 spi1-m1 {
1590 spi1m1_miso: spi1m1-miso {
1595 spi1m1_mosi: spi1m1-mosi {
1600 spi1m1_clk: spi1m1-clk {
1605 spi1m1_csn0: spi1m1-csn0 {
1612 spi2_clk: spi2-clk {
1617 spi2_csn0: spi2-csn0 {
1622 spi2_miso: spi2-miso {
1627 spi2_mosi: spi2-mosi {
1634 tsadc_otp_pin: tsadc-otp-pin {
1639 tsadc_otp_out: tsadc-otp-out {
1646 uart0_xfer: uart0-xfer {
1652 uart0_cts: uart0-cts {
1657 uart0_rts: uart0-rts {
1662 uart0_rts_pin: uart0-rts-pin {
1669 uart1_xfer: uart1-xfer {
1675 uart1_cts: uart1-cts {
1680 uart1_rts: uart1-rts {
1686 uart2-m0 {
1687 uart2m0_xfer: uart2m0-xfer {
1694 uart2-m1 {
1695 uart2m1_xfer: uart2m1-xfer {
1703 uart3_xfer: uart3-xfer {
1710 uart3-m1 {
1711 uart3m1_xfer: uart3m1-xfer {
1719 uart4_xfer: uart4-xfer {
1725 uart4_cts: uart4-cts {
1730 uart4_rts: uart4-rts {
1735 uart4_rts_pin: uart4-rts-pin {