Lines Matching +full:0 +full:xff500000
39 #size-cells = <0>;
41 cpu0: cpu@0 {
44 reg = <0x0 0x0>;
57 reg = <0x0 0x1>;
67 reg = <0x0 0x2>;
77 reg = <0x0 0x3>;
90 arm,psci-suspend-param = <0x0010000>;
142 #clock-cells = <0>;
160 #clock-cells = <0>;
167 reg = <0x0 0xff000000 0x0 0x10000>;
171 offset = <0x500>;
182 reg = <0x0 0xff00b000 0x0 0x1000>;
189 reg = <0x0 0xff00c000 0x0 0x1000>;
196 reg = <0x0 0xff040000 0x0 0x1000>;
201 pinctrl-0 = <&i2c0_xfer>;
203 #size-cells = <0>;
209 reg = <0x0 0xff050000 0x0 0x1000>;
214 pinctrl-0 = <&i2c1_xfer>;
216 #size-cells = <0>;
222 reg = <0x0 0xff060000 0x0 0x1000>;
227 pinctrl-0 = <&i2c2_xfer>;
229 #size-cells = <0>;
235 reg = <0x0 0xff070000 0x0 0x1000>;
240 pinctrl-0 = <&i2c3m0_xfer>;
242 #size-cells = <0>;
248 reg = <0x0 0xff080000 0x0 0x100>;
256 reg = <0x0 0xff0a0000 0x0 0x100>;
263 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
269 reg = <0x0 0xff0b0000 0x0 0x100>;
276 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
282 reg = <0x0 0xff0c0000 0x0 0x100>;
289 pinctrl-0 = <&uart2m0_xfer>;
295 reg = <0x0 0xff0d0000 0x0 0x100>;
302 pinctrl-0 = <&uart3_xfer>;
308 reg = <0x0 0xff0e0000 0x0 0x100>;
315 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
321 reg = <0x0 0xff120000 0x0 0x1000>;
324 #size-cells = <0>;
327 dmas = <&dmac0 0>, <&dmac0 1>;
330 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>;
336 reg = <0x0 0xff130000 0x0 0x1000>;
339 #size-cells = <0>;
345 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>;
351 reg = <0x0 0xff140000 0x0 0x1000>;
354 #size-cells = <0>;
360 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>;
366 reg = <0x0 0xff160000 0x0 0x10>;
370 pinctrl-0 = <&pwm8_pin>;
377 reg = <0x0 0xff160010 0x0 0x10>;
381 pinctrl-0 = <&pwm9_pin>;
388 reg = <0x0 0xff160020 0x0 0x10>;
392 pinctrl-0 = <&pwm10_pin>;
399 reg = <0x0 0xff160030 0x0 0x10>;
403 pinctrl-0 = <&pwm11_pin>;
410 reg = <0x0 0xff170000 0x0 0x10>;
414 pinctrl-0 = <&pwm4_pin>;
421 reg = <0x0 0xff170010 0x0 0x10>;
425 pinctrl-0 = <&pwm5_pin>;
432 reg = <0x0 0xff170020 0x0 0x10>;
436 pinctrl-0 = <&pwm6_pin>;
443 reg = <0x0 0xff170030 0x0 0x10>;
447 pinctrl-0 = <&pwm7_pin>;
454 reg = <0x0 0xff180000 0x0 0x10>;
458 pinctrl-0 = <&pwm0_pin>;
465 reg = <0x0 0xff180010 0x0 0x10>;
469 pinctrl-0 = <&pwm1_pin>;
476 reg = <0x0 0xff180020 0x0 0x10>;
480 pinctrl-0 = <&pwm2_pin>;
487 reg = <0x0 0xff180030 0x0 0x10>;
491 pinctrl-0 = <&pwm3_pin>;
498 reg = <0x0 0xff1a0000 0x0 0x20>;
506 reg = <0x0 0xff1e0000 0x0 0x100>;
524 reg = <0x0 0xff2c0000 0x0 0x4000>;
525 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
535 reg = <0x0 0xff2d0000 0x0 0x4000>;
547 reg = <0x0 0xff350000 0x0 0x1000>;
556 pinctrl-0 = <&i2s_2ch_0_sclk
565 reg = <0x0 0xff360000 0x0 0x1000>;
578 reg = <0x0 0xff3a0000 0x0 0x1000>;
585 pinctrl-0 = <&spdif_out>;
591 reg = <0x0 0xff480000 0x0 0x4000>;
597 fifo-depth = <0x100>;
600 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
606 reg = <0x0 0xff490000 0x0 0x4000>;
612 fifo-depth = <0x100>;
619 reg = <0x0 0xff4a0000 0x0 0x4000>;
625 fifo-depth = <0x100>;
628 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
634 reg = <0x0 0xff500000 0x0 0x1000>;
645 reg = <0x0 0xff581000 0x0 0x1000>,
646 <0x0 0xff582000 0x0 0x2000>,
647 <0x0 0xff584000 0x0 0x2000>,
648 <0x0 0xff586000 0x0 0x2000>;
652 #address-cells = <0>;
657 reg = <0x0 0xfff80000 0x0 0x40000>;
658 ranges = <0 0x0 0xfff80000 0x40000>;
663 ddr-sram@0 {
664 reg = <0x0 0x8000>;
669 reg = <0x8000 0x38000>;
682 reg = <0x0 0xff220000 0x0 0x100>;
693 reg = <0x0 0xff230000 0x0 0x100>;
704 reg = <0x0 0xff240000 0x0 0x100>;
715 reg = <0x0 0xff250000 0x0 0x100>;
726 reg = <0x0 0xff260000 0x0 0x100>;
984 <0 RK_PB3 1 &pcfg_pull_none_smt>,
985 <0 RK_PB4 1 &pcfg_pull_none_smt>;
1000 <0 RK_PB7 2 &pcfg_pull_none_smt>,
1001 <0 RK_PC0 2 &pcfg_pull_none_smt>;
1022 i2s_2ch_0_mclk: i2s-2ch-0-mclk {
1027 i2s_2ch_0_sclk: i2s-2ch-0-sclk {
1032 i2s_2ch_0_lrck: i2s-2ch-0-lrck {
1037 i2s_2ch_0_sdo: i2s-2ch-0-sdo {
1042 i2s_2ch_0_sdi: i2s-2ch-0-sdi {
1049 i2s_8ch_0_mclk: i2s-8ch-0-mclk {
1054 i2s_8ch_0_sclktx: i2s-8ch-0-sclktx {
1059 i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx {
1064 i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx {
1069 i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx {
1074 i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 {
1079 i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 {
1084 i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 {
1089 i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 {
1094 i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 {
1099 i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 {
1104 i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 {
1109 i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 {
1308 <0 RK_PB5 1 &pcfg_pull_none>;
1313 <0 RK_PB5 1 &pcfg_pull_down>;
1320 <0 RK_PB6 1 &pcfg_pull_none>;
1325 <0 RK_PB6 1 &pcfg_pull_down>;
1332 <0 RK_PB7 1 &pcfg_pull_none>;
1337 <0 RK_PB7 1 &pcfg_pull_down>;
1344 <0 RK_PC0 1 &pcfg_pull_none>;
1349 <0 RK_PC0 1 &pcfg_pull_down>;
1356 <0 RK_PA1 2 &pcfg_pull_none>;
1361 <0 RK_PA1 2 &pcfg_pull_down>;
1368 <0 RK_PC1 2 &pcfg_pull_none>;
1373 <0 RK_PC1 2 &pcfg_pull_down>;
1380 <0 RK_PC2 2 &pcfg_pull_none>;
1385 <0 RK_PC2 2 &pcfg_pull_down>;
1452 <0 RK_PC3 1 &pcfg_pull_none>;
1469 <0 RK_PA3 1 &pcfg_pull_up_4ma>;
1504 <0 RK_PA2 1 &pcfg_pull_none_8ma>;
1509 <0 RK_PA1 1 &pcfg_pull_none_8ma>;
1514 <0 RK_PA0 1 &pcfg_pull_none_8ma>;
1534 <0 RK_PC2 1 &pcfg_pull_none>;
1541 <0 RK_PC1 1 &pcfg_pull_none>;
1636 <0 RK_PB2 0 &pcfg_pull_none>;
1641 <0 RK_PB2 1 &pcfg_pull_none>;
1664 <2 RK_PA3 0 &pcfg_pull_none>;
1713 <0 RK_PC2 3 &pcfg_pull_up>,
1714 <0 RK_PC1 3 &pcfg_pull_up>;
1737 <4 RK_PA7 0 &pcfg_pull_none>;