Lines Matching +full:mipi +full:- +full:bias
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/px30-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/px30-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
39 #address-cells = <2>;
40 #size-cells = <0>;
44 compatible = "arm,cortex-a35";
46 enable-method = "psci";
48 #cooling-cells = <2>;
49 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
50 dynamic-power-coefficient = <90>;
51 operating-points-v2 = <&cpu0_opp_table>;
56 compatible = "arm,cortex-a35";
58 enable-method = "psci";
60 #cooling-cells = <2>;
61 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
62 dynamic-power-coefficient = <90>;
63 operating-points-v2 = <&cpu0_opp_table>;
68 compatible = "arm,cortex-a35";
70 enable-method = "psci";
72 #cooling-cells = <2>;
73 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
74 dynamic-power-coefficient = <90>;
75 operating-points-v2 = <&cpu0_opp_table>;
80 compatible = "arm,cortex-a35";
82 enable-method = "psci";
84 #cooling-cells = <2>;
85 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
86 dynamic-power-coefficient = <90>;
87 operating-points-v2 = <&cpu0_opp_table>;
90 idle-states {
91 entry-method = "psci";
93 CPU_SLEEP: cpu-sleep {
94 compatible = "arm,idle-state";
95 local-timer-stop;
96 arm,psci-suspend-param = <0x0010000>;
97 entry-latency-us = <120>;
98 exit-latency-us = <250>;
99 min-residency-us = <900>;
102 CLUSTER_SLEEP: cluster-sleep {
103 compatible = "arm,idle-state";
104 local-timer-stop;
105 arm,psci-suspend-param = <0x1010000>;
106 entry-latency-us = <400>;
107 exit-latency-us = <500>;
108 min-residency-us = <2000>;
113 cpu0_opp_table: cpu0-opp-table {
114 compatible = "operating-points-v2";
115 opp-shared;
117 opp-600000000 {
118 opp-hz = /bits/ 64 <600000000>;
119 opp-microvolt = <950000 950000 1350000>;
120 clock-latency-ns = <40000>;
121 opp-suspend;
123 opp-816000000 {
124 opp-hz = /bits/ 64 <816000000>;
125 opp-microvolt = <1050000 1050000 1350000>;
126 clock-latency-ns = <40000>;
128 opp-1008000000 {
129 opp-hz = /bits/ 64 <1008000000>;
130 opp-microvolt = <1175000 1175000 1350000>;
131 clock-latency-ns = <40000>;
133 opp-1200000000 {
134 opp-hz = /bits/ 64 <1200000000>;
135 opp-microvolt = <1300000 1300000 1350000>;
136 clock-latency-ns = <40000>;
138 opp-1296000000 {
139 opp-hz = /bits/ 64 <1296000000>;
140 opp-microvolt = <1350000 1350000 1350000>;
141 clock-latency-ns = <40000>;
145 arm-pmu {
146 compatible = "arm,cortex-a35-pmu";
151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
154 display_subsystem: display-subsystem {
155 compatible = "rockchip,display-subsystem";
160 gmac_clkin: external-gmac-clock {
161 compatible = "fixed-clock";
162 clock-frequency = <50000000>;
163 clock-output-names = "gmac_clkin";
164 #clock-cells = <0>;
168 compatible = "arm,psci-1.0";
173 compatible = "arm,armv8-timer";
180 thermal_zones: thermal-zones {
181 soc_thermal: soc-thermal {
182 polling-delay-passive = <20>;
183 polling-delay = <1000>;
184 sustainable-power = <750>;
185 thermal-sensors = <&tsadc 0>;
188 threshold: trip-point-0 {
194 target: trip-point-1 {
200 soc_crit: soc-crit {
207 cooling-maps {
210 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
216 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
222 gpu_thermal: gpu-thermal {
223 polling-delay-passive = <100>; /* milliseconds */
224 polling-delay = <1000>; /* milliseconds */
225 thermal-sensors = <&tsadc 1>;
230 compatible = "fixed-clock";
231 #clock-cells = <0>;
232 clock-frequency = <24000000>;
233 clock-output-names = "xin24m";
236 pmu: power-management@ff000000 {
237 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
240 power: power-controller {
241 compatible = "rockchip,px30-power-controller";
242 #power-domain-cells = <1>;
243 #address-cells = <1>;
244 #size-cells = <0>;
324 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
326 #address-cells = <1>;
327 #size-cells = <1>;
329 pmu_io_domains: io-domains {
330 compatible = "rockchip,px30-pmu-io-voltage-domain";
334 reboot-mode {
335 compatible = "syscon-reboot-mode";
337 mode-bootloader = <BOOT_BL_DOWNLOAD>;
338 mode-fastboot = <BOOT_FASTBOOT>;
339 mode-loader = <BOOT_BL_DOWNLOAD>;
340 mode-normal = <BOOT_NORMAL>;
341 mode-recovery = <BOOT_RECOVERY>;
346 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
350 clock-names = "baudclk", "apb_pclk";
352 dma-names = "tx", "rx";
353 reg-shift = <2>;
354 reg-io-width = <4>;
355 pinctrl-names = "default";
356 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
361 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
365 clock-names = "i2s_clk", "i2s_hclk";
367 dma-names = "tx", "rx";
368 pinctrl-names = "default";
369 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
371 #sound-dai-cells = <0>;
376 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
380 clock-names = "i2s_clk", "i2s_hclk";
382 dma-names = "tx", "rx";
383 pinctrl-names = "default";
384 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
386 #sound-dai-cells = <0>;
390 gic: interrupt-controller@ff131000 {
391 compatible = "arm,gic-400";
392 #interrupt-cells = <3>;
393 #address-cells = <0>;
394 interrupt-controller;
404 compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
406 #address-cells = <1>;
407 #size-cells = <1>;
409 io_domains: io-domains {
410 compatible = "rockchip,px30-io-voltage-domain";
415 compatible = "rockchip,px30-lvds";
417 phy-names = "dphy";
423 #address-cells = <1>;
424 #size-cells = <0>;
428 #address-cells = <1>;
429 #size-cells = <0>;
433 remote-endpoint = <&vopb_out_lvds>;
438 remote-endpoint = <&vopl_out_lvds>;
446 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
450 clock-names = "baudclk", "apb_pclk";
452 dma-names = "tx", "rx";
453 reg-shift = <2>;
454 reg-io-width = <4>;
455 pinctrl-names = "default";
456 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
461 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
465 clock-names = "baudclk", "apb_pclk";
467 dma-names = "tx", "rx";
468 reg-shift = <2>;
469 reg-io-width = <4>;
470 pinctrl-names = "default";
471 pinctrl-0 = <&uart2m0_xfer>;
476 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
480 clock-names = "baudclk", "apb_pclk";
482 dma-names = "tx", "rx";
483 reg-shift = <2>;
484 reg-io-width = <4>;
485 pinctrl-names = "default";
486 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
491 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
495 clock-names = "baudclk", "apb_pclk";
497 dma-names = "tx", "rx";
498 reg-shift = <2>;
499 reg-io-width = <4>;
500 pinctrl-names = "default";
501 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
506 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
510 clock-names = "baudclk", "apb_pclk";
512 dma-names = "tx", "rx";
513 reg-shift = <2>;
514 reg-io-width = <4>;
515 pinctrl-names = "default";
516 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
521 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
524 clock-names = "i2c", "pclk";
526 pinctrl-names = "default";
527 pinctrl-0 = <&i2c0_xfer>;
528 #address-cells = <1>;
529 #size-cells = <0>;
534 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
537 clock-names = "i2c", "pclk";
539 pinctrl-names = "default";
540 pinctrl-0 = <&i2c1_xfer>;
541 #address-cells = <1>;
542 #size-cells = <0>;
547 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
550 clock-names = "i2c", "pclk";
552 pinctrl-names = "default";
553 pinctrl-0 = <&i2c2_xfer>;
554 #address-cells = <1>;
555 #size-cells = <0>;
560 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
563 clock-names = "i2c", "pclk";
565 pinctrl-names = "default";
566 pinctrl-0 = <&i2c3_xfer>;
567 #address-cells = <1>;
568 #size-cells = <0>;
573 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
577 clock-names = "spiclk", "apb_pclk";
579 dma-names = "tx", "rx";
580 pinctrl-names = "default";
581 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
582 #address-cells = <1>;
583 #size-cells = <0>;
588 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
592 clock-names = "spiclk", "apb_pclk";
594 dma-names = "tx", "rx";
595 pinctrl-names = "default";
596 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
597 #address-cells = <1>;
598 #size-cells = <0>;
603 compatible = "snps,dw-wdt";
611 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
614 clock-names = "pwm", "pclk";
615 pinctrl-names = "default";
616 pinctrl-0 = <&pwm0_pin>;
617 #pwm-cells = <3>;
622 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
625 clock-names = "pwm", "pclk";
626 pinctrl-names = "default";
627 pinctrl-0 = <&pwm1_pin>;
628 #pwm-cells = <3>;
633 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
636 clock-names = "pwm", "pclk";
637 pinctrl-names = "default";
638 pinctrl-0 = <&pwm2_pin>;
639 #pwm-cells = <3>;
644 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
647 clock-names = "pwm", "pclk";
648 pinctrl-names = "default";
649 pinctrl-0 = <&pwm3_pin>;
650 #pwm-cells = <3>;
655 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
658 clock-names = "pwm", "pclk";
659 pinctrl-names = "default";
660 pinctrl-0 = <&pwm4_pin>;
661 #pwm-cells = <3>;
666 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
669 clock-names = "pwm", "pclk";
670 pinctrl-names = "default";
671 pinctrl-0 = <&pwm5_pin>;
672 #pwm-cells = <3>;
677 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
680 clock-names = "pwm", "pclk";
681 pinctrl-names = "default";
682 pinctrl-0 = <&pwm6_pin>;
683 #pwm-cells = <3>;
688 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
691 clock-names = "pwm", "pclk";
692 pinctrl-names = "default";
693 pinctrl-0 = <&pwm7_pin>;
694 #pwm-cells = <3>;
699 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
703 clock-names = "pclk", "timer";
707 compatible = "simple-bus";
708 #address-cells = <2>;
709 #size-cells = <2>;
717 arm,pl330-periph-burst;
719 clock-names = "apb_pclk";
720 #dma-cells = <1>;
725 compatible = "rockchip,px30-tsadc";
728 assigned-clocks = <&cru SCLK_TSADC>;
729 assigned-clock-rates = <50000>;
731 clock-names = "tsadc", "apb_pclk";
733 reset-names = "tsadc-apb";
735 rockchip,hw-tshut-temp = <120000>;
736 pinctrl-names = "init", "default", "sleep";
737 pinctrl-0 = <&tsadc_otp_pin>;
738 pinctrl-1 = <&tsadc_otp_out>;
739 pinctrl-2 = <&tsadc_otp_pin>;
740 #thermal-sensor-cells = <1>;
745 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
748 #io-channel-cells = <1>;
750 clock-names = "saradc", "apb_pclk";
752 reset-names = "saradc-apb";
757 compatible = "rockchip,px30-otp";
761 clock-names = "otp", "apb_pclk", "phy";
763 reset-names = "phy";
764 #address-cells = <1>;
765 #size-cells = <1>;
771 cpu_leakage: cpu-leakage@17 {
780 cru: clock-controller@ff2b0000 {
781 compatible = "rockchip,px30-cru";
784 clock-names = "xin24m", "gpll";
786 #clock-cells = <1>;
787 #reset-cells = <1>;
789 assigned-clocks = <&cru PLL_NPLL>,
794 assigned-clock-rates = <1188000000>,
800 pmucru: clock-controller@ff2bc000 {
801 compatible = "rockchip,px30-pmucru";
804 clock-names = "xin24m";
806 #clock-cells = <1>;
807 #reset-cells = <1>;
809 assigned-clocks =
812 assigned-clock-rates =
818 compatible = "rockchip,px30-usb2phy-grf", "syscon",
819 "simple-mfd";
821 #address-cells = <1>;
822 #size-cells = <1>;
824 u2phy: usb2-phy@100 {
825 compatible = "rockchip,px30-usb2phy";
828 clock-names = "phyclk";
829 #clock-cells = <0>;
830 assigned-clocks = <&cru USB480M>;
831 assigned-clock-parents = <&u2phy>;
832 clock-output-names = "usb480m_phy";
835 u2phy_host: host-port {
836 #phy-cells = <0>;
838 interrupt-names = "linestate";
842 u2phy_otg: otg-port {
843 #phy-cells = <0>;
847 interrupt-names = "otg-bvalid", "otg-id",
855 compatible = "rockchip,px30-dsi-dphy";
858 clock-names = "ref", "pclk";
860 reset-names = "apb";
861 #phy-cells = <0>;
862 power-domains = <&power PX30_PD_VO>;
867 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
872 clock-names = "otg";
874 g-np-tx-fifo-size = <16>;
875 g-rx-fifo-size = <280>;
876 g-tx-fifo-size = <256 128 128 64 32 16>;
878 phy-names = "usb2-phy";
879 power-domains = <&power PX30_PD_USB>;
884 compatible = "generic-ehci";
889 phy-names = "usb";
890 power-domains = <&power PX30_PD_USB>;
895 compatible = "generic-ohci";
900 phy-names = "usb";
901 power-domains = <&power PX30_PD_USB>;
906 compatible = "rockchip,px30-gmac";
909 interrupt-names = "macirq";
914 clock-names = "stmmaceth", "mac_clk_rx",
919 phy-mode = "rmii";
920 pinctrl-names = "default";
921 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
922 power-domains = <&power PX30_PD_GMAC>;
924 reset-names = "stmmaceth";
929 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
934 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
935 bus-width = <4>;
936 fifo-depth = <0x100>;
937 max-frequency = <150000000>;
938 pinctrl-names = "default";
939 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
940 power-domains = <&power PX30_PD_SDCARD>;
945 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
950 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
951 bus-width = <4>;
952 fifo-depth = <0x100>;
953 max-frequency = <150000000>;
954 pinctrl-names = "default";
955 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
956 power-domains = <&power PX30_PD_MMC_NAND>;
961 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
966 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
967 bus-width = <8>;
968 fifo-depth = <0x100>;
969 max-frequency = <150000000>;
970 pinctrl-names = "default";
971 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
972 power-domains = <&power PX30_PD_MMC_NAND>;
977 compatible = "rockchip,px30-mali", "arm,mali-bifrost";
982 interrupt-names = "job", "mmu", "gpu";
984 #cooling-cells = <2>;
985 power-domains = <&power PX30_PD_GPU>;
990 compatible = "rockchip,px30-mipi-dsi";
994 clock-names = "pclk";
996 phy-names = "dphy";
997 power-domains = <&power PX30_PD_VO>;
999 reset-names = "apb";
1001 #address-cells = <1>;
1002 #size-cells = <0>;
1006 #address-cells = <1>;
1007 #size-cells = <0>;
1011 #address-cells = <1>;
1012 #size-cells = <0>;
1016 remote-endpoint = <&vopb_out_dsi>;
1021 remote-endpoint = <&vopl_out_dsi>;
1028 compatible = "rockchip,px30-vop-big";
1033 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1035 reset-names = "axi", "ahb", "dclk";
1037 power-domains = <&power PX30_PD_VO>;
1041 #address-cells = <1>;
1042 #size-cells = <0>;
1046 remote-endpoint = <&dsi_in_vopb>;
1051 remote-endpoint = <&lvds_vopb_in>;
1060 interrupt-names = "vopb_mmu";
1062 clock-names = "aclk", "iface";
1063 power-domains = <&power PX30_PD_VO>;
1064 #iommu-cells = <0>;
1069 compatible = "rockchip,px30-vop-lit";
1074 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1076 reset-names = "axi", "ahb", "dclk";
1078 power-domains = <&power PX30_PD_VO>;
1082 #address-cells = <1>;
1083 #size-cells = <0>;
1087 remote-endpoint = <&dsi_in_vopl>;
1092 remote-endpoint = <&lvds_vopl_in>;
1101 interrupt-names = "vopl_mmu";
1103 clock-names = "aclk", "iface";
1104 power-domains = <&power PX30_PD_VO>;
1105 #iommu-cells = <0>;
1210 compatible = "rockchip,px30-pinctrl";
1213 #address-cells = <2>;
1214 #size-cells = <2>;
1218 compatible = "rockchip,gpio-bank";
1222 gpio-controller;
1223 #gpio-cells = <2>;
1225 interrupt-controller;
1226 #interrupt-cells = <2>;
1230 compatible = "rockchip,gpio-bank";
1234 gpio-controller;
1235 #gpio-cells = <2>;
1237 interrupt-controller;
1238 #interrupt-cells = <2>;
1242 compatible = "rockchip,gpio-bank";
1246 gpio-controller;
1247 #gpio-cells = <2>;
1249 interrupt-controller;
1250 #interrupt-cells = <2>;
1254 compatible = "rockchip,gpio-bank";
1258 gpio-controller;
1259 #gpio-cells = <2>;
1261 interrupt-controller;
1262 #interrupt-cells = <2>;
1265 pcfg_pull_up: pcfg-pull-up {
1266 bias-pull-up;
1269 pcfg_pull_down: pcfg-pull-down {
1270 bias-pull-down;
1273 pcfg_pull_none: pcfg-pull-none {
1274 bias-disable;
1277 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1278 bias-disable;
1279 drive-strength = <2>;
1282 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1283 bias-pull-up;
1284 drive-strength = <2>;
1287 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1288 bias-pull-up;
1289 drive-strength = <4>;
1292 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1293 bias-disable;
1294 drive-strength = <4>;
1297 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1298 bias-pull-down;
1299 drive-strength = <4>;
1302 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1303 bias-disable;
1304 drive-strength = <8>;
1307 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1308 bias-pull-up;
1309 drive-strength = <8>;
1312 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1313 bias-disable;
1314 drive-strength = <12>;
1317 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1318 bias-pull-up;
1319 drive-strength = <12>;
1322 pcfg_pull_none_smt: pcfg-pull-none-smt {
1323 bias-disable;
1324 input-schmitt-enable;
1327 pcfg_output_high: pcfg-output-high {
1328 output-high;
1331 pcfg_output_low: pcfg-output-low {
1332 output-low;
1335 pcfg_input_high: pcfg-input-high {
1336 bias-pull-up;
1337 input-enable;
1340 pcfg_input: pcfg-input {
1341 input-enable;
1345 i2c0_xfer: i2c0-xfer {
1353 i2c1_xfer: i2c1-xfer {
1361 i2c2_xfer: i2c2-xfer {
1369 i2c3_xfer: i2c3-xfer {
1377 tsadc_otp_pin: tsadc-otp-pin {
1382 tsadc_otp_out: tsadc-otp-out {
1389 uart0_xfer: uart0-xfer {
1395 uart0_cts: uart0-cts {
1400 uart0_rts: uart0-rts {
1407 uart1_xfer: uart1-xfer {
1413 uart1_cts: uart1-cts {
1418 uart1_rts: uart1-rts {
1424 uart2-m0 {
1425 uart2m0_xfer: uart2m0-xfer {
1432 uart2-m1 {
1433 uart2m1_xfer: uart2m1-xfer {
1440 uart3-m0 {
1441 uart3m0_xfer: uart3m0-xfer {
1447 uart3m0_cts: uart3m0-cts {
1452 uart3m0_rts: uart3m0-rts {
1458 uart3-m1 {
1459 uart3m1_xfer: uart3m1-xfer {
1465 uart3m1_cts: uart3m1-cts {
1470 uart3m1_rts: uart3m1-rts {
1477 uart4_xfer: uart4-xfer {
1483 uart4_cts: uart4-cts {
1488 uart4_rts: uart4-rts {
1495 uart5_xfer: uart5-xfer {
1501 uart5_cts: uart5-cts {
1506 uart5_rts: uart5-rts {
1513 spi0_clk: spi0-clk {
1518 spi0_csn: spi0-csn {
1523 spi0_miso: spi0-miso {
1528 spi0_mosi: spi0-mosi {
1533 spi0_clk_hs: spi0-clk-hs {
1538 spi0_miso_hs: spi0-miso-hs {
1543 spi0_mosi_hs: spi0-mosi-hs {
1550 spi1_clk: spi1-clk {
1555 spi1_csn0: spi1-csn0 {
1560 spi1_csn1: spi1-csn1 {
1565 spi1_miso: spi1-miso {
1570 spi1_mosi: spi1-mosi {
1575 spi1_clk_hs: spi1-clk-hs {
1580 spi1_miso_hs: spi1-miso-hs {
1585 spi1_mosi_hs: spi1-mosi-hs {
1592 pdm_clk0m0: pdm-clk0m0 {
1597 pdm_clk0m1: pdm-clk0m1 {
1602 pdm_clk1: pdm-clk1 {
1607 pdm_sdi0m0: pdm-sdi0m0 {
1612 pdm_sdi0m1: pdm-sdi0m1 {
1617 pdm_sdi1: pdm-sdi1 {
1622 pdm_sdi2: pdm-sdi2 {
1627 pdm_sdi3: pdm-sdi3 {
1632 pdm_clk0m0_sleep: pdm-clk0m0-sleep {
1637 pdm_clk0m_sleep1: pdm-clk0m1-sleep {
1642 pdm_clk1_sleep: pdm-clk1-sleep {
1647 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
1652 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
1657 pdm_sdi1_sleep: pdm-sdi1-sleep {
1662 pdm_sdi2_sleep: pdm-sdi2-sleep {
1667 pdm_sdi3_sleep: pdm-sdi3-sleep {
1674 i2s0_8ch_mclk: i2s0-8ch-mclk {
1679 i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1684 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1689 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1694 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1699 i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1704 i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1709 i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1714 i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1719 i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1724 i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1729 i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1734 i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1741 i2s1_2ch_mclk: i2s1-2ch-mclk {
1746 i2s1_2ch_sclk: i2s1-2ch-sclk {
1751 i2s1_2ch_lrck: i2s1-2ch-lrck {
1756 i2s1_2ch_sdi: i2s1-2ch-sdi {
1761 i2s1_2ch_sdo: i2s1-2ch-sdo {
1768 i2s2_2ch_mclk: i2s2-2ch-mclk {
1773 i2s2_2ch_sclk: i2s2-2ch-sclk {
1778 i2s2_2ch_lrck: i2s2-2ch-lrck {
1783 i2s2_2ch_sdi: i2s2-2ch-sdi {
1788 i2s2_2ch_sdo: i2s2-2ch-sdo {
1795 sdmmc_clk: sdmmc-clk {
1800 sdmmc_cmd: sdmmc-cmd {
1805 sdmmc_det: sdmmc-det {
1810 sdmmc_bus1: sdmmc-bus1 {
1815 sdmmc_bus4: sdmmc-bus4 {
1825 sdio_clk: sdio-clk {
1830 sdio_cmd: sdio-cmd {
1835 sdio_bus4: sdio-bus4 {
1845 emmc_clk: emmc-clk {
1850 emmc_cmd: emmc-cmd {
1855 emmc_rstnout: emmc-rstnout {
1860 emmc_bus1: emmc-bus1 {
1865 emmc_bus4: emmc-bus4 {
1873 emmc_bus8: emmc-bus8 {
1887 flash_cs0: flash-cs0 {
1892 flash_rdy: flash-rdy {
1897 flash_dqs: flash-dqs {
1902 flash_ale: flash-ale {
1907 flash_cle: flash-cle {
1912 flash_wrn: flash-wrn {
1917 flash_csl: flash-csl {
1922 flash_rdn: flash-rdn {
1927 flash_bus8: flash-bus8 {
1941 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
1946 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
1951 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
1956 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
1961 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
1989 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
2011 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
2031 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
2052 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
2067 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
2082 pwm0_pin: pwm0-pin {
2089 pwm1_pin: pwm1-pin {
2096 pwm2_pin: pwm2-pin {
2103 pwm3_pin: pwm3-pin {
2110 pwm4_pin: pwm4-pin {
2117 pwm5_pin: pwm5-pin {
2124 pwm6_pin: pwm6-pin {
2131 pwm7_pin: pwm7-pin {
2138 rmii_pins: rmii-pins {
2151 mac_refclk_12ma: mac-refclk-12ma {
2156 mac_refclk: mac-refclk {
2162 cif-m0 {
2163 cif_clkout_m0: cif-clkout-m0 {
2168 dvp_d2d9_m0: dvp-d2d9-m0 {
2184 dvp_d0d1_m0: dvp-d0d1-m0 {
2190 dvp_d10d11_m0:d10-d11-m0 {
2197 cif-m1 {
2198 cif_clkout_m1: cif-clkout-m1 {
2203 dvp_d2d9_m1: dvp-d2d9-m1 {
2219 dvp_d0d1_m1: dvp-d0d1-m1 {
2225 dvp_d10d11_m1:d10-d11-m1 {
2233 isp_prelight: isp-prelight {