Lines Matching +full:0 +full:xff400000
40 #size-cells = <0>;
42 cpu0: cpu@0 {
45 reg = <0x0 0x0>;
57 reg = <0x0 0x1>;
69 reg = <0x0 0x2>;
81 reg = <0x0 0x3>;
96 arm,psci-suspend-param = <0x0010000>;
105 arm,psci-suspend-param = <0x1010000>;
164 #clock-cells = <0>;
185 thermal-sensors = <&tsadc 0>;
188 threshold: trip-point-0 {
231 #clock-cells = <0>;
238 reg = <0x0 0xff000000 0x0 0x1000>;
244 #size-cells = <0>;
325 reg = <0x0 0xff010000 0x0 0x1000>;
336 offset = <0x200>;
347 reg = <0x0 0xff030000 0x0 0x100>;
351 dmas = <&dmac 0>, <&dmac 1>;
356 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
362 reg = <0x0 0xff070000 0x0 0x1000>;
369 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
371 #sound-dai-cells = <0>;
377 reg = <0x0 0xff080000 0x0 0x1000>;
384 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
386 #sound-dai-cells = <0>;
393 #address-cells = <0>;
395 reg = <0x0 0xff131000 0 0x1000>,
396 <0x0 0xff132000 0 0x2000>,
397 <0x0 0xff134000 0 0x2000>,
398 <0x0 0xff136000 0 0x2000>;
405 reg = <0x0 0xff140000 0x0 0x1000>;
424 #size-cells = <0>;
426 port@0 {
427 reg = <0>;
429 #size-cells = <0>;
431 lvds_vopb_in: endpoint@0 {
432 reg = <0>;
447 reg = <0x0 0xff158000 0x0 0x100>;
456 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
462 reg = <0x0 0xff160000 0x0 0x100>;
471 pinctrl-0 = <&uart2m0_xfer>;
477 reg = <0x0 0xff168000 0x0 0x100>;
486 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
492 reg = <0x0 0xff170000 0x0 0x100>;
501 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
507 reg = <0x0 0xff178000 0x0 0x100>;
516 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
522 reg = <0x0 0xff180000 0x0 0x1000>;
527 pinctrl-0 = <&i2c0_xfer>;
529 #size-cells = <0>;
535 reg = <0x0 0xff190000 0x0 0x1000>;
540 pinctrl-0 = <&i2c1_xfer>;
542 #size-cells = <0>;
548 reg = <0x0 0xff1a0000 0x0 0x1000>;
553 pinctrl-0 = <&i2c2_xfer>;
555 #size-cells = <0>;
561 reg = <0x0 0xff1b0000 0x0 0x1000>;
566 pinctrl-0 = <&i2c3_xfer>;
568 #size-cells = <0>;
574 reg = <0x0 0xff1d0000 0x0 0x1000>;
581 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
583 #size-cells = <0>;
589 reg = <0x0 0xff1d8000 0x0 0x1000>;
596 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
598 #size-cells = <0>;
604 reg = <0x0 0xff1e0000 0x0 0x100>;
612 reg = <0x0 0xff200000 0x0 0x10>;
616 pinctrl-0 = <&pwm0_pin>;
623 reg = <0x0 0xff200010 0x0 0x10>;
627 pinctrl-0 = <&pwm1_pin>;
634 reg = <0x0 0xff200020 0x0 0x10>;
638 pinctrl-0 = <&pwm2_pin>;
645 reg = <0x0 0xff200030 0x0 0x10>;
649 pinctrl-0 = <&pwm3_pin>;
656 reg = <0x0 0xff208000 0x0 0x10>;
660 pinctrl-0 = <&pwm4_pin>;
667 reg = <0x0 0xff208010 0x0 0x10>;
671 pinctrl-0 = <&pwm5_pin>;
678 reg = <0x0 0xff208020 0x0 0x10>;
682 pinctrl-0 = <&pwm6_pin>;
689 reg = <0x0 0xff208030 0x0 0x10>;
693 pinctrl-0 = <&pwm7_pin>;
700 reg = <0x0 0xff210000 0x0 0x1000>;
714 reg = <0x0 0xff240000 0x0 0x4000>;
726 reg = <0x0 0xff280000 0x0 0x100>;
737 pinctrl-0 = <&tsadc_otp_pin>;
746 reg = <0x0 0xff288000 0x0 0x100>;
758 reg = <0x0 0xff290000 0x0 0x4000>;
769 reg = <0x07 0x10>;
772 reg = <0x17 0x1>;
775 reg = <0x1e 0x1>;
782 reg = <0x0 0xff2b0000 0x0 0x1000>;
802 reg = <0x0 0xff2bc000 0x0 0x1000>;
820 reg = <0x0 0xff2c0000 0x0 0x10000>;
826 reg = <0x100 0x20>;
829 #clock-cells = <0>;
836 #phy-cells = <0>;
843 #phy-cells = <0>;
856 reg = <0x0 0xff2e0000 0x0 0x10000>;
861 #phy-cells = <0>;
869 reg = <0x0 0xff300000 0x0 0x40000>;
885 reg = <0x0 0xff340000 0x0 0x10000>;
896 reg = <0x0 0xff350000 0x0 0x10000>;
907 reg = <0x0 0xff360000 0x0 0x10000>;
921 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
930 reg = <0x0 0xff370000 0x0 0x4000>;
936 fifo-depth = <0x100>;
939 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
946 reg = <0x0 0xff380000 0x0 0x4000>;
952 fifo-depth = <0x100>;
955 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
962 reg = <0x0 0xff390000 0x0 0x4000>;
968 fifo-depth = <0x100>;
971 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
978 reg = <0x0 0xff400000 0x0 0x4000>;
991 reg = <0x0 0xff450000 0x0 0x10000>;
1002 #size-cells = <0>;
1007 #size-cells = <0>;
1009 port@0 {
1010 reg = <0>;
1012 #size-cells = <0>;
1014 dsi_in_vopb: endpoint@0 {
1015 reg = <0>;
1029 reg = <0x0 0xff460000 0x0 0xefc>;
1042 #size-cells = <0>;
1044 vopb_out_dsi: endpoint@0 {
1045 reg = <0>;
1058 reg = <0x0 0xff460f00 0x0 0x100>;
1064 #iommu-cells = <0>;
1070 reg = <0x0 0xff470000 0x0 0xefc>;
1083 #size-cells = <0>;
1085 vopl_out_dsi: endpoint@0 {
1086 reg = <0>;
1099 reg = <0x0 0xff470f00 0x0 0x100>;
1105 #iommu-cells = <0>;
1111 reg = <0x0 0xff518000 0x0 0x20>;
1116 reg = <0x0 0xff520000 0x0 0x20>;
1121 reg = <0x0 0xff52c000 0x0 0x20>;
1126 reg = <0x0 0xff538000 0x0 0x20>;
1131 reg = <0x0 0xff538080 0x0 0x20>;
1136 reg = <0x0 0xff538100 0x0 0x20>;
1141 reg = <0x0 0xff538180 0x0 0x20>;
1146 reg = <0x0 0xff540000 0x0 0x20>;
1151 reg = <0x0 0xff540080 0x0 0x20>;
1156 reg = <0x0 0xff548000 0x0 0x20>;
1161 reg = <0x0 0xff548080 0x0 0x20>;
1166 reg = <0x0 0xff548100 0x0 0x20>;
1171 reg = <0x0 0xff548180 0x0 0x20>;
1176 reg = <0x0 0xff548200 0x0 0x20>;
1181 reg = <0x0 0xff550000 0x0 0x20>;
1186 reg = <0x0 0xff550080 0x0 0x20>;
1191 reg = <0x0 0xff550100 0x0 0x20>;
1196 reg = <0x0 0xff550180 0x0 0x20>;
1201 reg = <0x0 0xff558000 0x0 0x20>;
1206 reg = <0x0 0xff558080 0x0 0x20>;
1219 reg = <0x0 0xff040000 0x0 0x100>;
1231 reg = <0x0 0xff250000 0x0 0x100>;
1243 reg = <0x0 0xff260000 0x0 0x100>;
1255 reg = <0x0 0xff270000 0x0 0x100>;
1347 <0 RK_PB0 1 &pcfg_pull_none_smt>,
1348 <0 RK_PB1 1 &pcfg_pull_none_smt>;
1355 <0 RK_PC2 1 &pcfg_pull_none_smt>,
1356 <0 RK_PC3 1 &pcfg_pull_none_smt>;
1379 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1384 <0 RK_PA6 1 &pcfg_pull_none>;
1391 <0 RK_PB2 1 &pcfg_pull_up>,
1392 <0 RK_PB3 1 &pcfg_pull_up>;
1397 <0 RK_PB4 1 &pcfg_pull_none>;
1402 <0 RK_PB5 1 &pcfg_pull_none>;
1443 <0 RK_PC0 2 &pcfg_pull_up>,
1444 <0 RK_PC1 2 &pcfg_pull_up>;
1449 <0 RK_PC2 2 &pcfg_pull_none>;
1454 <0 RK_PC3 2 &pcfg_pull_none>;
1807 <0 RK_PA3 1 &pcfg_pull_up_8ma>;
2084 <0 RK_PB7 1 &pcfg_pull_none>;
2091 <0 RK_PC0 1 &pcfg_pull_none>;
2105 <0 RK_PC1 1 &pcfg_pull_none>;