Lines Matching +full:rcar +full:- +full:gen3 +full:- +full:hscif
1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car V3H (R8A77980) SoC
9 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/power/r8a77980-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
28 /* External CAN clock - to be overridden by boards that provide it */
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <0>;
36 #address-cells = <1>;
37 #size-cells = <0>;
41 compatible = "arm,cortex-a53";
44 power-domains = <&sysc R8A77980_PD_CA53_CPU0>;
45 next-level-cache = <&L2_CA53>;
46 enable-method = "psci";
51 compatible = "arm,cortex-a53";
54 power-domains = <&sysc R8A77980_PD_CA53_CPU1>;
55 next-level-cache = <&L2_CA53>;
56 enable-method = "psci";
61 compatible = "arm,cortex-a53";
64 power-domains = <&sysc R8A77980_PD_CA53_CPU2>;
65 next-level-cache = <&L2_CA53>;
66 enable-method = "psci";
71 compatible = "arm,cortex-a53";
74 power-domains = <&sysc R8A77980_PD_CA53_CPU3>;
75 next-level-cache = <&L2_CA53>;
76 enable-method = "psci";
79 L2_CA53: cache-controller {
81 power-domains = <&sysc R8A77980_PD_CA53_SCU>;
82 cache-unified;
83 cache-level = <2>;
88 compatible = "fixed-clock";
89 #clock-cells = <0>;
91 clock-frequency = <0>;
95 compatible = "fixed-clock";
96 #clock-cells = <0>;
98 clock-frequency = <0>;
101 /* External PCIe clock - can be overridden by the board */
103 compatible = "fixed-clock";
104 #clock-cells = <0>;
105 clock-frequency = <0>;
109 compatible = "arm,cortex-a53-pmu";
110 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
114 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
118 compatible = "arm,psci-1.0", "arm,psci-0.2";
122 /* External SCIF clock - to be overridden by boards that provide it */
124 compatible = "fixed-clock";
125 #clock-cells = <0>;
126 clock-frequency = <0>;
130 compatible = "simple-bus";
131 interrupt-parent = <&gic>;
133 #address-cells = <2>;
134 #size-cells = <2>;
138 compatible = "renesas,r8a77980-wdt",
139 "renesas,rcar-gen3-wdt";
142 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
148 compatible = "renesas,gpio-r8a77980",
149 "renesas,rcar-gen3-gpio";
152 #gpio-cells = <2>;
153 gpio-controller;
154 gpio-ranges = <&pfc 0 0 22>;
155 #interrupt-cells = <2>;
156 interrupt-controller;
158 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
163 compatible = "renesas,gpio-r8a77980",
164 "renesas,rcar-gen3-gpio";
167 #gpio-cells = <2>;
168 gpio-controller;
169 gpio-ranges = <&pfc 0 32 28>;
170 #interrupt-cells = <2>;
171 interrupt-controller;
173 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
178 compatible = "renesas,gpio-r8a77980",
179 "renesas,rcar-gen3-gpio";
182 #gpio-cells = <2>;
183 gpio-controller;
184 gpio-ranges = <&pfc 0 64 30>;
185 #interrupt-cells = <2>;
186 interrupt-controller;
188 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
193 compatible = "renesas,gpio-r8a77980",
194 "renesas,rcar-gen3-gpio";
197 #gpio-cells = <2>;
198 gpio-controller;
199 gpio-ranges = <&pfc 0 96 17>;
200 #interrupt-cells = <2>;
201 interrupt-controller;
203 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
208 compatible = "renesas,gpio-r8a77980",
209 "renesas,rcar-gen3-gpio";
212 #gpio-cells = <2>;
213 gpio-controller;
214 gpio-ranges = <&pfc 0 128 25>;
215 #interrupt-cells = <2>;
216 interrupt-controller;
218 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
223 compatible = "renesas,gpio-r8a77980",
224 "renesas,rcar-gen3-gpio";
227 #gpio-cells = <2>;
228 gpio-controller;
229 gpio-ranges = <&pfc 0 160 15>;
230 #interrupt-cells = <2>;
231 interrupt-controller;
233 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
238 compatible = "renesas,pfc-r8a77980";
243 compatible = "renesas,r8a77980-cmt0",
244 "renesas,rcar-gen3-cmt0";
249 clock-names = "fck";
250 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
256 compatible = "renesas,r8a77980-cmt1",
257 "renesas,rcar-gen3-cmt1";
268 clock-names = "fck";
269 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
275 compatible = "renesas,r8a77980-cmt1",
276 "renesas,rcar-gen3-cmt1";
287 clock-names = "fck";
288 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
294 compatible = "renesas,r8a77980-cmt1",
295 "renesas,rcar-gen3-cmt1";
306 clock-names = "fck";
307 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
312 cpg: clock-controller@e6150000 {
313 compatible = "renesas,r8a77980-cpg-mssr";
316 clock-names = "extal", "extalr";
317 #clock-cells = <2>;
318 #power-domain-cells = <0>;
319 #reset-cells = <1>;
322 rst: reset-controller@e6160000 {
323 compatible = "renesas,r8a77980-rst";
327 sysc: system-controller@e6180000 {
328 compatible = "renesas,r8a77980-sysc";
330 #power-domain-cells = <1>;
334 compatible = "renesas,r8a77980-thermal";
341 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
343 #thermal-sensor-cells = <1>;
346 intc_ex: interrupt-controller@e61c0000 {
347 compatible = "renesas,intc-ex-r8a77980", "renesas,irqc";
348 #interrupt-cells = <2>;
349 interrupt-controller;
358 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
363 compatible = "renesas,tmu-r8a77980", "renesas,tmu";
369 clock-names = "fck";
370 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
376 compatible = "renesas,tmu-r8a77980", "renesas,tmu";
382 clock-names = "fck";
383 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
389 compatible = "renesas,tmu-r8a77980", "renesas,tmu";
395 clock-names = "fck";
396 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
402 compatible = "renesas,tmu-r8a77980", "renesas,tmu";
408 clock-names = "fck";
409 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
415 compatible = "renesas,tmu-r8a77980", "renesas,tmu";
421 clock-names = "fck";
422 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
428 compatible = "renesas,i2c-r8a77980",
429 "renesas,rcar-gen3-i2c";
433 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
437 dma-names = "tx", "rx", "tx", "rx";
438 i2c-scl-internal-delay-ns = <6>;
439 #address-cells = <1>;
440 #size-cells = <0>;
445 compatible = "renesas,i2c-r8a77980",
446 "renesas,rcar-gen3-i2c";
450 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
454 dma-names = "tx", "rx", "tx", "rx";
455 i2c-scl-internal-delay-ns = <6>;
456 #address-cells = <1>;
457 #size-cells = <0>;
462 compatible = "renesas,i2c-r8a77980",
463 "renesas,rcar-gen3-i2c";
467 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
471 dma-names = "tx", "rx", "tx", "rx";
472 i2c-scl-internal-delay-ns = <6>;
473 #address-cells = <1>;
474 #size-cells = <0>;
479 compatible = "renesas,i2c-r8a77980",
480 "renesas,rcar-gen3-i2c";
484 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
486 i2c-scl-internal-delay-ns = <6>;
487 #address-cells = <1>;
488 #size-cells = <0>;
493 compatible = "renesas,i2c-r8a77980",
494 "renesas,rcar-gen3-i2c";
498 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
500 i2c-scl-internal-delay-ns = <6>;
501 #address-cells = <1>;
502 #size-cells = <0>;
507 compatible = "renesas,i2c-r8a77980",
508 "renesas,rcar-gen3-i2c";
512 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
516 dma-names = "tx", "rx", "tx", "rx";
517 i2c-scl-internal-delay-ns = <6>;
518 #address-cells = <1>;
519 #size-cells = <0>;
524 compatible = "renesas,hscif-r8a77980",
525 "renesas,rcar-gen3-hscif",
526 "renesas,hscif";
532 clock-names = "fck", "brg_int", "scif_clk";
535 dma-names = "tx", "rx", "tx", "rx";
536 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
542 compatible = "renesas,hscif-r8a77980",
543 "renesas,rcar-gen3-hscif",
544 "renesas,hscif";
550 clock-names = "fck", "brg_int", "scif_clk";
553 dma-names = "tx", "rx", "tx", "rx";
554 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
560 compatible = "renesas,hscif-r8a77980",
561 "renesas,rcar-gen3-hscif",
562 "renesas,hscif";
568 clock-names = "fck", "brg_int", "scif_clk";
571 dma-names = "tx", "rx", "tx", "rx";
572 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
578 compatible = "renesas,hscif-r8a77980",
579 "renesas,rcar-gen3-hscif",
580 "renesas,hscif";
586 clock-names = "fck", "brg_int", "scif_clk";
589 dma-names = "tx", "rx", "tx", "rx";
590 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
595 pcie_phy: pcie-phy@e65d0000 {
596 compatible = "renesas,r8a77980-pcie-phy";
598 #phy-cells = <0>;
600 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
606 compatible = "renesas,r8a77980-canfd",
607 "renesas,rcar-gen3-canfd";
614 clock-names = "fck", "canfd", "can_clk";
615 assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>;
616 assigned-clock-rates = <40000000>;
617 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
631 compatible = "renesas,etheravb-r8a77980",
632 "renesas,etheravb-rcar-gen3";
659 interrupt-names = "ch0", "ch1", "ch2", "ch3",
667 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
669 phy-mode = "rgmii";
671 #address-cells = <1>;
672 #size-cells = <0>;
677 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
679 #pwm-cells = <2>;
681 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
687 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
689 #pwm-cells = <2>;
691 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
697 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
699 #pwm-cells = <2>;
701 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
707 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
709 #pwm-cells = <2>;
711 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
717 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar";
719 #pwm-cells = <2>;
721 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
727 compatible = "renesas,scif-r8a77980",
728 "renesas,rcar-gen3-scif",
735 clock-names = "fck", "brg_int", "scif_clk";
738 dma-names = "tx", "rx", "tx", "rx";
739 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
745 compatible = "renesas,scif-r8a77980",
746 "renesas,rcar-gen3-scif",
753 clock-names = "fck", "brg_int", "scif_clk";
756 dma-names = "tx", "rx", "tx", "rx";
757 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
763 compatible = "renesas,scif-r8a77980",
764 "renesas,rcar-gen3-scif",
771 clock-names = "fck", "brg_int", "scif_clk";
774 dma-names = "tx", "rx", "tx", "rx";
775 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
781 compatible = "renesas,scif-r8a77980",
782 "renesas,rcar-gen3-scif",
789 clock-names = "fck", "brg_int", "scif_clk";
792 dma-names = "tx", "rx", "tx", "rx";
793 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
799 compatible = "renesas,tpu-r8a77980", "renesas,tpu";
803 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
805 #pwm-cells = <3>;
810 compatible = "renesas,msiof-r8a77980",
811 "renesas,rcar-gen3-msiof";
815 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
817 #address-cells = <1>;
818 #size-cells = <0>;
823 compatible = "renesas,msiof-r8a77980",
824 "renesas,rcar-gen3-msiof";
828 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
830 #address-cells = <1>;
831 #size-cells = <0>;
836 compatible = "renesas,msiof-r8a77980",
837 "renesas,rcar-gen3-msiof";
841 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
843 #address-cells = <1>;
844 #size-cells = <0>;
849 compatible = "renesas,msiof-r8a77980",
850 "renesas,rcar-gen3-msiof";
854 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
856 #address-cells = <1>;
857 #size-cells = <0>;
862 compatible = "renesas,vin-r8a77980";
866 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
872 #address-cells = <1>;
873 #size-cells = <0>;
876 #address-cells = <1>;
877 #size-cells = <0>;
883 remote-endpoint = <&csi40vin0>;
890 compatible = "renesas,vin-r8a77980";
894 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
900 #address-cells = <1>;
901 #size-cells = <0>;
904 #address-cells = <1>;
905 #size-cells = <0>;
911 remote-endpoint = <&csi40vin1>;
918 compatible = "renesas,vin-r8a77980";
922 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
928 #address-cells = <1>;
929 #size-cells = <0>;
932 #address-cells = <1>;
933 #size-cells = <0>;
939 remote-endpoint = <&csi40vin2>;
946 compatible = "renesas,vin-r8a77980";
950 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
956 #address-cells = <1>;
957 #size-cells = <0>;
960 #address-cells = <1>;
961 #size-cells = <0>;
967 remote-endpoint = <&csi40vin3>;
974 compatible = "renesas,vin-r8a77980";
978 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
984 #address-cells = <1>;
985 #size-cells = <0>;
988 #address-cells = <1>;
989 #size-cells = <0>;
995 remote-endpoint = <&csi41vin4>;
1002 compatible = "renesas,vin-r8a77980";
1006 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1012 #address-cells = <1>;
1013 #size-cells = <0>;
1016 #address-cells = <1>;
1017 #size-cells = <0>;
1023 remote-endpoint = <&csi41vin5>;
1030 compatible = "renesas,vin-r8a77980";
1034 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1040 #address-cells = <1>;
1041 #size-cells = <0>;
1044 #address-cells = <1>;
1045 #size-cells = <0>;
1051 remote-endpoint = <&csi41vin6>;
1058 compatible = "renesas,vin-r8a77980";
1062 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1068 #address-cells = <1>;
1069 #size-cells = <0>;
1072 #address-cells = <1>;
1073 #size-cells = <0>;
1079 remote-endpoint = <&csi41vin7>;
1086 compatible = "renesas,vin-r8a77980";
1090 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1097 compatible = "renesas,vin-r8a77980";
1101 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1108 compatible = "renesas,vin-r8a77980";
1112 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1119 compatible = "renesas,vin-r8a77980";
1123 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1130 compatible = "renesas,vin-r8a77980";
1134 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1141 compatible = "renesas,vin-r8a77980";
1145 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1152 compatible = "renesas,vin-r8a77980";
1156 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1163 compatible = "renesas,vin-r8a77980";
1167 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1173 dmac1: dma-controller@e7300000 {
1174 compatible = "renesas,dmac-r8a77980",
1175 "renesas,rcar-dmac";
1194 interrupt-names = "error",
1200 clock-names = "fck";
1201 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1203 #dma-cells = <1>;
1204 dma-channels = <16>;
1215 dmac2: dma-controller@e7310000 {
1216 compatible = "renesas,dmac-r8a77980",
1217 "renesas,rcar-dmac";
1236 interrupt-names = "error",
1242 clock-names = "fck";
1243 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1245 #dma-cells = <1>;
1246 dma-channels = <16>;
1258 compatible = "renesas,gether-r8a77980";
1262 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1264 #address-cells = <1>;
1265 #size-cells = <0>;
1270 compatible = "renesas,ipmmu-r8a77980";
1272 renesas,ipmmu-main = <&ipmmu_mm 0>;
1273 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1274 #iommu-cells = <1>;
1278 compatible = "renesas,ipmmu-r8a77980";
1280 renesas,ipmmu-main = <&ipmmu_mm 3>;
1281 power-domains = <&sysc R8A77980_PD_A3IR>;
1282 #iommu-cells = <1>;
1286 compatible = "renesas,ipmmu-r8a77980";
1290 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1291 #iommu-cells = <1>;
1295 compatible = "renesas,ipmmu-r8a77980";
1297 renesas,ipmmu-main = <&ipmmu_mm 10>;
1298 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1299 #iommu-cells = <1>;
1303 compatible = "renesas,ipmmu-r8a77980";
1305 renesas,ipmmu-main = <&ipmmu_mm 12>;
1306 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1307 #iommu-cells = <1>;
1311 compatible = "renesas,ipmmu-r8a77980";
1313 renesas,ipmmu-main = <&ipmmu_mm 14>;
1314 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1315 #iommu-cells = <1>;
1319 compatible = "renesas,ipmmu-r8a77980";
1321 renesas,ipmmu-main = <&ipmmu_mm 4>;
1322 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1323 #iommu-cells = <1>;
1327 compatible = "renesas,ipmmu-r8a77980";
1329 renesas,ipmmu-main = <&ipmmu_mm 11>;
1330 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1331 #iommu-cells = <1>;
1335 compatible = "renesas,sdhi-r8a77980",
1336 "renesas,rcar-gen3-sdhi";
1340 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1342 max-frequency = <200000000>;
1348 compatible = "renesas,r8a77980-rpc-if",
1349 "renesas,rcar-gen3-rpc-if";
1353 reg-names = "regs", "dirmap", "wbuf";
1356 clock-names = "rpc";
1357 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1359 #address-cells = <1>;
1360 #size-cells = <0>;
1364 gic: interrupt-controller@f1010000 {
1365 compatible = "arm,gic-400";
1366 #interrupt-cells = <3>;
1367 #address-cells = <0>;
1368 interrupt-controller;
1376 clock-names = "clk";
1377 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1382 compatible = "renesas,pcie-r8a77980",
1383 "renesas,pcie-rcar-gen3";
1385 #address-cells = <3>;
1386 #size-cells = <2>;
1387 bus-range = <0x00 0xff>;
1393 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
1397 #interrupt-cells = <1>;
1398 interrupt-map-mask = <0 0 0 0>;
1399 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1401 clock-names = "pcie", "pcie_bus";
1402 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1405 phy-names = "pcie";
1414 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1423 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1428 compatible = "renesas,r8a77980-csi2";
1432 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1437 #address-cells = <1>;
1438 #size-cells = <0>;
1441 #address-cells = <1>;
1442 #size-cells = <0>;
1448 remote-endpoint = <&vin0csi40>;
1452 remote-endpoint = <&vin1csi40>;
1456 remote-endpoint = <&vin2csi40>;
1460 remote-endpoint = <&vin3csi40>;
1467 compatible = "renesas,r8a77980-csi2";
1471 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1476 #address-cells = <1>;
1477 #size-cells = <0>;
1480 #address-cells = <1>;
1481 #size-cells = <0>;
1487 remote-endpoint = <&vin4csi41>;
1491 remote-endpoint = <&vin5csi41>;
1495 remote-endpoint = <&vin6csi41>;
1499 remote-endpoint = <&vin7csi41>;
1506 compatible = "renesas,du-r8a77980";
1510 clock-names = "du.0";
1511 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1513 reset-names = "du.0";
1519 #address-cells = <1>;
1520 #size-cells = <0>;
1531 remote-endpoint = <&lvds0_in>;
1537 lvds0: lvds-encoder@feb90000 {
1538 compatible = "renesas,r8a77980-lvds";
1541 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1546 #address-cells = <1>;
1547 #size-cells = <0>;
1552 remote-endpoint =
1571 thermal-zones {
1572 thermal-sensor-1 {
1573 polling-delay-passive = <250>;
1574 polling-delay = <1000>;
1575 thermal-sensors = <&tsc 0>;
1578 sensor1-passive {
1583 sensor1-critical {
1591 thermal-sensor-2 {
1592 polling-delay-passive = <250>;
1593 polling-delay = <1000>;
1594 thermal-sensors = <&tsc 1>;
1597 sensor2-passive {
1602 sensor2-critical {
1612 compatible = "arm,armv8-timer";
1613 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |