Lines Matching +full:0 +full:xe61a0000
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #size-cells = <0>;
39 a53_0: cpu@0 {
42 reg = <0>;
89 #clock-cells = <0>;
91 clock-frequency = <0>;
96 #clock-cells = <0>;
98 clock-frequency = <0>;
104 #clock-cells = <0>;
105 clock-frequency = <0>;
125 #clock-cells = <0>;
126 clock-frequency = <0>;
140 reg = <0 0xe6020000 0 0x0c>;
150 reg = <0 0xe6050000 0 0x50>;
154 gpio-ranges = <&pfc 0 0 22>;
165 reg = <0 0xe6051000 0 0x50>;
169 gpio-ranges = <&pfc 0 32 28>;
180 reg = <0 0xe6052000 0 0x50>;
184 gpio-ranges = <&pfc 0 64 30>;
195 reg = <0 0xe6053000 0 0x50>;
199 gpio-ranges = <&pfc 0 96 17>;
210 reg = <0 0xe6054000 0 0x50>;
214 gpio-ranges = <&pfc 0 128 25>;
225 reg = <0 0xe6055000 0 0x50>;
229 gpio-ranges = <&pfc 0 160 15>;
239 reg = <0 0xe6060000 0 0x50c>;
245 reg = <0 0xe60f0000 0 0x1004>;
258 reg = <0 0xe6130000 0 0x1004>;
277 reg = <0 0xe6140000 0 0x1004>;
296 reg = <0 0xe6148000 0 0x1004>;
314 reg = <0 0xe6150000 0 0x1000>;
318 #power-domain-cells = <0>;
324 reg = <0 0xe6160000 0 0x200>;
329 reg = <0 0xe6180000 0 0x440>;
335 reg = <0 0xe6198000 0 0x100>,
336 <0 0xe61a0000 0 0x100>;
350 reg = <0 0xe61c0000 0 0x200>;
351 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
364 reg = <0 0xe61e0000 0 0x30>;
377 reg = <0 0xe6fc0000 0 0x30>;
390 reg = <0 0xe6fd0000 0 0x30>;
403 reg = <0 0xe6fe0000 0 0x30>;
416 reg = <0 0xffc00000 0 0x30>;
430 reg = <0 0xe6500000 0 0x40>;
435 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
436 <&dmac2 0x91>, <&dmac2 0x90>;
440 #size-cells = <0>;
447 reg = <0 0xe6508000 0 0x40>;
452 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
453 <&dmac2 0x93>, <&dmac2 0x92>;
457 #size-cells = <0>;
464 reg = <0 0xe6510000 0 0x40>;
469 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
470 <&dmac2 0x95>, <&dmac2 0x94>;
474 #size-cells = <0>;
481 reg = <0 0xe66d0000 0 0x40>;
488 #size-cells = <0>;
495 reg = <0 0xe66d8000 0 0x40>;
502 #size-cells = <0>;
509 reg = <0 0xe66e0000 0 0x40>;
514 dmas = <&dmac1 0x9b>, <&dmac1 0x9a>,
515 <&dmac2 0x9b>, <&dmac2 0x9a>;
519 #size-cells = <0>;
527 reg = <0 0xe6540000 0 0x60>;
533 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
534 <&dmac2 0x31>, <&dmac2 0x30>;
545 reg = <0 0xe6550000 0 0x60>;
551 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
552 <&dmac2 0x33>, <&dmac2 0x32>;
563 reg = <0 0xe6560000 0 0x60>;
569 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
570 <&dmac2 0x35>, <&dmac2 0x34>;
581 reg = <0 0xe66a0000 0 0x60>;
587 dmas = <&dmac1 0x37>, <&dmac1 0x36>,
588 <&dmac2 0x37>, <&dmac2 0x36>;
597 reg = <0 0xe65d0000 0 0x8000>;
598 #phy-cells = <0>;
608 reg = <0 0xe66c0000 0 0x8000>;
633 reg = <0 0xe6800000 0 0x800>;
672 #size-cells = <0>;
678 reg = <0 0xe6e30000 0 0x10>;
688 reg = <0 0xe6e31000 0 0x10>;
698 reg = <0 0xe6e32000 0 0x10>;
708 reg = <0 0xe6e33000 0 0x10>;
718 reg = <0 0xe6e34000 0 0x10>;
730 reg = <0 0xe6e60000 0 0x40>;
736 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
737 <&dmac2 0x51>, <&dmac2 0x50>;
748 reg = <0 0xe6e68000 0 0x40>;
754 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
755 <&dmac2 0x53>, <&dmac2 0x52>;
766 reg = <0 0xe6c50000 0 0x40>;
772 dmas = <&dmac1 0x57>, <&dmac1 0x56>,
773 <&dmac2 0x57>, <&dmac2 0x56>;
784 reg = <0 0xe6c40000 0 0x40>;
790 dmas = <&dmac1 0x59>, <&dmac1 0x58>,
791 <&dmac2 0x59>, <&dmac2 0x58>;
800 reg = <0 0xe6e80000 0 0x148>;
812 reg = <0 0xe6e90000 0 0x64>;
818 #size-cells = <0>;
825 reg = <0 0xe6ea0000 0 0x0064>;
831 #size-cells = <0>;
838 reg = <0 0xe6c00000 0 0x0064>;
844 #size-cells = <0>;
851 reg = <0 0xe6c10000 0 0x0064>;
857 #size-cells = <0>;
863 reg = <0 0xe6ef0000 0 0x1000>;
868 renesas,id = <0>;
873 #size-cells = <0>;
877 #size-cells = <0>;
891 reg = <0 0xe6ef1000 0 0x1000>;
901 #size-cells = <0>;
905 #size-cells = <0>;
919 reg = <0 0xe6ef2000 0 0x1000>;
929 #size-cells = <0>;
933 #size-cells = <0>;
947 reg = <0 0xe6ef3000 0 0x1000>;
957 #size-cells = <0>;
961 #size-cells = <0>;
975 reg = <0 0xe6ef4000 0 0x1000>;
985 #size-cells = <0>;
989 #size-cells = <0>;
1003 reg = <0 0xe6ef5000 0 0x1000>;
1013 #size-cells = <0>;
1017 #size-cells = <0>;
1031 reg = <0 0xe6ef6000 0 0x1000>;
1041 #size-cells = <0>;
1045 #size-cells = <0>;
1059 reg = <0 0xe6ef7000 0 0x1000>;
1069 #size-cells = <0>;
1073 #size-cells = <0>;
1087 reg = <0 0xe6ef8000 0 0x1000>;
1098 reg = <0 0xe6ef9000 0 0x1000>;
1109 reg = <0 0xe6efa000 0 0x1000>;
1120 reg = <0 0xe6efb000 0 0x1000>;
1131 reg = <0 0xe6efc000 0 0x1000>;
1142 reg = <0 0xe6efd000 0 0x1000>;
1153 reg = <0 0xe6efe000 0 0x1000>;
1164 reg = <0 0xe6eff000 0 0x1000>;
1176 reg = <0 0xe7300000 0 0x10000>;
1205 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1218 reg = <0 0xe7310000 0 0x10000>;
1259 reg = <0 0xe7400000 0 0x1000>;
1265 #size-cells = <0>;
1271 reg = <0 0xe7740000 0 0x1000>;
1272 renesas,ipmmu-main = <&ipmmu_mm 0>;
1279 reg = <0 0xff8b0000 0 0x1000>;
1287 reg = <0 0xe67b0000 0 0x1000>;
1296 reg = <0 0xffc80000 0 0x1000>;
1304 reg = <0 0xfe990000 0 0x1000>;
1312 reg = <0 0xfebd0000 0 0x1000>;
1320 reg = <0 0xe7b00000 0 0x1000>;
1328 reg = <0 0xe7960000 0 0x1000>;
1337 reg = <0 0xee140000 0 0x2000>;
1350 reg = <0 0xee200000 0 0x200>,
1351 <0 0x08000000 0 0x4000000>,
1352 <0 0xee208000 0 0x100>;
1360 #size-cells = <0>;
1367 #address-cells = <0>;
1369 reg = <0x0 0xf1010000 0 0x1000>,
1370 <0x0 0xf1020000 0 0x20000>,
1371 <0x0 0xf1040000 0 0x20000>,
1372 <0x0 0xf1060000 0 0x20000>;
1384 reg = <0 0xfe000000 0 0x80000>;
1387 bus-range = <0x00 0xff>;
1389 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x0100000>,
1390 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000>,
1391 <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>,
1392 <0x42000000 0 0x38000000 0 0x38000000 0 0x8000000>;
1393 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
1398 interrupt-map-mask = <0 0 0 0>;
1399 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1411 reg = <0 0xfea20000 0 0x5000>;
1421 reg = <0 0xfea27000 0 0x200>;
1429 reg = <0 0xfeaa0000 0 0x10000>;
1438 #size-cells = <0>;
1442 #size-cells = <0>;
1446 csi40vin0: endpoint@0 {
1447 reg = <0>;
1468 reg = <0 0xfeab0000 0 0x10000>;
1477 #size-cells = <0>;
1481 #size-cells = <0>;
1485 csi41vin4: endpoint@0 {
1486 reg = <0>;
1507 reg = <0 0xfeb00000 0 0x80000>;
1510 clock-names = "du.0";
1513 reset-names = "du.0";
1514 renesas,vsps = <&vspd0 0>;
1520 #size-cells = <0>;
1522 port@0 {
1523 reg = <0>;
1539 reg = <0 0xfeb90000 0 0x14>;
1547 #size-cells = <0>;
1549 port@0 {
1550 reg = <0>;
1567 reg = <0 0xfff00044 0 4>;
1575 thermal-sensors = <&tsc 0>;