Lines Matching +full:0 +full:xe6550000
30 #clock-cells = <0>;
31 clock-frequency = <0>;
36 #size-cells = <0>;
38 a53_0: cpu@0 {
41 reg = <0>;
68 #clock-cells = <0>;
70 clock-frequency = <0>;
75 #clock-cells = <0>;
77 clock-frequency = <0>;
95 #clock-cells = <0>;
96 clock-frequency = <0>;
110 reg = <0 0xe6020000 0 0x0c>;
120 reg = <0 0xe6050000 0 0x50>;
124 gpio-ranges = <&pfc 0 0 22>;
135 reg = <0 0xe6051000 0 0x50>;
139 gpio-ranges = <&pfc 0 32 28>;
150 reg = <0 0xe6052000 0 0x50>;
154 gpio-ranges = <&pfc 0 64 17>;
165 reg = <0 0xe6053000 0 0x50>;
169 gpio-ranges = <&pfc 0 96 17>;
180 reg = <0 0xe6054000 0 0x50>;
184 gpio-ranges = <&pfc 0 128 6>;
195 reg = <0 0xe6055000 0 0x50>;
199 gpio-ranges = <&pfc 0 160 15>;
209 reg = <0 0xe6060000 0 0x504>;
215 reg = <0 0xe60f0000 0 0x1004>;
228 reg = <0 0xe6130000 0 0x1004>;
247 reg = <0 0xe6140000 0 0x1004>;
266 reg = <0 0xe6148000 0 0x1004>;
284 reg = <0 0xe6150000 0 0x1000>;
288 #power-domain-cells = <0>;
294 reg = <0 0xe6160000 0 0x200>;
299 reg = <0 0xe6180000 0 0x440>;
305 reg = <0 0xe6190000 0 0x10>,
306 <0 0xe6190100 0 0x120>;
313 #thermal-sensor-cells = <0>;
320 reg = <0 0xe61c0000 0 0x200>;
321 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
334 reg = <0 0xe61e0000 0 0x30>;
347 reg = <0 0xe6fc0000 0 0x30>;
360 reg = <0 0xe6fd0000 0 0x30>;
373 reg = <0 0xe6fe0000 0 0x30>;
386 reg = <0 0xffc00000 0 0x30>;
400 reg = <0 0xe6500000 0 0x40>;
405 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
406 <&dmac2 0x91>, <&dmac2 0x90>;
410 #size-cells = <0>;
417 reg = <0 0xe6508000 0 0x40>;
422 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
423 <&dmac2 0x93>, <&dmac2 0x92>;
427 #size-cells = <0>;
434 reg = <0 0xe6510000 0 0x40>;
439 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
440 <&dmac2 0x95>, <&dmac2 0x94>;
444 #size-cells = <0>;
451 reg = <0 0xe66d0000 0 0x40>;
456 dmas = <&dmac1 0x97>, <&dmac1 0x96>,
457 <&dmac2 0x97>, <&dmac2 0x96>;
461 #size-cells = <0>;
468 reg = <0 0xe66d8000 0 0x40>;
473 dmas = <&dmac1 0x99>, <&dmac1 0x98>,
474 <&dmac2 0x99>, <&dmac2 0x98>;
478 #size-cells = <0>;
486 reg = <0 0xe6540000 0 96>;
492 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
493 <&dmac2 0x31>, <&dmac2 0x30>;
504 reg = <0 0xe6550000 0 96>;
510 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
511 <&dmac2 0x33>, <&dmac2 0x32>;
522 reg = <0 0xe6560000 0 96>;
528 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
529 <&dmac2 0x35>, <&dmac2 0x34>;
539 reg = <0 0xe66a0000 0 96>;
545 dmas = <&dmac1 0x37>, <&dmac1 0x36>,
546 <&dmac2 0x37>, <&dmac2 0x36>;
556 reg = <0 0xe66c0000 0 0x8000>;
581 reg = <0 0xe6800000 0 0x800>;
620 #size-cells = <0>;
626 reg = <0 0xe6e30000 0 8>;
636 reg = <0 0xe6e31000 0 8>;
646 reg = <0 0xe6e32000 0 8>;
656 reg = <0 0xe6e33000 0 8>;
666 reg = <0 0xe6e34000 0 8>;
678 reg = <0 0xe6e60000 0 64>;
684 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
685 <&dmac2 0x51>, <&dmac2 0x50>;
696 reg = <0 0xe6e68000 0 64>;
702 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
703 <&dmac2 0x53>, <&dmac2 0x52>;
714 reg = <0 0xe6c50000 0 64>;
720 dmas = <&dmac1 0x57>, <&dmac1 0x56>,
721 <&dmac2 0x57>, <&dmac2 0x56>;
731 reg = <0 0xe6c40000 0 64>;
737 dmas = <&dmac1 0x59>, <&dmac1 0x58>,
738 <&dmac2 0x59>, <&dmac2 0x58>;
747 reg = <0 0xe6e80000 0 0x148>;
759 reg = <0 0xe6e90000 0 0x64>;
764 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
765 <&dmac2 0x41>, <&dmac2 0x40>;
768 #size-cells = <0>;
775 reg = <0 0xe6ea0000 0 0x0064>;
780 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
781 <&dmac2 0x43>, <&dmac2 0x42>;
784 #size-cells = <0>;
791 reg = <0 0xe6c00000 0 0x0064>;
796 dmas = <&dmac1 0x45>, <&dmac1 0x44>,
797 <&dmac2 0x45>, <&dmac2 0x44>;
800 #size-cells = <0>;
807 reg = <0 0xe6c10000 0 0x0064>;
812 dmas = <&dmac1 0x47>, <&dmac1 0x46>,
813 <&dmac2 0x47>, <&dmac2 0x46>;
816 #size-cells = <0>;
822 reg = <0 0xe6ef0000 0 0x1000>;
827 renesas,id = <0>;
832 #size-cells = <0>;
836 #size-cells = <0>;
850 reg = <0 0xe6ef1000 0 0x1000>;
860 #size-cells = <0>;
864 #size-cells = <0>;
878 reg = <0 0xe6ef2000 0 0x1000>;
888 #size-cells = <0>;
892 #size-cells = <0>;
906 reg = <0 0xe6ef3000 0 0x1000>;
916 #size-cells = <0>;
920 #size-cells = <0>;
935 reg = <0 0xe7300000 0 0x10000>;
954 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
963 reg = <0 0xe7310000 0 0x10000>;
990 reg = <0 0xe7740000 0 0x1000>;
991 renesas,ipmmu-main = <&ipmmu_mm 0>;
998 reg = <0 0xff8b0000 0 0x1000>;
1006 reg = <0 0xe67b0000 0 0x1000>;
1015 reg = <0 0xffc80000 0 0x1000>;
1023 reg = <0 0xfebd0000 0 0x1000>;
1032 reg = <0 0xee140000 0 0x2000>;
1045 reg = <0 0xee200000 0 0x200>,
1046 <0 0x08000000 0 0x4000000>,
1047 <0 0xee208000 0 0x100>;
1055 #size-cells = <0>;
1062 #address-cells = <0>;
1064 reg = <0 0xf1010000 0 0x1000>,
1065 <0 0xf1020000 0 0x20000>,
1066 <0 0xf1040000 0 0x20000>,
1067 <0 0xf1060000 0 0x20000>;
1078 reg = <0 0xfea20000 0 0x5000>;
1088 reg = <0 0xfea27000 0 0x200>;
1096 reg = <0 0xfeaa0000 0 0x10000>;
1105 #size-cells = <0>;
1109 #size-cells = <0>;
1113 csi40vin0: endpoint@0 {
1114 reg = <0>;
1135 reg = <0 0xfeb00000 0 0x80000>;
1138 clock-names = "du.0";
1141 reset-names = "du.0";
1142 renesas,vsps = <&vspd0 0>;
1148 #size-cells = <0>;
1150 port@0 {
1151 reg = <0>;
1167 reg = <0 0xfeb90000 0 0x14>;
1175 #size-cells = <0>;
1177 port@0 {
1178 reg = <0>;
1194 reg = <0 0xfff00044 0 4>;