Lines Matching +full:0 +full:xee020000
34 * The external audio clocks are configured as 0 Hz fixed frequency
40 #clock-cells = <0>;
41 clock-frequency = <0>;
46 #clock-cells = <0>;
47 clock-frequency = <0>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
59 #clock-cells = <0>;
60 clock-frequency = <0>;
105 #size-cells = <0>;
107 a57_0: cpu@0 {
109 reg = <0x0>;
123 reg = <0x1>;
133 L2_CA57: cache-controller-0 {
143 CPU_SLEEP_0: cpu-sleep-0 {
145 arm,psci-suspend-param = <0x0010000>;
156 #clock-cells = <0>;
158 clock-frequency = <0>;
163 #clock-cells = <0>;
165 clock-frequency = <0>;
171 #clock-cells = <0>;
172 clock-frequency = <0>;
191 #clock-cells = <0>;
192 clock-frequency = <0>;
205 reg = <0 0xe6020000 0 0x0c>;
215 reg = <0 0xe6050000 0 0x50>;
219 gpio-ranges = <&pfc 0 0 16>;
230 reg = <0 0xe6051000 0 0x50>;
234 gpio-ranges = <&pfc 0 32 29>;
245 reg = <0 0xe6052000 0 0x50>;
249 gpio-ranges = <&pfc 0 64 15>;
260 reg = <0 0xe6053000 0 0x50>;
264 gpio-ranges = <&pfc 0 96 16>;
275 reg = <0 0xe6054000 0 0x50>;
279 gpio-ranges = <&pfc 0 128 18>;
290 reg = <0 0xe6055000 0 0x50>;
294 gpio-ranges = <&pfc 0 160 26>;
305 reg = <0 0xe6055400 0 0x50>;
309 gpio-ranges = <&pfc 0 192 32>;
320 reg = <0 0xe6055800 0 0x50>;
324 gpio-ranges = <&pfc 0 224 4>;
334 reg = <0 0xe6060000 0 0x50c>;
340 reg = <0 0xe60f0000 0 0x1004>;
353 reg = <0 0xe6130000 0 0x1004>;
372 reg = <0 0xe6140000 0 0x1004>;
391 reg = <0 0xe6148000 0 0x1004>;
409 reg = <0 0xe6150000 0 0x1000>;
413 #power-domain-cells = <0>;
419 reg = <0 0xe6160000 0 0x0200>;
424 reg = <0 0xe6180000 0 0x0400>;
430 reg = <0 0xe6198000 0 0x100>,
431 <0 0xe61a0000 0 0x100>,
432 <0 0xe61a8000 0 0x100>;
446 reg = <0 0xe61c0000 0 0x200>;
447 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
460 #size-cells = <0>;
463 reg = <0 0xe6500000 0 0x40>;
468 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
469 <&dmac2 0x91>, <&dmac2 0x90>;
477 #size-cells = <0>;
480 reg = <0 0xe6508000 0 0x40>;
485 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
486 <&dmac2 0x93>, <&dmac2 0x92>;
494 #size-cells = <0>;
497 reg = <0 0xe6510000 0 0x40>;
502 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
503 <&dmac2 0x95>, <&dmac2 0x94>;
511 #size-cells = <0>;
514 reg = <0 0xe66d0000 0 0x40>;
519 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
527 #size-cells = <0>;
530 reg = <0 0xe66d8000 0 0x40>;
535 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
543 #size-cells = <0>;
546 reg = <0 0xe66e0000 0 0x40>;
551 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
559 #size-cells = <0>;
562 reg = <0 0xe66e8000 0 0x40>;
567 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
575 #size-cells = <0>;
579 reg = <0 0xe60b0000 0 0x425>;
584 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
593 reg = <0 0xe6540000 0 0x60>;
599 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
600 <&dmac2 0x31>, <&dmac2 0x30>;
611 reg = <0 0xe6550000 0 0x60>;
617 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
618 <&dmac2 0x33>, <&dmac2 0x32>;
629 reg = <0 0xe6560000 0 0x60>;
635 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
636 <&dmac2 0x35>, <&dmac2 0x34>;
647 reg = <0 0xe66a0000 0 0x60>;
653 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
664 reg = <0 0xe66b0000 0 0x60>;
670 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
680 reg = <0 0xe6590000 0 0x200>;
683 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
684 <&usb_dmac1 0>, <&usb_dmac1 1>;
697 reg = <0 0xe65a0000 0 0x100>;
711 reg = <0 0xe65b0000 0 0x100>;
725 reg = <0 0xe65ee000 0 0x90>;
731 #phy-cells = <0>;
738 reg = <0x0 0xe6601000 0 0x1000>;
747 reg = <0 0xe6700000 0 0x10000>;
776 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
789 reg = <0 0xe7300000 0 0x10000>;
818 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
831 reg = <0 0xe7310000 0 0x10000>;
872 reg = <0 0xe6740000 0 0x1000>;
873 renesas,ipmmu-main = <&ipmmu_mm 0>;
880 reg = <0 0xe7740000 0 0x1000>;
888 reg = <0 0xe6570000 0 0x1000>;
896 reg = <0 0xe67b0000 0 0x1000>;
905 reg = <0 0xec670000 0 0x1000>;
913 reg = <0 0xfd800000 0 0x1000>;
921 reg = <0 0xffc80000 0 0x1000>;
929 reg = <0 0xfe6b0000 0 0x1000>;
937 reg = <0 0xfebd0000 0 0x1000>;
945 reg = <0 0xfe990000 0 0x1000>;
954 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
993 #size-cells = <0>;
1000 reg = <0 0xe6c30000 0 0x1000>;
1016 reg = <0 0xe6c38000 0 0x1000>;
1032 reg = <0 0xe66c0000 0 0x8000>;
1056 reg = <0 0xe6e30000 0 8>;
1066 reg = <0 0xe6e31000 0 8>;
1076 reg = <0 0xe6e32000 0 8>;
1086 reg = <0 0xe6e33000 0 8>;
1096 reg = <0 0xe6e34000 0 8>;
1106 reg = <0 0xe6e35000 0 8>;
1116 reg = <0 0xe6e36000 0 8>;
1127 reg = <0 0xe6e60000 0 64>;
1133 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1134 <&dmac2 0x51>, <&dmac2 0x50>;
1144 reg = <0 0xe6e68000 0 64>;
1150 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1151 <&dmac2 0x53>, <&dmac2 0x52>;
1161 reg = <0 0xe6e88000 0 64>;
1167 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1168 <&dmac2 0x13>, <&dmac2 0x12>;
1178 reg = <0 0xe6c50000 0 64>;
1184 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1194 reg = <0 0xe6c40000 0 64>;
1200 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1210 reg = <0 0xe6f30000 0 64>;
1216 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1217 <&dmac2 0x5b>, <&dmac2 0x5a>;
1226 reg = <0 0xe6e80000 0 0x148>;
1238 reg = <0 0xe6e90000 0 0x0064>;
1241 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1242 <&dmac2 0x41>, <&dmac2 0x40>;
1247 #size-cells = <0>;
1254 reg = <0 0xe6ea0000 0 0x0064>;
1257 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1258 <&dmac2 0x43>, <&dmac2 0x42>;
1263 #size-cells = <0>;
1270 reg = <0 0xe6c00000 0 0x0064>;
1273 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1278 #size-cells = <0>;
1285 reg = <0 0xe6c10000 0 0x0064>;
1288 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1293 #size-cells = <0>;
1299 reg = <0 0xe6ef0000 0 0x1000>;
1304 renesas,id = <0>;
1309 #size-cells = <0>;
1313 #size-cells = <0>;
1317 vin0csi20: endpoint@0 {
1318 reg = <0>;
1331 reg = <0 0xe6ef1000 0 0x1000>;
1341 #size-cells = <0>;
1345 #size-cells = <0>;
1349 vin1csi20: endpoint@0 {
1350 reg = <0>;
1363 reg = <0 0xe6ef2000 0 0x1000>;
1373 #size-cells = <0>;
1377 #size-cells = <0>;
1381 vin2csi20: endpoint@0 {
1382 reg = <0>;
1395 reg = <0 0xe6ef3000 0 0x1000>;
1405 #size-cells = <0>;
1409 #size-cells = <0>;
1413 vin3csi20: endpoint@0 {
1414 reg = <0>;
1427 reg = <0 0xe6ef4000 0 0x1000>;
1437 #size-cells = <0>;
1441 #size-cells = <0>;
1445 vin4csi20: endpoint@0 {
1446 reg = <0>;
1459 reg = <0 0xe6ef5000 0 0x1000>;
1469 #size-cells = <0>;
1473 #size-cells = <0>;
1477 vin5csi20: endpoint@0 {
1478 reg = <0>;
1491 reg = <0 0xe6ef6000 0 0x1000>;
1501 #size-cells = <0>;
1505 #size-cells = <0>;
1509 vin6csi20: endpoint@0 {
1510 reg = <0>;
1523 reg = <0 0xe6ef7000 0 0x1000>;
1533 #size-cells = <0>;
1537 #size-cells = <0>;
1541 vin7csi20: endpoint@0 {
1542 reg = <0>;
1557 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1563 * clkout : #clock-cells = <0>; <&rcar_sound>;
1567 reg = <0 0xec500000 0 0x1000>, /* SCU */
1568 <0 0xec5a0000 0 0x100>, /* ADG */
1569 <0 0xec540000 0 0x1000>, /* SSIU */
1570 <0 0xec541000 0 0x280>, /* SSI */
1571 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1594 "ssi.1", "ssi.0",
1597 "src.1", "src.0",
1598 "mix.1", "mix.0",
1599 "ctu.1", "ctu.0",
1600 "dvc.0", "dvc.1",
1612 "ssi.1", "ssi.0";
1616 dvc0: dvc-0 {
1617 dmas = <&audma1 0xbc>;
1621 dmas = <&audma1 0xbe>;
1627 mix0: mix-0 { };
1632 ctu00: ctu-0 { };
1643 src0: src-0 {
1645 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1650 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1655 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1660 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1665 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1670 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1675 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1680 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1685 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1690 dmas = <&audma0 0x97>, <&audma1 0xba>;
1696 ssiu00: ssiu-0 {
1697 dmas = <&audma0 0x15>, <&audma1 0x16>;
1701 dmas = <&audma0 0x35>, <&audma1 0x36>;
1705 dmas = <&audma0 0x37>, <&audma1 0x38>;
1709 dmas = <&audma0 0x47>, <&audma1 0x48>;
1713 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1717 dmas = <&audma0 0x43>, <&audma1 0x44>;
1721 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1725 dmas = <&audma0 0x53>, <&audma1 0x54>;
1729 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1733 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1737 dmas = <&audma0 0x57>, <&audma1 0x58>;
1741 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1745 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1749 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1753 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1757 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1761 dmas = <&audma0 0x63>, <&audma1 0x64>;
1765 dmas = <&audma0 0x67>, <&audma1 0x68>;
1769 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
1773 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
1777 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
1781 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
1785 dmas = <&audma0 0xED>, <&audma1 0xEE>;
1789 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
1793 dmas = <&audma0 0x6f>, <&audma1 0x70>;
1797 dmas = <&audma0 0x21>, <&audma1 0x22>;
1801 dmas = <&audma0 0x23>, <&audma1 0x24>;
1805 dmas = <&audma0 0x25>, <&audma1 0x26>;
1809 dmas = <&audma0 0x27>, <&audma1 0x28>;
1813 dmas = <&audma0 0x29>, <&audma1 0x2A>;
1817 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
1821 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
1825 dmas = <&audma0 0x71>, <&audma1 0x72>;
1829 dmas = <&audma0 0x17>, <&audma1 0x18>;
1833 dmas = <&audma0 0x19>, <&audma1 0x1A>;
1837 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
1841 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
1845 dmas = <&audma0 0x1F>, <&audma1 0x20>;
1849 dmas = <&audma0 0x31>, <&audma1 0x32>;
1853 dmas = <&audma0 0x33>, <&audma1 0x34>;
1857 dmas = <&audma0 0x73>, <&audma1 0x74>;
1861 dmas = <&audma0 0x75>, <&audma1 0x76>;
1865 dmas = <&audma0 0x79>, <&audma1 0x7a>;
1869 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
1873 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
1877 dmas = <&audma0 0x7F>, <&audma1 0x80>;
1881 dmas = <&audma0 0x81>, <&audma1 0x82>;
1885 dmas = <&audma0 0x83>, <&audma1 0x84>;
1889 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
1893 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
1897 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
1901 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
1907 ssi0: ssi-0 {
1909 dmas = <&audma0 0x01>, <&audma1 0x02>;
1914 dmas = <&audma0 0x03>, <&audma1 0x04>;
1919 dmas = <&audma0 0x05>, <&audma1 0x06>;
1924 dmas = <&audma0 0x07>, <&audma1 0x08>;
1929 dmas = <&audma0 0x09>, <&audma1 0x0a>;
1934 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
1939 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
1944 dmas = <&audma0 0x0f>, <&audma1 0x10>;
1949 dmas = <&audma0 0x11>, <&audma1 0x12>;
1954 dmas = <&audma0 0x13>, <&audma1 0x14>;
1963 reg = <0 0xec700000 0 0x10000>;
1997 reg = <0 0xec720000 0 0x10000>;
2031 reg = <0 0xee000000 0 0xc00>;
2042 reg = <0 0xee020000 0 0x400>;
2052 reg = <0 0xee080000 0 0x100>;
2064 reg = <0 0xee0a0000 0 0x100>;
2076 reg = <0 0xee080100 0 0x100>;
2089 reg = <0 0xee0a0100 0 0x100>;
2103 reg = <0 0xee080200 0 0x700>;
2115 reg = <0 0xee0a0200 0 0x700>;
2126 reg = <0 0xee100000 0 0x2000>;
2139 reg = <0 0xee120000 0 0x2000>;
2152 reg = <0 0xee140000 0 0x2000>;
2165 reg = <0 0xee160000 0 0x2000>;
2178 reg = <0 0xee300000 0 0x200000>;
2189 #address-cells = <0>;
2191 reg = <0x0 0xf1010000 0 0x1000>,
2192 <0x0 0xf1020000 0 0x20000>,
2193 <0x0 0xf1040000 0 0x20000>,
2194 <0x0 0xf1060000 0 0x20000>;
2206 reg = <0 0xfe000000 0 0x80000>;
2209 bus-range = <0x00 0xff>;
2211 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2212 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2213 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2214 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2216 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2221 interrupt-map-mask = <0 0 0 0>;
2222 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2233 reg = <0 0xee800000 0 0x80000>;
2236 bus-range = <0x00 0xff>;
2238 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2239 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2240 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2241 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2243 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2248 interrupt-map-mask = <0 0 0 0>;
2249 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2259 reg = <0 0xfe940000 0 0x2400>;
2269 reg = <0 0xfe950000 0 0x200>;
2277 reg = <0 0xfe960000 0 0x8000>;
2288 reg = <0 0xfe9a0000 0 0x8000>;
2299 reg = <0 0xfea20000 0 0x5000>;
2310 reg = <0 0xfea28000 0 0x5000>;
2321 reg = <0 0xfe96f000 0 0x200>;
2329 reg = <0 0xfea27000 0 0x200>;
2337 reg = <0 0xfea2f000 0 0x200>;
2345 reg = <0 0xfe9af000 0 0x200>;
2354 reg = <0 0xfea40000 0 0x1000>;
2363 reg = <0 0xfea50000 0 0x1000>;
2372 reg = <0 0xfea70000 0 0x1000>;
2380 reg = <0 0xfea80000 0 0x10000>;
2389 #size-cells = <0>;
2393 #size-cells = <0>;
2397 csi20vin0: endpoint@0 {
2398 reg = <0>;
2435 reg = <0 0xfeaa0000 0 0x10000>;
2444 #size-cells = <0>;
2448 #size-cells = <0>;
2452 csi40vin0: endpoint@0 {
2453 reg = <0>;
2491 reg = <0 0xfead0000 0 0x10000>;
2502 #size-cells = <0>;
2503 port@0 {
2504 reg = <0>;
2517 reg = <0 0xfeb00000 0 0x80000>;
2523 clock-names = "du.0", "du.1", "du.3";
2525 reset-names = "du.0", "du.3";
2528 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
2534 #size-cells = <0>;
2536 port@0 {
2537 reg = <0>;
2558 reg = <0 0xfeb90000 0 0x14>;
2566 #size-cells = <0>;
2568 port@0 {
2569 reg = <0>;
2584 reg = <0 0xfff00044 0 4>;
2592 thermal-sensors = <&tsc 0>;
2661 #clock-cells = <0>;
2662 clock-frequency = <0>;
2667 #clock-cells = <0>;
2668 clock-frequency = <0>;