Lines Matching +full:0 +full:xe6550000
31 * The external audio clocks are configured as 0 Hz fixed frequency
37 #clock-cells = <0>;
38 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
49 #clock-cells = <0>;
50 clock-frequency = <0>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
128 #size-cells = <0>;
156 a57_0: cpu@0 {
158 reg = <0x0>;
173 reg = <0x1>;
187 reg = <0x100>;
202 reg = <0x101>;
215 reg = <0x102>;
228 reg = <0x103>;
239 L2_CA57: cache-controller-0 {
256 CPU_SLEEP_0: cpu-sleep-0 {
258 arm,psci-suspend-param = <0x0010000>;
267 arm,psci-suspend-param = <0x0010000>;
278 #clock-cells = <0>;
280 clock-frequency = <0>;
285 #clock-cells = <0>;
287 clock-frequency = <0>;
293 #clock-cells = <0>;
294 clock-frequency = <0>;
321 #clock-cells = <0>;
322 clock-frequency = <0>;
335 reg = <0 0xe6020000 0 0x0c>;
345 reg = <0 0xe6050000 0 0x50>;
349 gpio-ranges = <&pfc 0 0 16>;
360 reg = <0 0xe6051000 0 0x50>;
364 gpio-ranges = <&pfc 0 32 29>;
375 reg = <0 0xe6052000 0 0x50>;
379 gpio-ranges = <&pfc 0 64 15>;
390 reg = <0 0xe6053000 0 0x50>;
394 gpio-ranges = <&pfc 0 96 16>;
405 reg = <0 0xe6054000 0 0x50>;
409 gpio-ranges = <&pfc 0 128 18>;
420 reg = <0 0xe6055000 0 0x50>;
424 gpio-ranges = <&pfc 0 160 26>;
435 reg = <0 0xe6055400 0 0x50>;
439 gpio-ranges = <&pfc 0 192 32>;
450 reg = <0 0xe6055800 0 0x50>;
454 gpio-ranges = <&pfc 0 224 4>;
464 reg = <0 0xe6060000 0 0x50c>;
470 reg = <0 0xe60f0000 0 0x1004>;
483 reg = <0 0xe6130000 0 0x1004>;
502 reg = <0 0xe6140000 0 0x1004>;
521 reg = <0 0xe6148000 0 0x1004>;
539 reg = <0 0xe6150000 0 0x1000>;
543 #power-domain-cells = <0>;
549 reg = <0 0xe6160000 0 0x0200>;
554 reg = <0 0xe6180000 0 0x0400>;
560 reg = <0 0xe6198000 0 0x100>,
561 <0 0xe61a0000 0 0x100>,
562 <0 0xe61a8000 0 0x100>;
576 reg = <0 0xe61c0000 0 0x200>;
577 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
590 #size-cells = <0>;
593 reg = <0 0xe6500000 0 0x40>;
598 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
599 <&dmac2 0x91>, <&dmac2 0x90>;
607 #size-cells = <0>;
610 reg = <0 0xe6508000 0 0x40>;
615 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
616 <&dmac2 0x93>, <&dmac2 0x92>;
624 #size-cells = <0>;
627 reg = <0 0xe6510000 0 0x40>;
632 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
633 <&dmac2 0x95>, <&dmac2 0x94>;
641 #size-cells = <0>;
644 reg = <0 0xe66d0000 0 0x40>;
649 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
657 #size-cells = <0>;
660 reg = <0 0xe66d8000 0 0x40>;
665 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
673 #size-cells = <0>;
676 reg = <0 0xe66e0000 0 0x40>;
681 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
689 #size-cells = <0>;
692 reg = <0 0xe66e8000 0 0x40>;
697 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
705 #size-cells = <0>;
709 reg = <0 0xe60b0000 0 0x425>;
714 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
723 reg = <0 0xe6540000 0 0x60>;
729 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
730 <&dmac2 0x31>, <&dmac2 0x30>;
741 reg = <0 0xe6550000 0 0x60>;
747 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
748 <&dmac2 0x33>, <&dmac2 0x32>;
759 reg = <0 0xe6560000 0 0x60>;
765 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
766 <&dmac2 0x35>, <&dmac2 0x34>;
777 reg = <0 0xe66a0000 0 0x60>;
783 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
794 reg = <0 0xe66b0000 0 0x60>;
800 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
810 reg = <0 0xe6590000 0 0x200>;
813 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
814 <&usb_dmac1 0>, <&usb_dmac1 1>;
827 reg = <0 0xe65a0000 0 0x100>;
841 reg = <0 0xe65b0000 0 0x100>;
855 reg = <0 0xe65ee000 0 0x90>;
861 #phy-cells = <0>;
868 reg = <0x0 0xe6601000 0 0x1000>;
877 reg = <0 0xe6700000 0 0x10000>;
906 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
919 reg = <0 0xe7300000 0 0x10000>;
948 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
961 reg = <0 0xe7310000 0 0x10000>;
1002 reg = <0 0xe6740000 0 0x1000>;
1003 renesas,ipmmu-main = <&ipmmu_mm 0>;
1010 reg = <0 0xe7740000 0 0x1000>;
1018 reg = <0 0xe6570000 0 0x1000>;
1026 reg = <0 0xff8b0000 0 0x1000>;
1034 reg = <0 0xe67b0000 0 0x1000>;
1043 reg = <0 0xec670000 0 0x1000>;
1051 reg = <0 0xfd800000 0 0x1000>;
1059 reg = <0 0xfd950000 0 0x1000>;
1067 reg = <0 0xffc80000 0 0x1000>;
1075 reg = <0 0xfe6b0000 0 0x1000>;
1083 reg = <0 0xfebd0000 0 0x1000>;
1092 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
1131 #size-cells = <0>;
1138 reg = <0 0xe6c30000 0 0x1000>;
1154 reg = <0 0xe6c38000 0 0x1000>;
1170 reg = <0 0xe66c0000 0 0x8000>;
1194 reg = <0 0xe6e30000 0 8>;
1204 reg = <0 0xe6e31000 0 8>;
1214 reg = <0 0xe6e32000 0 8>;
1224 reg = <0 0xe6e33000 0 8>;
1234 reg = <0 0xe6e34000 0 8>;
1244 reg = <0 0xe6e35000 0 8>;
1254 reg = <0 0xe6e36000 0 8>;
1265 reg = <0 0xe6e60000 0 64>;
1271 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1272 <&dmac2 0x51>, <&dmac2 0x50>;
1282 reg = <0 0xe6e68000 0 64>;
1288 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1289 <&dmac2 0x53>, <&dmac2 0x52>;
1299 reg = <0 0xe6e88000 0 64>;
1305 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1306 <&dmac2 0x13>, <&dmac2 0x12>;
1316 reg = <0 0xe6c50000 0 64>;
1322 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1332 reg = <0 0xe6c40000 0 64>;
1338 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1348 reg = <0 0xe6f30000 0 64>;
1354 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1355 <&dmac2 0x5b>, <&dmac2 0x5a>;
1364 reg = <0 0xe6e80000 0 0x148>;
1376 reg = <0 0xe6e90000 0 0x0064>;
1379 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1380 <&dmac2 0x41>, <&dmac2 0x40>;
1385 #size-cells = <0>;
1392 reg = <0 0xe6ea0000 0 0x0064>;
1395 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1396 <&dmac2 0x43>, <&dmac2 0x42>;
1401 #size-cells = <0>;
1408 reg = <0 0xe6c00000 0 0x0064>;
1411 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1416 #size-cells = <0>;
1423 reg = <0 0xe6c10000 0 0x0064>;
1426 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1431 #size-cells = <0>;
1437 reg = <0 0xe6ef0000 0 0x1000>;
1442 renesas,id = <0>;
1447 #size-cells = <0>;
1451 #size-cells = <0>;
1455 vin0csi20: endpoint@0 {
1456 reg = <0>;
1469 reg = <0 0xe6ef1000 0 0x1000>;
1479 #size-cells = <0>;
1483 #size-cells = <0>;
1487 vin1csi20: endpoint@0 {
1488 reg = <0>;
1501 reg = <0 0xe6ef2000 0 0x1000>;
1511 #size-cells = <0>;
1515 #size-cells = <0>;
1519 vin2csi20: endpoint@0 {
1520 reg = <0>;
1533 reg = <0 0xe6ef3000 0 0x1000>;
1543 #size-cells = <0>;
1547 #size-cells = <0>;
1551 vin3csi20: endpoint@0 {
1552 reg = <0>;
1565 reg = <0 0xe6ef4000 0 0x1000>;
1575 #size-cells = <0>;
1579 #size-cells = <0>;
1583 vin4csi20: endpoint@0 {
1584 reg = <0>;
1597 reg = <0 0xe6ef5000 0 0x1000>;
1607 #size-cells = <0>;
1611 #size-cells = <0>;
1615 vin5csi20: endpoint@0 {
1616 reg = <0>;
1629 reg = <0 0xe6ef6000 0 0x1000>;
1639 #size-cells = <0>;
1643 #size-cells = <0>;
1647 vin6csi20: endpoint@0 {
1648 reg = <0>;
1661 reg = <0 0xe6ef7000 0 0x1000>;
1671 #size-cells = <0>;
1675 #size-cells = <0>;
1679 vin7csi20: endpoint@0 {
1680 reg = <0>;
1694 reg = <0 0xe6f40000 0 0x64>;
1698 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
1709 reg = <0 0xe6f50000 0 0x64>;
1713 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
1724 reg = <0 0xe6f60000 0 0x64>;
1728 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
1739 reg = <0 0xe6f70000 0 0x64>;
1743 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
1754 reg = <0 0xe6f80000 0 0x64>;
1758 dmas = <&dmac1 0x28>, <&dmac2 0x28>;
1769 reg = <0 0xe6f90000 0 0x64>;
1773 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
1784 reg = <0 0xe6fa0000 0 0x64>;
1788 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
1799 reg = <0 0xe6fb0000 0 0x64>;
1803 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
1815 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1821 * clkout : #clock-cells = <0>; <&rcar_sound>;
1825 reg = <0 0xec500000 0 0x1000>, /* SCU */
1826 <0 0xec5a0000 0 0x100>, /* ADG */
1827 <0 0xec540000 0 0x1000>, /* SSIU */
1828 <0 0xec541000 0 0x280>, /* SSI */
1829 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1852 "ssi.1", "ssi.0",
1855 "src.1", "src.0",
1856 "mix.1", "mix.0",
1857 "ctu.1", "ctu.0",
1858 "dvc.0", "dvc.1",
1870 "ssi.1", "ssi.0";
1874 ctu00: ctu-0 { };
1885 dvc0: dvc-0 {
1886 dmas = <&audma1 0xbc>;
1890 dmas = <&audma1 0xbe>;
1896 mix0: mix-0 { };
1901 src0: src-0 {
1903 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1908 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1913 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1918 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1923 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1928 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1933 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1938 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1943 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1948 dmas = <&audma0 0x97>, <&audma1 0xba>;
1954 ssi0: ssi-0 {
1956 dmas = <&audma0 0x01>, <&audma1 0x02>;
1961 dmas = <&audma0 0x03>, <&audma1 0x04>;
1966 dmas = <&audma0 0x05>, <&audma1 0x06>;
1971 dmas = <&audma0 0x07>, <&audma1 0x08>;
1976 dmas = <&audma0 0x09>, <&audma1 0x0a>;
1981 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
1986 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
1991 dmas = <&audma0 0x0f>, <&audma1 0x10>;
1996 dmas = <&audma0 0x11>, <&audma1 0x12>;
2001 dmas = <&audma0 0x13>, <&audma1 0x14>;
2007 ssiu00: ssiu-0 {
2008 dmas = <&audma0 0x15>, <&audma1 0x16>;
2012 dmas = <&audma0 0x35>, <&audma1 0x36>;
2016 dmas = <&audma0 0x37>, <&audma1 0x38>;
2020 dmas = <&audma0 0x47>, <&audma1 0x48>;
2024 dmas = <&audma0 0x3F>, <&audma1 0x40>;
2028 dmas = <&audma0 0x43>, <&audma1 0x44>;
2032 dmas = <&audma0 0x4F>, <&audma1 0x50>;
2036 dmas = <&audma0 0x53>, <&audma1 0x54>;
2040 dmas = <&audma0 0x49>, <&audma1 0x4a>;
2044 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
2048 dmas = <&audma0 0x57>, <&audma1 0x58>;
2052 dmas = <&audma0 0x59>, <&audma1 0x5A>;
2056 dmas = <&audma0 0x5F>, <&audma1 0x60>;
2060 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
2064 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
2068 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
2072 dmas = <&audma0 0x63>, <&audma1 0x64>;
2076 dmas = <&audma0 0x67>, <&audma1 0x68>;
2080 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
2084 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
2088 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
2092 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
2096 dmas = <&audma0 0xED>, <&audma1 0xEE>;
2100 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
2104 dmas = <&audma0 0x6f>, <&audma1 0x70>;
2108 dmas = <&audma0 0x21>, <&audma1 0x22>;
2112 dmas = <&audma0 0x23>, <&audma1 0x24>;
2116 dmas = <&audma0 0x25>, <&audma1 0x26>;
2120 dmas = <&audma0 0x27>, <&audma1 0x28>;
2124 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2128 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2132 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2136 dmas = <&audma0 0x71>, <&audma1 0x72>;
2140 dmas = <&audma0 0x17>, <&audma1 0x18>;
2144 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2148 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2152 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2156 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2160 dmas = <&audma0 0x31>, <&audma1 0x32>;
2164 dmas = <&audma0 0x33>, <&audma1 0x34>;
2168 dmas = <&audma0 0x73>, <&audma1 0x74>;
2172 dmas = <&audma0 0x75>, <&audma1 0x76>;
2176 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2180 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2184 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2188 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2192 dmas = <&audma0 0x81>, <&audma1 0x82>;
2196 dmas = <&audma0 0x83>, <&audma1 0x84>;
2200 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2204 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2208 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2212 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2221 reg = <0 0xec700000 0 0x10000>;
2250 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
2263 reg = <0 0xec720000 0 0x10000>;
2305 reg = <0 0xee000000 0 0xc00>;
2316 reg = <0 0xee020000 0 0x400>;
2326 reg = <0 0xee080000 0 0x100>;
2338 reg = <0 0xee0a0000 0 0x100>;
2350 reg = <0 0xee080100 0 0x100>;
2363 reg = <0 0xee0a0100 0 0x100>;
2377 reg = <0 0xee080200 0 0x700>;
2389 reg = <0 0xee0a0200 0 0x700>;
2400 reg = <0 0xee100000 0 0x2000>;
2413 reg = <0 0xee120000 0 0x2000>;
2426 reg = <0 0xee140000 0 0x2000>;
2439 reg = <0 0xee160000 0 0x2000>;
2452 #address-cells = <0>;
2454 reg = <0x0 0xf1010000 0 0x1000>,
2455 <0x0 0xf1020000 0 0x20000>,
2456 <0x0 0xf1040000 0 0x20000>,
2457 <0x0 0xf1060000 0 0x20000>;
2469 reg = <0 0xfe000000 0 0x80000>;
2472 bus-range = <0x00 0xff>;
2474 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2475 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2476 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2477 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2479 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2484 interrupt-map-mask = <0 0 0 0>;
2485 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2496 reg = <0 0xee800000 0 0x80000>;
2499 bus-range = <0x00 0xff>;
2501 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2502 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2503 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2504 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2506 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2511 interrupt-map-mask = <0 0 0 0>;
2512 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2523 reg = <0 0xfe860000 0 0x2000>;
2533 reg = <0 0xfe870000 0 0x2000>;
2542 reg = <0 0xfe940000 0 0x2400>;
2552 reg = <0 0xfe950000 0 0x200>;
2560 reg = <0 0xfe96f000 0 0x200>;
2568 reg = <0 0xfe9af000 0 0x200>;
2577 reg = <0 0xfea27000 0 0x200>;
2586 reg = <0 0xfea2f000 0 0x200>;
2595 reg = <0 0xfea37000 0 0x200>;
2604 reg = <0 0xfe960000 0 0x8000>;
2615 reg = <0 0xfea20000 0 0x5000>;
2626 reg = <0 0xfea28000 0 0x5000>;
2637 reg = <0 0xfea30000 0 0x5000>;
2648 reg = <0 0xfe9a0000 0 0x8000>;
2660 reg = <0 0xfea40000 0 0x1000>;
2669 reg = <0 0xfea50000 0 0x1000>;
2678 reg = <0 0xfea60000 0 0x1000>;
2686 reg = <0 0xfea80000 0 0x10000>;
2695 #size-cells = <0>;
2699 #size-cells = <0>;
2703 csi20vin0: endpoint@0 {
2704 reg = <0>;
2741 reg = <0 0xfeaa0000 0 0x10000>;
2750 #size-cells = <0>;
2754 #size-cells = <0>;
2758 csi40vin0: endpoint@0 {
2759 reg = <0>;
2797 reg = <0 0xfead0000 0 0x10000>;
2807 #size-cells = <0>;
2808 port@0 {
2809 reg = <0>;
2826 reg = <0 0xfeb00000 0 0x70000>;
2832 clock-names = "du.0", "du.1", "du.2";
2834 reset-names = "du.0", "du.2";
2837 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
2843 #size-cells = <0>;
2845 port@0 {
2846 reg = <0>;
2867 reg = <0 0xfeb90000 0 0x14>;
2875 #size-cells = <0>;
2877 port@0 {
2878 reg = <0>;
2893 reg = <0 0xfff00044 0 4>;
2901 thermal-sensors = <&tsc 0>;
2942 cooling-device = <&a53_0 0 2>;
2973 #clock-cells = <0>;
2974 clock-frequency = <0>;
2979 #clock-cells = <0>;
2980 clock-frequency = <0>;