Lines Matching +full:0 +full:xfe920000
31 * The external audio clocks are configured as 0 Hz fixed frequency
37 #clock-cells = <0>;
38 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
49 #clock-cells = <0>;
50 clock-frequency = <0>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
117 #size-cells = <0>;
151 a57_0: cpu@0 {
153 reg = <0x0>;
168 reg = <0x1>;
182 reg = <0x2>;
196 reg = <0x3>;
210 reg = <0x100>;
225 reg = <0x101>;
238 reg = <0x102>;
251 reg = <0x103>;
262 L2_CA57: cache-controller-0 {
279 CPU_SLEEP_0: cpu-sleep-0 {
281 arm,psci-suspend-param = <0x0010000>;
290 arm,psci-suspend-param = <0x0010000>;
301 #clock-cells = <0>;
303 clock-frequency = <0>;
308 #clock-cells = <0>;
310 clock-frequency = <0>;
316 #clock-cells = <0>;
317 clock-frequency = <0>;
352 #clock-cells = <0>;
353 clock-frequency = <0>;
366 reg = <0 0xe6020000 0 0x0c>;
376 reg = <0 0xe6050000 0 0x50>;
380 gpio-ranges = <&pfc 0 0 16>;
391 reg = <0 0xe6051000 0 0x50>;
395 gpio-ranges = <&pfc 0 32 29>;
406 reg = <0 0xe6052000 0 0x50>;
410 gpio-ranges = <&pfc 0 64 15>;
421 reg = <0 0xe6053000 0 0x50>;
425 gpio-ranges = <&pfc 0 96 16>;
436 reg = <0 0xe6054000 0 0x50>;
440 gpio-ranges = <&pfc 0 128 18>;
451 reg = <0 0xe6055000 0 0x50>;
455 gpio-ranges = <&pfc 0 160 26>;
466 reg = <0 0xe6055400 0 0x50>;
470 gpio-ranges = <&pfc 0 192 32>;
481 reg = <0 0xe6055800 0 0x50>;
485 gpio-ranges = <&pfc 0 224 4>;
495 reg = <0 0xe6060000 0 0x50c>;
501 reg = <0 0xe60f0000 0 0x1004>;
514 reg = <0 0xe6130000 0 0x1004>;
533 reg = <0 0xe6140000 0 0x1004>;
552 reg = <0 0xe6148000 0 0x1004>;
570 reg = <0 0xe6150000 0 0x1000>;
574 #power-domain-cells = <0>;
580 reg = <0 0xe6160000 0 0x0200>;
585 reg = <0 0xe6180000 0 0x0400>;
591 reg = <0 0xe6198000 0 0x100>,
592 <0 0xe61a0000 0 0x100>,
593 <0 0xe61a8000 0 0x100>;
607 reg = <0 0xe61c0000 0 0x200>;
608 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
621 #size-cells = <0>;
624 reg = <0 0xe6500000 0 0x40>;
629 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
630 <&dmac2 0x91>, <&dmac2 0x90>;
638 #size-cells = <0>;
641 reg = <0 0xe6508000 0 0x40>;
646 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
647 <&dmac2 0x93>, <&dmac2 0x92>;
655 #size-cells = <0>;
658 reg = <0 0xe6510000 0 0x40>;
663 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
664 <&dmac2 0x95>, <&dmac2 0x94>;
672 #size-cells = <0>;
675 reg = <0 0xe66d0000 0 0x40>;
680 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
688 #size-cells = <0>;
691 reg = <0 0xe66d8000 0 0x40>;
696 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
704 #size-cells = <0>;
707 reg = <0 0xe66e0000 0 0x40>;
712 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
720 #size-cells = <0>;
723 reg = <0 0xe66e8000 0 0x40>;
728 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
736 #size-cells = <0>;
740 reg = <0 0xe60b0000 0 0x425>;
745 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
754 reg = <0 0xe6540000 0 96>;
760 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
761 <&dmac2 0x31>, <&dmac2 0x30>;
772 reg = <0 0xe6550000 0 96>;
778 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
779 <&dmac2 0x33>, <&dmac2 0x32>;
790 reg = <0 0xe6560000 0 96>;
796 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
797 <&dmac2 0x35>, <&dmac2 0x34>;
808 reg = <0 0xe66a0000 0 96>;
814 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
825 reg = <0 0xe66b0000 0 96>;
831 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
841 reg = <0 0xe6590000 0 0x200>;
844 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
845 <&usb_dmac1 0>, <&usb_dmac1 1>;
858 reg = <0 0xe659c000 0 0x200>;
861 dmas = <&usb_dmac2 0>, <&usb_dmac2 1>,
862 <&usb_dmac3 0>, <&usb_dmac3 1>;
875 reg = <0 0xe65a0000 0 0x100>;
889 reg = <0 0xe65b0000 0 0x100>;
903 reg = <0 0xe6460000 0 0x100>;
917 reg = <0 0xe6470000 0 0x100>;
931 reg = <0 0xe65ee000 0 0x90>;
937 #phy-cells = <0>;
944 reg = <0x0 0xe6601000 0 0x1000>;
953 reg = <0 0xe6700000 0 0x10000>;
982 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
995 reg = <0 0xe7300000 0 0x10000>;
1024 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1037 reg = <0 0xe7310000 0 0x10000>;
1078 reg = <0 0xe6740000 0 0x1000>;
1079 renesas,ipmmu-main = <&ipmmu_mm 0>;
1086 reg = <0 0xe7740000 0 0x1000>;
1094 reg = <0 0xe6570000 0 0x1000>;
1102 reg = <0 0xff8b0000 0 0x1000>;
1110 reg = <0 0xe67b0000 0 0x1000>;
1119 reg = <0 0xec670000 0 0x1000>;
1127 reg = <0 0xfd800000 0 0x1000>;
1135 reg = <0 0xfd950000 0 0x1000>;
1143 reg = <0 0xfd960000 0 0x1000>;
1151 reg = <0 0xfd970000 0 0x1000>;
1159 reg = <0 0xffc80000 0 0x1000>;
1167 reg = <0 0xfe6b0000 0 0x1000>;
1175 reg = <0 0xfe6f0000 0 0x1000>;
1183 reg = <0 0xfebd0000 0 0x1000>;
1191 reg = <0 0xfebe0000 0 0x1000>;
1199 reg = <0 0xfe990000 0 0x1000>;
1207 reg = <0 0xfe980000 0 0x1000>;
1216 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
1255 #size-cells = <0>;
1262 reg = <0 0xe6c30000 0 0x1000>;
1278 reg = <0 0xe6c38000 0 0x1000>;
1294 reg = <0 0xe66c0000 0 0x8000>;
1318 reg = <0 0xe6e30000 0 0x8>;
1328 reg = <0 0xe6e31000 0 0x8>;
1338 reg = <0 0xe6e32000 0 0x8>;
1348 reg = <0 0xe6e33000 0 0x8>;
1358 reg = <0 0xe6e34000 0 0x8>;
1368 reg = <0 0xe6e35000 0 0x8>;
1378 reg = <0 0xe6e36000 0 0x8>;
1389 reg = <0 0xe6e60000 0 64>;
1395 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1396 <&dmac2 0x51>, <&dmac2 0x50>;
1406 reg = <0 0xe6e68000 0 64>;
1412 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1413 <&dmac2 0x53>, <&dmac2 0x52>;
1423 reg = <0 0xe6e88000 0 64>;
1429 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1430 <&dmac2 0x13>, <&dmac2 0x12>;
1440 reg = <0 0xe6c50000 0 64>;
1446 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1456 reg = <0 0xe6c40000 0 64>;
1462 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1472 reg = <0 0xe6f30000 0 64>;
1478 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1479 <&dmac2 0x5b>, <&dmac2 0x5a>;
1488 reg = <0 0xe6e80000 0 0x148>;
1500 reg = <0 0xe6e90000 0 0x0064>;
1503 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1504 <&dmac2 0x41>, <&dmac2 0x40>;
1509 #size-cells = <0>;
1516 reg = <0 0xe6ea0000 0 0x0064>;
1519 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1520 <&dmac2 0x43>, <&dmac2 0x42>;
1525 #size-cells = <0>;
1532 reg = <0 0xe6c00000 0 0x0064>;
1535 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1540 #size-cells = <0>;
1547 reg = <0 0xe6c10000 0 0x0064>;
1550 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1555 #size-cells = <0>;
1561 reg = <0 0xe6ef0000 0 0x1000>;
1566 renesas,id = <0>;
1571 #size-cells = <0>;
1575 #size-cells = <0>;
1579 vin0csi20: endpoint@0 {
1580 reg = <0>;
1593 reg = <0 0xe6ef1000 0 0x1000>;
1603 #size-cells = <0>;
1607 #size-cells = <0>;
1611 vin1csi20: endpoint@0 {
1612 reg = <0>;
1625 reg = <0 0xe6ef2000 0 0x1000>;
1635 #size-cells = <0>;
1639 #size-cells = <0>;
1643 vin2csi20: endpoint@0 {
1644 reg = <0>;
1657 reg = <0 0xe6ef3000 0 0x1000>;
1667 #size-cells = <0>;
1671 #size-cells = <0>;
1675 vin3csi20: endpoint@0 {
1676 reg = <0>;
1689 reg = <0 0xe6ef4000 0 0x1000>;
1699 #size-cells = <0>;
1703 #size-cells = <0>;
1707 vin4csi20: endpoint@0 {
1708 reg = <0>;
1721 reg = <0 0xe6ef5000 0 0x1000>;
1731 #size-cells = <0>;
1735 #size-cells = <0>;
1739 vin5csi20: endpoint@0 {
1740 reg = <0>;
1753 reg = <0 0xe6ef6000 0 0x1000>;
1763 #size-cells = <0>;
1767 #size-cells = <0>;
1771 vin6csi20: endpoint@0 {
1772 reg = <0>;
1785 reg = <0 0xe6ef7000 0 0x1000>;
1795 #size-cells = <0>;
1799 #size-cells = <0>;
1803 vin7csi20: endpoint@0 {
1804 reg = <0>;
1818 reg = <0 0xe6f40000 0 0x64>;
1822 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
1833 reg = <0 0xe6f50000 0 0x64>;
1837 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
1848 reg = <0 0xe6f60000 0 0x64>;
1852 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
1863 reg = <0 0xe6f70000 0 0x64>;
1867 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
1878 reg = <0 0xe6f80000 0 0x64>;
1882 dmas = <&dmac1 0x28>, <&dmac2 0x28>;
1893 reg = <0 0xe6f90000 0 0x64>;
1897 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
1908 reg = <0 0xe6fa0000 0 0x64>;
1912 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
1923 reg = <0 0xe6fb0000 0 0x64>;
1927 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
1939 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1945 * clkout : #clock-cells = <0>; <&rcar_sound>;
1949 reg = <0 0xec500000 0 0x1000>, /* SCU */
1950 <0 0xec5a0000 0 0x100>, /* ADG */
1951 <0 0xec540000 0 0x1000>, /* SSIU */
1952 <0 0xec541000 0 0x280>, /* SSI */
1953 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1976 "ssi.1", "ssi.0",
1979 "src.1", "src.0",
1980 "mix.1", "mix.0",
1981 "ctu.1", "ctu.0",
1982 "dvc.0", "dvc.1",
1994 "ssi.1", "ssi.0";
1998 dvc0: dvc-0 {
1999 dmas = <&audma1 0xbc>;
2003 dmas = <&audma1 0xbe>;
2009 mix0: mix-0 { };
2014 ctu00: ctu-0 { };
2025 src0: src-0 {
2027 dmas = <&audma0 0x85>, <&audma1 0x9a>;
2032 dmas = <&audma0 0x87>, <&audma1 0x9c>;
2037 dmas = <&audma0 0x89>, <&audma1 0x9e>;
2042 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
2047 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
2052 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
2057 dmas = <&audma0 0x91>, <&audma1 0xb4>;
2062 dmas = <&audma0 0x93>, <&audma1 0xb6>;
2067 dmas = <&audma0 0x95>, <&audma1 0xb8>;
2072 dmas = <&audma0 0x97>, <&audma1 0xba>;
2078 ssiu00: ssiu-0 {
2079 dmas = <&audma0 0x15>, <&audma1 0x16>;
2083 dmas = <&audma0 0x35>, <&audma1 0x36>;
2087 dmas = <&audma0 0x37>, <&audma1 0x38>;
2091 dmas = <&audma0 0x47>, <&audma1 0x48>;
2095 dmas = <&audma0 0x3F>, <&audma1 0x40>;
2099 dmas = <&audma0 0x43>, <&audma1 0x44>;
2103 dmas = <&audma0 0x4F>, <&audma1 0x50>;
2107 dmas = <&audma0 0x53>, <&audma1 0x54>;
2111 dmas = <&audma0 0x49>, <&audma1 0x4a>;
2115 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
2119 dmas = <&audma0 0x57>, <&audma1 0x58>;
2123 dmas = <&audma0 0x59>, <&audma1 0x5A>;
2127 dmas = <&audma0 0x5F>, <&audma1 0x60>;
2131 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
2135 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
2139 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
2143 dmas = <&audma0 0x63>, <&audma1 0x64>;
2147 dmas = <&audma0 0x67>, <&audma1 0x68>;
2151 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
2155 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
2159 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
2163 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
2167 dmas = <&audma0 0xED>, <&audma1 0xEE>;
2171 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
2175 dmas = <&audma0 0x6f>, <&audma1 0x70>;
2179 dmas = <&audma0 0x21>, <&audma1 0x22>;
2183 dmas = <&audma0 0x23>, <&audma1 0x24>;
2187 dmas = <&audma0 0x25>, <&audma1 0x26>;
2191 dmas = <&audma0 0x27>, <&audma1 0x28>;
2195 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2199 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2203 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2207 dmas = <&audma0 0x71>, <&audma1 0x72>;
2211 dmas = <&audma0 0x17>, <&audma1 0x18>;
2215 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2219 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2223 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2227 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2231 dmas = <&audma0 0x31>, <&audma1 0x32>;
2235 dmas = <&audma0 0x33>, <&audma1 0x34>;
2239 dmas = <&audma0 0x73>, <&audma1 0x74>;
2243 dmas = <&audma0 0x75>, <&audma1 0x76>;
2247 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2251 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2255 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2259 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2263 dmas = <&audma0 0x81>, <&audma1 0x82>;
2267 dmas = <&audma0 0x83>, <&audma1 0x84>;
2271 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2275 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2279 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2283 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2289 ssi0: ssi-0 {
2291 dmas = <&audma0 0x01>, <&audma1 0x02>;
2296 dmas = <&audma0 0x03>, <&audma1 0x04>;
2301 dmas = <&audma0 0x05>, <&audma1 0x06>;
2306 dmas = <&audma0 0x07>, <&audma1 0x08>;
2311 dmas = <&audma0 0x09>, <&audma1 0x0a>;
2316 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
2321 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
2326 dmas = <&audma0 0x0f>, <&audma1 0x10>;
2331 dmas = <&audma0 0x11>, <&audma1 0x12>;
2336 dmas = <&audma0 0x13>, <&audma1 0x14>;
2345 reg = <0 0xec700000 0 0x10000>;
2374 iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>,
2387 reg = <0 0xec720000 0 0x10000>;
2428 reg = <0 0xee000000 0 0xc00>;
2439 reg = <0 0xee020000 0 0x400>;
2449 reg = <0 0xee080000 0 0x100>;
2461 reg = <0 0xee0a0000 0 0x100>;
2473 reg = <0 0xee0c0000 0 0x100>;
2485 reg = <0 0xee0e0000 0 0x100>;
2497 reg = <0 0xee080100 0 0x100>;
2510 reg = <0 0xee0a0100 0 0x100>;
2523 reg = <0 0xee0c0100 0 0x100>;
2536 reg = <0 0xee0e0100 0 0x100>;
2550 reg = <0 0xee080200 0 0x700>;
2562 reg = <0 0xee0a0200 0 0x700>;
2573 reg = <0 0xee0c0200 0 0x700>;
2584 reg = <0 0xee0e0200 0 0x700>;
2596 reg = <0 0xee100000 0 0x2000>;
2609 reg = <0 0xee120000 0 0x2000>;
2622 reg = <0 0xee140000 0 0x2000>;
2635 reg = <0 0xee160000 0 0x2000>;
2648 reg = <0 0xee300000 0 0x200000>;
2660 #address-cells = <0>;
2662 reg = <0x0 0xf1010000 0 0x1000>,
2663 <0x0 0xf1020000 0 0x20000>,
2664 <0x0 0xf1040000 0 0x20000>,
2665 <0x0 0xf1060000 0 0x20000>;
2677 reg = <0 0xfe000000 0 0x80000>;
2680 bus-range = <0x00 0xff>;
2682 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2683 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2684 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2685 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2687 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
2692 interrupt-map-mask = <0 0 0 0>;
2693 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2704 reg = <0 0xee800000 0 0x80000>;
2707 bus-range = <0x00 0xff>;
2709 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2710 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2711 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2712 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2714 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
2719 interrupt-map-mask = <0 0 0 0>;
2720 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2731 reg = <0 0xfe860000 0 0x2000>;
2741 reg = <0 0xfe870000 0 0x2000>;
2751 reg = <0 0xfe880000 0 0x2000>;
2761 reg = <0 0xfe890000 0 0x2000>;
2770 reg = <0 0xfe920000 0 0x8000>;
2781 reg = <0 0xfe960000 0 0x8000>;
2792 reg = <0 0xfea20000 0 0x5000>;
2803 reg = <0 0xfea28000 0 0x5000>;
2814 reg = <0 0xfea30000 0 0x5000>;
2825 reg = <0 0xfe9a0000 0 0x8000>;
2836 reg = <0 0xfe9b0000 0 0x8000>;
2847 reg = <0 0xfe940000 0 0x2400>;
2857 reg = <0 0xfe944000 0 0x2400>;
2867 reg = <0 0xfe950000 0 0x200>;
2871 iommus = <&ipmmu_vp0 0>;
2876 reg = <0 0xfe951000 0 0x200>;
2885 reg = <0 0xfe96f000 0 0x200>;
2894 reg = <0 0xfe92f000 0 0x200>;
2903 reg = <0 0xfe9af000 0 0x200>;
2912 reg = <0 0xfe9bf000 0 0x200>;
2921 reg = <0 0xfea27000 0 0x200>;
2930 reg = <0 0xfea2f000 0 0x200>;
2939 reg = <0 0xfea37000 0 0x200>;
2949 reg = <0 0xfea40000 0 0x1000>;
2958 reg = <0 0xfea50000 0 0x1000>;
2967 reg = <0 0xfea60000 0 0x1000>;
2976 reg = <0 0xfea70000 0 0x1000>;
2984 reg = <0 0xfea80000 0 0x10000>;
2993 #size-cells = <0>;
2997 #size-cells = <0>;
3001 csi20vin0: endpoint@0 {
3002 reg = <0>;
3039 reg = <0 0xfeaa0000 0 0x10000>;
3048 #size-cells = <0>;
3052 #size-cells = <0>;
3056 csi40vin0: endpoint@0 {
3057 reg = <0>;
3078 reg = <0 0xfeab0000 0 0x10000>;
3087 #size-cells = <0>;
3091 #size-cells = <0>;
3095 csi41vin4: endpoint@0 {
3096 reg = <0>;
3117 reg = <0 0xfead0000 0 0x10000>;
3127 #size-cells = <0>;
3128 port@0 {
3129 reg = <0>;
3146 reg = <0 0xfeae0000 0 0x10000>;
3156 #size-cells = <0>;
3157 port@0 {
3158 reg = <0>;
3175 reg = <0 0xfeb00000 0 0x80000>;
3182 clock-names = "du.0", "du.1", "du.2", "du.3";
3184 reset-names = "du.0", "du.2";
3187 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>,
3194 #size-cells = <0>;
3196 port@0 {
3197 reg = <0>;
3224 reg = <0 0xfeb90000 0 0x14>;
3232 #size-cells = <0>;
3234 port@0 {
3235 reg = <0>;
3250 reg = <0 0xfff00044 0 4>;
3258 thermal-sensors = <&tsc 0>;
3313 cooling-device = <&a53_0 0 2>;
3331 #clock-cells = <0>;
3332 clock-frequency = <0>;
3337 #clock-cells = <0>;
3338 clock-frequency = <0>;