Lines Matching +full:0 +full:xe6550000
21 * The external audio clocks are configured as 0 Hz fixed frequency
27 #clock-cells = <0>;
28 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
39 #clock-cells = <0>;
40 clock-frequency = <0>;
46 #clock-cells = <0>;
47 clock-frequency = <0>;
95 #size-cells = <0>;
129 a57_0: cpu@0 {
131 reg = <0x0>;
146 reg = <0x1>;
160 reg = <0x2>;
174 reg = <0x3>;
188 reg = <0x100>;
203 reg = <0x101>;
216 reg = <0x102>;
229 reg = <0x103>;
240 L2_CA57: cache-controller-0 {
257 CPU_SLEEP_0: cpu-sleep-0 {
259 arm,psci-suspend-param = <0x0010000>;
268 arm,psci-suspend-param = <0x0010000>;
279 #clock-cells = <0>;
281 clock-frequency = <0>;
286 #clock-cells = <0>;
288 clock-frequency = <0>;
294 #clock-cells = <0>;
295 clock-frequency = <0>;
324 #clock-cells = <0>;
325 clock-frequency = <0>;
338 reg = <0 0xe6020000 0 0x0c>;
349 reg = <0 0xe6050000 0 0x50>;
353 gpio-ranges = <&pfc 0 0 16>;
364 reg = <0 0xe6051000 0 0x50>;
368 gpio-ranges = <&pfc 0 32 29>;
379 reg = <0 0xe6052000 0 0x50>;
383 gpio-ranges = <&pfc 0 64 15>;
394 reg = <0 0xe6053000 0 0x50>;
398 gpio-ranges = <&pfc 0 96 16>;
409 reg = <0 0xe6054000 0 0x50>;
413 gpio-ranges = <&pfc 0 128 18>;
424 reg = <0 0xe6055000 0 0x50>;
428 gpio-ranges = <&pfc 0 160 26>;
439 reg = <0 0xe6055400 0 0x50>;
443 gpio-ranges = <&pfc 0 192 32>;
454 reg = <0 0xe6055800 0 0x50>;
458 gpio-ranges = <&pfc 0 224 4>;
468 reg = <0 0xe6060000 0 0x50c>;
474 reg = <0 0xe60f0000 0 0x1004>;
487 reg = <0 0xe6130000 0 0x1004>;
506 reg = <0 0xe6140000 0 0x1004>;
525 reg = <0 0xe6148000 0 0x1004>;
543 reg = <0 0xe6150000 0 0x1000>;
547 #power-domain-cells = <0>;
553 reg = <0 0xe6160000 0 0x0200>;
558 reg = <0 0xe6180000 0 0x0400>;
564 reg = <0 0xe6198000 0 0x100>,
565 <0 0xe61a0000 0 0x100>,
566 <0 0xe61a8000 0 0x100>;
580 reg = <0 0xe61c0000 0 0x200>;
581 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
594 reg = <0 0xe61e0000 0 0x30>;
607 reg = <0 0xe6fc0000 0 0x30>;
620 reg = <0 0xe6fd0000 0 0x30>;
633 reg = <0 0xe6fe0000 0 0x30>;
646 reg = <0 0xffc00000 0 0x30>;
659 #size-cells = <0>;
662 reg = <0 0xe6500000 0 0x40>;
667 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
668 <&dmac2 0x91>, <&dmac2 0x90>;
676 #size-cells = <0>;
679 reg = <0 0xe6508000 0 0x40>;
684 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
685 <&dmac2 0x93>, <&dmac2 0x92>;
693 #size-cells = <0>;
696 reg = <0 0xe6510000 0 0x40>;
701 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
702 <&dmac2 0x95>, <&dmac2 0x94>;
710 #size-cells = <0>;
713 reg = <0 0xe66d0000 0 0x40>;
718 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
726 #size-cells = <0>;
729 reg = <0 0xe66d8000 0 0x40>;
734 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
742 #size-cells = <0>;
745 reg = <0 0xe66e0000 0 0x40>;
750 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
758 #size-cells = <0>;
761 reg = <0 0xe66e8000 0 0x40>;
766 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
774 #size-cells = <0>;
778 reg = <0 0xe60b0000 0 0x425>;
783 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
792 reg = <0 0xe6540000 0 0x60>;
798 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
799 <&dmac2 0x31>, <&dmac2 0x30>;
810 reg = <0 0xe6550000 0 0x60>;
816 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
817 <&dmac2 0x33>, <&dmac2 0x32>;
828 reg = <0 0xe6560000 0 0x60>;
834 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
835 <&dmac2 0x35>, <&dmac2 0x34>;
846 reg = <0 0xe66a0000 0 0x60>;
852 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
863 reg = <0 0xe66b0000 0 0x60>;
869 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
879 reg = <0 0xe6590000 0 0x200>;
882 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
883 <&usb_dmac1 0>, <&usb_dmac1 1>;
896 reg = <0 0xe65a0000 0 0x100>;
910 reg = <0 0xe65b0000 0 0x100>;
924 reg = <0 0xe65ee000 0 0x90>;
930 #phy-cells = <0>;
937 reg = <0 0xe6700000 0 0x10000>;
966 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
979 reg = <0 0xe7300000 0 0x10000>;
1008 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1021 reg = <0 0xe7310000 0 0x10000>;
1062 reg = <0 0xe6740000 0 0x1000>;
1063 renesas,ipmmu-main = <&ipmmu_mm 0>;
1070 reg = <0 0xe7740000 0 0x1000>;
1078 reg = <0 0xe6570000 0 0x1000>;
1086 reg = <0 0xe67b0000 0 0x1000>;
1095 reg = <0 0xec670000 0 0x1000>;
1103 reg = <0 0xfd800000 0 0x1000>;
1111 reg = <0 0xfd950000 0 0x1000>;
1119 reg = <0 0xfd960000 0 0x1000>;
1127 reg = <0 0xfd970000 0 0x1000>;
1135 reg = <0 0xfe6b0000 0 0x1000>;
1143 reg = <0 0xfe6f0000 0 0x1000>;
1151 reg = <0 0xfebd0000 0 0x1000>;
1159 reg = <0 0xfebe0000 0 0x1000>;
1167 reg = <0 0xfe990000 0 0x1000>;
1175 reg = <0 0xfe980000 0 0x1000>;
1184 reg = <0 0xe6800000 0 0x800>;
1223 #size-cells = <0>;
1230 reg = <0 0xe6c30000 0 0x1000>;
1246 reg = <0 0xe6c38000 0 0x1000>;
1262 reg = <0 0xe66c0000 0 0x8000>;
1286 reg = <0 0xe6e30000 0 0x8>;
1296 reg = <0 0xe6e31000 0 0x8>;
1306 reg = <0 0xe6e32000 0 0x8>;
1316 reg = <0 0xe6e33000 0 0x8>;
1326 reg = <0 0xe6e34000 0 0x8>;
1336 reg = <0 0xe6e35000 0 0x8>;
1346 reg = <0 0xe6e36000 0 0x8>;
1357 reg = <0 0xe6e60000 0 0x40>;
1363 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1364 <&dmac2 0x51>, <&dmac2 0x50>;
1374 reg = <0 0xe6e68000 0 0x40>;
1380 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1381 <&dmac2 0x53>, <&dmac2 0x52>;
1391 reg = <0 0xe6e88000 0 0x40>;
1397 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1398 <&dmac2 0x13>, <&dmac2 0x12>;
1408 reg = <0 0xe6c50000 0 0x40>;
1414 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1424 reg = <0 0xe6c40000 0 0x40>;
1430 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1440 reg = <0 0xe6f30000 0 0x40>;
1446 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1447 <&dmac2 0x5b>, <&dmac2 0x5a>;
1457 reg = <0 0xe6e90000 0 0x0064>;
1460 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1461 <&dmac2 0x41>, <&dmac2 0x40>;
1466 #size-cells = <0>;
1473 reg = <0 0xe6ea0000 0 0x0064>;
1476 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1477 <&dmac2 0x43>, <&dmac2 0x42>;
1482 #size-cells = <0>;
1489 reg = <0 0xe6c00000 0 0x0064>;
1492 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1497 #size-cells = <0>;
1504 reg = <0 0xe6c10000 0 0x0064>;
1507 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1512 #size-cells = <0>;
1518 reg = <0 0xe6ef0000 0 0x1000>;
1523 renesas,id = <0>;
1528 #size-cells = <0>;
1532 #size-cells = <0>;
1536 vin0csi20: endpoint@0 {
1537 reg = <0>;
1550 reg = <0 0xe6ef1000 0 0x1000>;
1560 #size-cells = <0>;
1564 #size-cells = <0>;
1568 vin1csi20: endpoint@0 {
1569 reg = <0>;
1582 reg = <0 0xe6ef2000 0 0x1000>;
1592 #size-cells = <0>;
1596 #size-cells = <0>;
1600 vin2csi20: endpoint@0 {
1601 reg = <0>;
1614 reg = <0 0xe6ef3000 0 0x1000>;
1624 #size-cells = <0>;
1628 #size-cells = <0>;
1632 vin3csi20: endpoint@0 {
1633 reg = <0>;
1646 reg = <0 0xe6ef4000 0 0x1000>;
1656 #size-cells = <0>;
1660 #size-cells = <0>;
1664 vin4csi20: endpoint@0 {
1665 reg = <0>;
1674 reg = <0 0xe6ef5000 0 0x1000>;
1684 #size-cells = <0>;
1688 #size-cells = <0>;
1692 vin5csi20: endpoint@0 {
1693 reg = <0>;
1702 reg = <0 0xe6ef6000 0 0x1000>;
1712 #size-cells = <0>;
1716 #size-cells = <0>;
1720 vin6csi20: endpoint@0 {
1721 reg = <0>;
1730 reg = <0 0xe6ef7000 0 0x1000>;
1740 #size-cells = <0>;
1744 #size-cells = <0>;
1748 vin7csi20: endpoint@0 {
1749 reg = <0>;
1760 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1766 * clkout : #clock-cells = <0>; <&rcar_sound>;
1770 reg = <0 0xec500000 0 0x1000>, /* SCU */
1771 <0 0xec5a0000 0 0x100>, /* ADG */
1772 <0 0xec540000 0 0x1000>, /* SSIU */
1773 <0 0xec541000 0 0x280>, /* SSI */
1774 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1797 "ssi.1", "ssi.0",
1800 "src.1", "src.0",
1801 "mix.1", "mix.0",
1802 "ctu.1", "ctu.0",
1803 "dvc.0", "dvc.1",
1815 "ssi.1", "ssi.0";
1819 dvc0: dvc-0 {
1820 dmas = <&audma1 0xbc>;
1824 dmas = <&audma1 0xbe>;
1830 mix0: mix-0 { };
1835 ctu00: ctu-0 { };
1846 src0: src-0 {
1848 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1853 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1858 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1863 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1868 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1873 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1878 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1883 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1888 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1893 dmas = <&audma0 0x97>, <&audma1 0xba>;
1899 ssiu00: ssiu-0 {
1900 dmas = <&audma0 0x15>, <&audma1 0x16>;
1904 dmas = <&audma0 0x35>, <&audma1 0x36>;
1908 dmas = <&audma0 0x37>, <&audma1 0x38>;
1912 dmas = <&audma0 0x47>, <&audma1 0x48>;
1916 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1920 dmas = <&audma0 0x43>, <&audma1 0x44>;
1924 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1928 dmas = <&audma0 0x53>, <&audma1 0x54>;
1932 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1936 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1940 dmas = <&audma0 0x57>, <&audma1 0x58>;
1944 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1948 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1952 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1956 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1960 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1964 dmas = <&audma0 0x63>, <&audma1 0x64>;
1968 dmas = <&audma0 0x67>, <&audma1 0x68>;
1972 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
1976 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
1980 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
1984 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
1988 dmas = <&audma0 0xED>, <&audma1 0xEE>;
1992 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
1996 dmas = <&audma0 0x6f>, <&audma1 0x70>;
2000 dmas = <&audma0 0x21>, <&audma1 0x22>;
2004 dmas = <&audma0 0x23>, <&audma1 0x24>;
2008 dmas = <&audma0 0x25>, <&audma1 0x26>;
2012 dmas = <&audma0 0x27>, <&audma1 0x28>;
2016 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2020 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2024 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2028 dmas = <&audma0 0x71>, <&audma1 0x72>;
2032 dmas = <&audma0 0x17>, <&audma1 0x18>;
2036 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2040 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2044 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2048 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2052 dmas = <&audma0 0x31>, <&audma1 0x32>;
2056 dmas = <&audma0 0x33>, <&audma1 0x34>;
2060 dmas = <&audma0 0x73>, <&audma1 0x74>;
2064 dmas = <&audma0 0x75>, <&audma1 0x76>;
2068 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2072 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2076 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2080 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2084 dmas = <&audma0 0x81>, <&audma1 0x82>;
2088 dmas = <&audma0 0x83>, <&audma1 0x84>;
2092 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2096 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2100 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2104 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2110 ssi0: ssi-0 {
2112 dmas = <&audma0 0x01>, <&audma1 0x02>;
2117 dmas = <&audma0 0x03>, <&audma1 0x04>;
2122 dmas = <&audma0 0x05>, <&audma1 0x06>;
2127 dmas = <&audma0 0x07>, <&audma1 0x08>;
2132 dmas = <&audma0 0x09>, <&audma1 0x0a>;
2137 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
2142 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
2147 dmas = <&audma0 0x0f>, <&audma1 0x10>;
2152 dmas = <&audma0 0x11>, <&audma1 0x12>;
2157 dmas = <&audma0 0x13>, <&audma1 0x14>;
2166 reg = <0 0xec700000 0 0x10000>;
2195 iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>,
2208 reg = <0 0xec720000 0 0x10000>;
2250 reg = <0 0xee000000 0 0xc00>;
2261 reg = <0 0xee020000 0 0x400>;
2271 reg = <0 0xee080000 0 0x100>;
2283 reg = <0 0xee0a0000 0 0x100>;
2295 reg = <0 0xee080100 0 0x100>;
2308 reg = <0 0xee0a0100 0 0x100>;
2322 reg = <0 0xee080200 0 0x700>;
2334 reg = <0 0xee0a0200 0 0x700>;
2345 reg = <0 0xee100000 0 0x2000>;
2358 reg = <0 0xee120000 0 0x2000>;
2371 reg = <0 0xee140000 0 0x2000>;
2384 reg = <0 0xee160000 0 0x2000>;
2397 reg = <0 0xee300000 0 0x200000>;
2409 #address-cells = <0>;
2411 reg = <0x0 0xf1010000 0 0x1000>,
2412 <0x0 0xf1020000 0 0x20000>,
2413 <0x0 0xf1040000 0 0x20000>,
2414 <0x0 0xf1060000 0 0x20000>;
2426 reg = <0 0xfe000000 0 0x80000>;
2429 bus-range = <0x00 0xff>;
2431 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2432 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2433 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2434 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2436 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2441 interrupt-map-mask = <0 0 0 0>;
2442 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2453 reg = <0 0xee800000 0 0x80000>;
2456 bus-range = <0x00 0xff>;
2458 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2459 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2460 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2461 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2463 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2468 interrupt-map-mask = <0 0 0 0>;
2469 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2480 reg = <0x0 0xfe000000 0 0x80000>,
2481 <0x0 0xfe100000 0 0x100000>,
2482 <0x0 0xfe200000 0 0x200000>,
2483 <0x0 0x30000000 0 0x8000000>,
2484 <0x0 0x38000000 0 0x8000000>;
2499 reg = <0x0 0xee800000 0 0x80000>,
2500 <0x0 0xee900000 0 0x100000>,
2501 <0x0 0xeea00000 0 0x200000>,
2502 <0x0 0xc0000000 0 0x8000000>,
2503 <0x0 0xc8000000 0 0x8000000>;
2517 reg = <0 0xfe920000 0 0x8000>;
2528 reg = <0 0xfe960000 0 0x8000>;
2539 reg = <0 0xfea20000 0 0x5000>;
2550 reg = <0 0xfea28000 0 0x5000>;
2561 reg = <0 0xfe9a0000 0 0x8000>;
2572 reg = <0 0xfe9b0000 0 0x8000>;
2583 reg = <0 0xfe940000 0 0x2400>;
2593 reg = <0 0xfe944000 0 0x2400>;
2603 reg = <0 0xfe950000 0 0x200>;
2611 reg = <0 0xfe951000 0 0x200>;
2619 reg = <0 0xfe96f000 0 0x200>;
2627 reg = <0 0xfe92f000 0 0x200>;
2635 reg = <0 0xfe9af000 0 0x200>;
2643 reg = <0 0xfe9bf000 0 0x200>;
2651 reg = <0 0xfea27000 0 0x200>;
2659 reg = <0 0xfea2f000 0 0x200>;
2667 reg = <0 0xfea80000 0 0x10000>;
2676 #size-cells = <0>;
2680 #size-cells = <0>;
2684 csi20vin0: endpoint@0 {
2685 reg = <0>;
2722 reg = <0 0xfeaa0000 0 0x10000>;
2731 #size-cells = <0>;
2735 #size-cells = <0>;
2739 csi40vin0: endpoint@0 {
2740 reg = <0>;
2762 reg = <0 0xfead0000 0 0x10000>;
2773 #size-cells = <0>;
2775 port@0 {
2776 reg = <0>;
2793 reg = <0 0xfeb00000 0 0x80000>;
2800 clock-names = "du.0", "du.1", "du.3";
2802 reset-names = "du.0", "du.3";
2805 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
2809 #size-cells = <0>;
2811 port@0 {
2812 reg = <0>;
2833 reg = <0 0xfeb90000 0 0x14>;
2841 #size-cells = <0>;
2843 port@0 {
2844 reg = <0>;
2859 reg = <0 0xfff00044 0 4>;
2867 thermal-sensors = <&tsc 0>;
2917 cooling-device = <&a57_0 0 2>;
2923 cooling-device = <&a53_0 0 2>;
2941 #clock-cells = <0>;
2942 clock-frequency = <0>;
2947 #clock-cells = <0>;
2948 clock-frequency = <0>;