Lines Matching +full:0 +full:xe6198000
21 * The external audio clocks are configured as 0 Hz fixed frequency
27 #clock-cells = <0>;
28 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
39 #clock-cells = <0>;
40 clock-frequency = <0>;
46 #clock-cells = <0>;
47 clock-frequency = <0>;
74 #size-cells = <0>;
76 a57_0: cpu@0 {
78 reg = <0x0>;
91 reg = <0x1>;
100 L2_CA57: cache-controller-0 {
110 #clock-cells = <0>;
112 clock-frequency = <0>;
117 #clock-cells = <0>;
119 clock-frequency = <0>;
125 #clock-cells = <0>;
126 clock-frequency = <0>;
144 #clock-cells = <0>;
145 clock-frequency = <0>;
158 reg = <0 0xe6020000 0 0x0c>;
168 reg = <0 0xe6050000 0 0x50>;
172 gpio-ranges = <&pfc 0 0 16>;
183 reg = <0 0xe6051000 0 0x50>;
187 gpio-ranges = <&pfc 0 32 29>;
198 reg = <0 0xe6052000 0 0x50>;
202 gpio-ranges = <&pfc 0 64 15>;
213 reg = <0 0xe6053000 0 0x50>;
217 gpio-ranges = <&pfc 0 96 16>;
228 reg = <0 0xe6054000 0 0x50>;
232 gpio-ranges = <&pfc 0 128 18>;
243 reg = <0 0xe6055000 0 0x50>;
247 gpio-ranges = <&pfc 0 160 26>;
258 reg = <0 0xe6055400 0 0x50>;
262 gpio-ranges = <&pfc 0 192 32>;
273 reg = <0 0xe6055800 0 0x50>;
277 gpio-ranges = <&pfc 0 224 4>;
287 reg = <0 0xe6060000 0 0x50c>;
293 reg = <0 0xe60f0000 0 0x1004>;
306 reg = <0 0xe6130000 0 0x1004>;
325 reg = <0 0xe6140000 0 0x1004>;
344 reg = <0 0xe6148000 0 0x1004>;
362 reg = <0 0xe6150000 0 0x1000>;
366 #power-domain-cells = <0>;
372 reg = <0 0xe6160000 0 0x0200>;
377 reg = <0 0xe6180000 0 0x0400>;
383 reg = <0 0xe6198000 0 0x100>,
384 <0 0xe61a0000 0 0x100>,
385 <0 0xe61a8000 0 0x100>;
399 reg = <0 0xe61c0000 0 0x200>;
400 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
413 reg = <0 0xe61e0000 0 0x30>;
426 reg = <0 0xe6fc0000 0 0x30>;
439 reg = <0 0xe6fd0000 0 0x30>;
452 reg = <0 0xe6fe0000 0 0x30>;
465 reg = <0 0xffc00000 0 0x30>;
478 #size-cells = <0>;
481 reg = <0 0xe6500000 0 0x40>;
486 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
487 <&dmac2 0x91>, <&dmac2 0x90>;
495 #size-cells = <0>;
498 reg = <0 0xe6508000 0 0x40>;
503 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
504 <&dmac2 0x93>, <&dmac2 0x92>;
512 #size-cells = <0>;
515 reg = <0 0xe6510000 0 0x40>;
520 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
521 <&dmac2 0x95>, <&dmac2 0x94>;
529 #size-cells = <0>;
532 reg = <0 0xe66d0000 0 0x40>;
537 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
545 #size-cells = <0>;
548 reg = <0 0xe66d8000 0 0x40>;
553 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
561 #size-cells = <0>;
564 reg = <0 0xe66e0000 0 0x40>;
569 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
577 #size-cells = <0>;
580 reg = <0 0xe66e8000 0 0x40>;
585 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
593 #size-cells = <0>;
597 reg = <0 0xe60b0000 0 0x425>;
602 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
611 reg = <0 0xe6540000 0 0x60>;
617 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
618 <&dmac2 0x31>, <&dmac2 0x30>;
629 reg = <0 0xe6550000 0 0x60>;
635 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
636 <&dmac2 0x33>, <&dmac2 0x32>;
647 reg = <0 0xe6560000 0 0x60>;
653 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
654 <&dmac2 0x35>, <&dmac2 0x34>;
665 reg = <0 0xe66a0000 0 0x60>;
671 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
682 reg = <0 0xe66b0000 0 0x60>;
688 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
698 reg = <0 0xe6590000 0 0x200>;
701 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
702 <&usb_dmac1 0>, <&usb_dmac1 1>;
715 reg = <0 0xe65a0000 0 0x100>;
729 reg = <0 0xe65b0000 0 0x100>;
743 reg = <0 0xe65ee000 0 0x90>;
749 #phy-cells = <0>;
756 reg = <0 0xe6700000 0 0x10000>;
785 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
798 reg = <0 0xe7300000 0 0x10000>;
827 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
840 reg = <0 0xe7310000 0 0x10000>;
881 reg = <0 0xe6740000 0 0x1000>;
882 renesas,ipmmu-main = <&ipmmu_mm 0>;
889 reg = <0 0xe7740000 0 0x1000>;
897 reg = <0 0xe6570000 0 0x1000>;
905 reg = <0 0xe67b0000 0 0x1000>;
914 reg = <0 0xec670000 0 0x1000>;
922 reg = <0 0xfd800000 0 0x1000>;
930 reg = <0 0xfe6b0000 0 0x1000>;
938 reg = <0 0xfebd0000 0 0x1000>;
946 reg = <0 0xfe990000 0 0x1000>;
955 reg = <0 0xe6800000 0 0x800>;
994 #size-cells = <0>;
1001 reg = <0 0xe6c30000 0 0x1000>;
1017 reg = <0 0xe6c38000 0 0x1000>;
1033 reg = <0 0xe66c0000 0 0x8000>;
1057 reg = <0 0xe6e30000 0 0x8>;
1067 reg = <0 0xe6e31000 0 0x8>;
1077 reg = <0 0xe6e32000 0 0x8>;
1087 reg = <0 0xe6e33000 0 0x8>;
1097 reg = <0 0xe6e34000 0 0x8>;
1107 reg = <0 0xe6e35000 0 0x8>;
1117 reg = <0 0xe6e36000 0 0x8>;
1128 reg = <0 0xe6e60000 0 0x40>;
1134 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1135 <&dmac2 0x51>, <&dmac2 0x50>;
1145 reg = <0 0xe6e68000 0 0x40>;
1151 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1152 <&dmac2 0x53>, <&dmac2 0x52>;
1162 reg = <0 0xe6e88000 0 0x40>;
1168 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1169 <&dmac2 0x13>, <&dmac2 0x12>;
1179 reg = <0 0xe6c50000 0 0x40>;
1185 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1195 reg = <0 0xe6c40000 0 0x40>;
1201 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1211 reg = <0 0xe6f30000 0 0x40>;
1217 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1218 <&dmac2 0x5b>, <&dmac2 0x5a>;
1228 reg = <0 0xe6e90000 0 0x0064>;
1231 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1232 <&dmac2 0x41>, <&dmac2 0x40>;
1237 #size-cells = <0>;
1244 reg = <0 0xe6ea0000 0 0x0064>;
1247 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1248 <&dmac2 0x43>, <&dmac2 0x42>;
1253 #size-cells = <0>;
1260 reg = <0 0xe6c00000 0 0x0064>;
1263 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1268 #size-cells = <0>;
1275 reg = <0 0xe6c10000 0 0x0064>;
1278 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1283 #size-cells = <0>;
1289 reg = <0 0xe6ef0000 0 0x1000>;
1294 renesas,id = <0>;
1299 #size-cells = <0>;
1303 #size-cells = <0>;
1307 vin0csi20: endpoint@0 {
1308 reg = <0>;
1321 reg = <0 0xe6ef1000 0 0x1000>;
1331 #size-cells = <0>;
1335 #size-cells = <0>;
1339 vin1csi20: endpoint@0 {
1340 reg = <0>;
1353 reg = <0 0xe6ef2000 0 0x1000>;
1363 #size-cells = <0>;
1367 #size-cells = <0>;
1371 vin2csi20: endpoint@0 {
1372 reg = <0>;
1385 reg = <0 0xe6ef3000 0 0x1000>;
1395 #size-cells = <0>;
1399 #size-cells = <0>;
1403 vin3csi20: endpoint@0 {
1404 reg = <0>;
1417 reg = <0 0xe6ef4000 0 0x1000>;
1427 #size-cells = <0>;
1431 #size-cells = <0>;
1435 vin4csi20: endpoint@0 {
1436 reg = <0>;
1449 reg = <0 0xe6ef5000 0 0x1000>;
1459 #size-cells = <0>;
1463 #size-cells = <0>;
1467 vin5csi20: endpoint@0 {
1468 reg = <0>;
1481 reg = <0 0xe6ef6000 0 0x1000>;
1491 #size-cells = <0>;
1495 #size-cells = <0>;
1499 vin6csi20: endpoint@0 {
1500 reg = <0>;
1513 reg = <0 0xe6ef7000 0 0x1000>;
1523 #size-cells = <0>;
1527 #size-cells = <0>;
1531 vin7csi20: endpoint@0 {
1532 reg = <0>;
1547 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1553 * clkout : #clock-cells = <0>; <&rcar_sound>;
1557 reg = <0 0xec500000 0 0x1000>, /* SCU */
1558 <0 0xec5a0000 0 0x100>, /* ADG */
1559 <0 0xec540000 0 0x1000>, /* SSIU */
1560 <0 0xec541000 0 0x280>, /* SSI */
1561 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1584 "ssi.1", "ssi.0",
1587 "src.1", "src.0",
1588 "mix.1", "mix.0",
1589 "ctu.1", "ctu.0",
1590 "dvc.0", "dvc.1",
1602 "ssi.1", "ssi.0";
1606 ctu00: ctu-0 { };
1617 dvc0: dvc-0 {
1618 dmas = <&audma1 0xbc>;
1622 dmas = <&audma1 0xbe>;
1628 mix0: mix-0 { };
1633 src0: src-0 {
1635 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1640 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1645 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1650 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1655 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1660 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1665 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1670 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1675 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1680 dmas = <&audma0 0x97>, <&audma1 0xba>;
1686 ssi0: ssi-0 {
1688 dmas = <&audma0 0x01>, <&audma1 0x02>;
1693 dmas = <&audma0 0x03>, <&audma1 0x04>;
1698 dmas = <&audma0 0x05>, <&audma1 0x06>;
1703 dmas = <&audma0 0x07>, <&audma1 0x08>;
1708 dmas = <&audma0 0x09>, <&audma1 0x0a>;
1713 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
1718 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
1723 dmas = <&audma0 0x0f>, <&audma1 0x10>;
1728 dmas = <&audma0 0x11>, <&audma1 0x12>;
1733 dmas = <&audma0 0x13>, <&audma1 0x14>;
1739 ssiu00: ssiu-0 {
1740 dmas = <&audma0 0x15>, <&audma1 0x16>;
1744 dmas = <&audma0 0x35>, <&audma1 0x36>;
1748 dmas = <&audma0 0x37>, <&audma1 0x38>;
1752 dmas = <&audma0 0x47>, <&audma1 0x48>;
1756 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1760 dmas = <&audma0 0x43>, <&audma1 0x44>;
1764 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1768 dmas = <&audma0 0x53>, <&audma1 0x54>;
1772 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1776 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1780 dmas = <&audma0 0x57>, <&audma1 0x58>;
1784 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1788 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1792 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1796 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1800 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1804 dmas = <&audma0 0x63>, <&audma1 0x64>;
1808 dmas = <&audma0 0x67>, <&audma1 0x68>;
1812 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
1816 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
1820 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
1824 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
1828 dmas = <&audma0 0xED>, <&audma1 0xEE>;
1832 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
1836 dmas = <&audma0 0x6f>, <&audma1 0x70>;
1840 dmas = <&audma0 0x21>, <&audma1 0x22>;
1844 dmas = <&audma0 0x23>, <&audma1 0x24>;
1848 dmas = <&audma0 0x25>, <&audma1 0x26>;
1852 dmas = <&audma0 0x27>, <&audma1 0x28>;
1856 dmas = <&audma0 0x29>, <&audma1 0x2A>;
1860 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
1864 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
1868 dmas = <&audma0 0x71>, <&audma1 0x72>;
1872 dmas = <&audma0 0x17>, <&audma1 0x18>;
1876 dmas = <&audma0 0x19>, <&audma1 0x1A>;
1880 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
1884 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
1888 dmas = <&audma0 0x1F>, <&audma1 0x20>;
1892 dmas = <&audma0 0x31>, <&audma1 0x32>;
1896 dmas = <&audma0 0x33>, <&audma1 0x34>;
1900 dmas = <&audma0 0x73>, <&audma1 0x74>;
1904 dmas = <&audma0 0x75>, <&audma1 0x76>;
1908 dmas = <&audma0 0x79>, <&audma1 0x7a>;
1912 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
1916 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
1920 dmas = <&audma0 0x7F>, <&audma1 0x80>;
1924 dmas = <&audma0 0x81>, <&audma1 0x82>;
1928 dmas = <&audma0 0x83>, <&audma1 0x84>;
1932 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
1936 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
1940 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
1944 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
1953 reg = <0 0xec700000 0 0x10000>;
1987 reg = <0 0xec720000 0 0x10000>;
2021 reg = <0 0xee000000 0 0xc00>;
2032 reg = <0 0xee020000 0 0x400>;
2042 reg = <0 0xee080000 0 0x100>;
2054 reg = <0 0xee0a0000 0 0x100>;
2066 reg = <0 0xee080100 0 0x100>;
2079 reg = <0 0xee0a0100 0 0x100>;
2093 reg = <0 0xee080200 0 0x700>;
2105 reg = <0 0xee0a0200 0 0x700>;
2116 reg = <0 0xee100000 0 0x2000>;
2128 reg = <0 0xee120000 0 0x2000>;
2140 reg = <0 0xee140000 0 0x2000>;
2152 reg = <0 0xee160000 0 0x2000>;
2164 reg = <0 0xee300000 0 0x200000>;
2175 #address-cells = <0>;
2177 reg = <0x0 0xf1010000 0 0x1000>,
2178 <0x0 0xf1020000 0 0x20000>,
2179 <0x0 0xf1040000 0 0x20000>,
2180 <0x0 0xf1060000 0 0x20000>;
2192 reg = <0 0xfe000000 0 0x80000>;
2195 bus-range = <0x00 0xff>;
2197 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2198 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2199 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2200 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2202 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2207 interrupt-map-mask = <0 0 0 0>;
2208 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2219 reg = <0 0xee800000 0 0x80000>;
2222 bus-range = <0x00 0xff>;
2224 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2225 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2226 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2227 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2229 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2234 interrupt-map-mask = <0 0 0 0>;
2235 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2246 reg = <0x0 0xfe000000 0 0x80000>,
2247 <0x0 0xfe100000 0 0x100000>,
2248 <0x0 0xfe200000 0 0x200000>,
2249 <0x0 0x30000000 0 0x8000000>,
2250 <0x0 0x38000000 0 0x8000000>;
2265 reg = <0x0 0xee800000 0 0x80000>,
2266 <0x0 0xee900000 0 0x100000>,
2267 <0x0 0xeea00000 0 0x200000>,
2268 <0x0 0xc0000000 0 0x8000000>,
2269 <0x0 0xc8000000 0 0x8000000>;
2283 reg = <0 0xfe940000 0 0x2400>;
2293 reg = <0 0xfe950000 0 0x200>;
2301 reg = <0 0xfe960000 0 0x8000>;
2312 reg = <0 0xfe9a0000 0 0x8000>;
2323 reg = <0 0xfea20000 0 0x5000>;
2334 reg = <0 0xfea28000 0 0x5000>;
2345 reg = <0 0xfe96f000 0 0x200>;
2353 reg = <0 0xfea27000 0 0x200>;
2361 reg = <0 0xfea2f000 0 0x200>;
2369 reg = <0 0xfe9af000 0 0x200>;
2377 reg = <0 0xfea80000 0 0x10000>;
2386 #size-cells = <0>;
2390 #size-cells = <0>;
2394 csi20vin0: endpoint@0 {
2395 reg = <0>;
2432 reg = <0 0xfeaa0000 0 0x10000>;
2441 #size-cells = <0>;
2445 #size-cells = <0>;
2449 csi40vin0: endpoint@0 {
2450 reg = <0>;
2488 reg = <0 0xfead0000 0 0x10000>;
2499 #size-cells = <0>;
2501 port@0 {
2502 reg = <0>;
2519 reg = <0 0xfeb00000 0 0x80000>;
2525 clock-names = "du.0", "du.1", "du.3";
2527 reset-names = "du.0", "du.3";
2530 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
2534 #size-cells = <0>;
2536 port@0 {
2537 reg = <0>;
2558 reg = <0 0xfeb90000 0 0x14>;
2566 #size-cells = <0>;
2568 port@0 {
2569 reg = <0>;
2584 reg = <0 0xfff00044 0 4>;
2592 thermal-sensors = <&tsc 0>;
2628 cooling-device = <&a57_0 0 2>;
2659 #clock-cells = <0>;
2660 clock-frequency = <0>;
2665 #clock-cells = <0>;
2666 clock-frequency = <0>;