Lines Matching +full:0 +full:xe6198000
32 * The external audio clocks are configured as 0 Hz fixed frequency
38 #clock-cells = <0>;
39 clock-frequency = <0>;
44 #clock-cells = <0>;
45 clock-frequency = <0>;
50 #clock-cells = <0>;
51 clock-frequency = <0>;
57 #clock-cells = <0>;
58 clock-frequency = <0>;
105 #size-cells = <0>;
133 a57_0: cpu@0 {
135 reg = <0x0>;
149 reg = <0x1>;
162 reg = <0x100>;
176 reg = <0x101>;
188 reg = <0x102>;
200 reg = <0x103>;
210 L2_CA57: cache-controller-0 {
227 #clock-cells = <0>;
229 clock-frequency = <0>;
234 #clock-cells = <0>;
236 clock-frequency = <0>;
242 #clock-cells = <0>;
243 clock-frequency = <0>;
270 #clock-cells = <0>;
271 clock-frequency = <0>;
284 reg = <0 0xe6020000 0 0x0c>;
294 reg = <0 0xe6050000 0 0x50>;
298 gpio-ranges = <&pfc 0 0 16>;
309 reg = <0 0xe6051000 0 0x50>;
313 gpio-ranges = <&pfc 0 32 29>;
324 reg = <0 0xe6052000 0 0x50>;
328 gpio-ranges = <&pfc 0 64 15>;
339 reg = <0 0xe6053000 0 0x50>;
343 gpio-ranges = <&pfc 0 96 16>;
354 reg = <0 0xe6054000 0 0x50>;
358 gpio-ranges = <&pfc 0 128 18>;
369 reg = <0 0xe6055000 0 0x50>;
373 gpio-ranges = <&pfc 0 160 26>;
384 reg = <0 0xe6055400 0 0x50>;
388 gpio-ranges = <&pfc 0 192 32>;
399 reg = <0 0xe6055800 0 0x50>;
403 gpio-ranges = <&pfc 0 224 4>;
413 reg = <0 0xe6060000 0 0x50c>;
419 reg = <0 0xe60f0000 0 0x1004>;
432 reg = <0 0xe6130000 0 0x1004>;
451 reg = <0 0xe6140000 0 0x1004>;
470 reg = <0 0xe6148000 0 0x1004>;
488 reg = <0 0xe6150000 0 0x0bb0>;
492 #power-domain-cells = <0>;
498 reg = <0 0xe6160000 0 0x018c>;
503 reg = <0 0xe6180000 0 0x0400>;
509 reg = <0 0xe6198000 0 0x100>,
510 <0 0xe61a0000 0 0x100>,
511 <0 0xe61a8000 0 0x100>;
525 reg = <0 0xe61c0000 0 0x200>;
526 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
539 reg = <0 0xe61e0000 0 0x30>;
552 reg = <0 0xe6fc0000 0 0x30>;
565 reg = <0 0xe6fd0000 0 0x30>;
578 reg = <0 0xe6fe0000 0 0x30>;
591 reg = <0 0xffc00000 0 0x30>;
604 #size-cells = <0>;
607 reg = <0 0xe6500000 0 0x40>;
612 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
613 <&dmac2 0x91>, <&dmac2 0x90>;
621 #size-cells = <0>;
624 reg = <0 0xe6508000 0 0x40>;
629 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
630 <&dmac2 0x93>, <&dmac2 0x92>;
638 #size-cells = <0>;
641 reg = <0 0xe6510000 0 0x40>;
646 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
647 <&dmac2 0x95>, <&dmac2 0x94>;
655 #size-cells = <0>;
658 reg = <0 0xe66d0000 0 0x40>;
663 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
671 #size-cells = <0>;
674 reg = <0 0xe66d8000 0 0x40>;
679 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
687 #size-cells = <0>;
690 reg = <0 0xe66e0000 0 0x40>;
695 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
703 #size-cells = <0>;
706 reg = <0 0xe66e8000 0 0x40>;
711 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
719 #size-cells = <0>;
723 reg = <0 0xe60b0000 0 0x425>;
728 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
737 reg = <0 0xe6540000 0 0x60>;
743 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
744 <&dmac2 0x31>, <&dmac2 0x30>;
755 reg = <0 0xe6550000 0 0x60>;
761 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
762 <&dmac2 0x33>, <&dmac2 0x32>;
773 reg = <0 0xe6560000 0 0x60>;
779 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
780 <&dmac2 0x35>, <&dmac2 0x34>;
791 reg = <0 0xe66a0000 0 0x60>;
797 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
808 reg = <0 0xe66b0000 0 0x60>;
814 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
824 reg = <0 0xe6590000 0 0x200>;
827 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
828 <&usb_dmac1 0>, <&usb_dmac1 1>;
841 reg = <0 0xe65a0000 0 0x100>;
855 reg = <0 0xe65b0000 0 0x100>;
869 reg = <0 0xe65ee000 0 0x90>;
875 #phy-cells = <0>;
882 reg = <0 0xe6700000 0 0x10000>;
911 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
924 reg = <0 0xe7300000 0 0x10000>;
953 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
966 reg = <0 0xe7310000 0 0x10000>;
1007 reg = <0 0xe6740000 0 0x1000>;
1008 renesas,ipmmu-main = <&ipmmu_mm 0>;
1015 reg = <0 0xe7740000 0 0x1000>;
1023 reg = <0 0xe6570000 0 0x1000>;
1031 reg = <0 0xe67b0000 0 0x1000>;
1040 reg = <0 0xec670000 0 0x1000>;
1048 reg = <0 0xfd800000 0 0x1000>;
1056 reg = <0 0xfd950000 0 0x1000>;
1064 reg = <0 0xfe6b0000 0 0x1000>;
1072 reg = <0 0xfebd0000 0 0x1000>;
1081 reg = <0 0xe6800000 0 0x800>;
1120 #size-cells = <0>;
1127 reg = <0 0xe6c30000 0 0x1000>;
1143 reg = <0 0xe6c38000 0 0x1000>;
1159 reg = <0 0xe66c0000 0 0x8000>;
1183 reg = <0 0xe6e30000 0 0x8>;
1193 reg = <0 0xe6e31000 0 0x8>;
1203 reg = <0 0xe6e32000 0 0x8>;
1213 reg = <0 0xe6e33000 0 0x8>;
1223 reg = <0 0xe6e34000 0 0x8>;
1233 reg = <0 0xe6e35000 0 0x8>;
1243 reg = <0 0xe6e36000 0 0x8>;
1254 reg = <0 0xe6e60000 0 0x40>;
1260 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1261 <&dmac2 0x51>, <&dmac2 0x50>;
1271 reg = <0 0xe6e68000 0 0x40>;
1277 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1278 <&dmac2 0x53>, <&dmac2 0x52>;
1288 reg = <0 0xe6e88000 0 0x40>;
1294 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1295 <&dmac2 0x13>, <&dmac2 0x12>;
1305 reg = <0 0xe6c50000 0 0x40>;
1311 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1321 reg = <0 0xe6c40000 0 0x40>;
1327 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1337 reg = <0 0xe6f30000 0 0x40>;
1343 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1344 <&dmac2 0x5b>, <&dmac2 0x5a>;
1354 reg = <0 0xe6e90000 0 0x0064>;
1357 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1358 <&dmac2 0x41>, <&dmac2 0x40>;
1363 #size-cells = <0>;
1370 reg = <0 0xe6ea0000 0 0x0064>;
1373 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1374 <&dmac2 0x43>, <&dmac2 0x42>;
1379 #size-cells = <0>;
1386 reg = <0 0xe6c00000 0 0x0064>;
1389 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1394 #size-cells = <0>;
1401 reg = <0 0xe6c10000 0 0x0064>;
1404 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1409 #size-cells = <0>;
1415 reg = <0 0xe6ef0000 0 0x1000>;
1420 renesas,id = <0>;
1425 #size-cells = <0>;
1429 #size-cells = <0>;
1433 vin0csi20: endpoint@0 {
1434 reg = <0>;
1447 reg = <0 0xe6ef1000 0 0x1000>;
1457 #size-cells = <0>;
1461 #size-cells = <0>;
1465 vin1csi20: endpoint@0 {
1466 reg = <0>;
1479 reg = <0 0xe6ef2000 0 0x1000>;
1489 #size-cells = <0>;
1493 #size-cells = <0>;
1497 vin2csi20: endpoint@0 {
1498 reg = <0>;
1511 reg = <0 0xe6ef3000 0 0x1000>;
1521 #size-cells = <0>;
1525 #size-cells = <0>;
1529 vin3csi20: endpoint@0 {
1530 reg = <0>;
1543 reg = <0 0xe6ef4000 0 0x1000>;
1553 #size-cells = <0>;
1557 #size-cells = <0>;
1561 vin4csi20: endpoint@0 {
1562 reg = <0>;
1575 reg = <0 0xe6ef5000 0 0x1000>;
1585 #size-cells = <0>;
1589 #size-cells = <0>;
1593 vin5csi20: endpoint@0 {
1594 reg = <0>;
1607 reg = <0 0xe6ef6000 0 0x1000>;
1617 #size-cells = <0>;
1621 #size-cells = <0>;
1625 vin6csi20: endpoint@0 {
1626 reg = <0>;
1639 reg = <0 0xe6ef7000 0 0x1000>;
1649 #size-cells = <0>;
1653 #size-cells = <0>;
1657 vin7csi20: endpoint@0 {
1658 reg = <0>;
1673 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1679 * clkout : #clock-cells = <0>; <&rcar_sound>;
1683 reg = <0 0xec500000 0 0x1000>, /* SCU */
1684 <0 0xec5a0000 0 0x100>, /* ADG */
1685 <0 0xec540000 0 0x1000>, /* SSIU */
1686 <0 0xec541000 0 0x280>, /* SSI */
1687 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1710 "ssi.1", "ssi.0",
1713 "src.1", "src.0",
1714 "mix.1", "mix.0",
1715 "ctu.1", "ctu.0",
1716 "dvc.0", "dvc.1",
1728 "ssi.1", "ssi.0";
1732 ctu00: ctu-0 { };
1743 dvc0: dvc-0 {
1744 dmas = <&audma1 0xbc>;
1748 dmas = <&audma1 0xbe>;
1754 mix0: mix-0 { };
1759 src0: src-0 {
1761 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1766 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1771 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1776 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1781 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1786 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1791 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1796 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1801 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1806 dmas = <&audma0 0x97>, <&audma1 0xba>;
1812 ssi0: ssi-0 {
1814 dmas = <&audma0 0x01>, <&audma1 0x02>;
1819 dmas = <&audma0 0x03>, <&audma1 0x04>;
1824 dmas = <&audma0 0x05>, <&audma1 0x06>;
1829 dmas = <&audma0 0x07>, <&audma1 0x08>;
1834 dmas = <&audma0 0x09>, <&audma1 0x0a>;
1839 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
1844 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
1849 dmas = <&audma0 0x0f>, <&audma1 0x10>;
1854 dmas = <&audma0 0x11>, <&audma1 0x12>;
1859 dmas = <&audma0 0x13>, <&audma1 0x14>;
1865 ssiu00: ssiu-0 {
1866 dmas = <&audma0 0x15>, <&audma1 0x16>;
1870 dmas = <&audma0 0x35>, <&audma1 0x36>;
1874 dmas = <&audma0 0x37>, <&audma1 0x38>;
1878 dmas = <&audma0 0x47>, <&audma1 0x48>;
1882 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1886 dmas = <&audma0 0x43>, <&audma1 0x44>;
1890 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1894 dmas = <&audma0 0x53>, <&audma1 0x54>;
1898 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1902 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1906 dmas = <&audma0 0x57>, <&audma1 0x58>;
1910 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1914 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1918 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1922 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1926 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1930 dmas = <&audma0 0x63>, <&audma1 0x64>;
1934 dmas = <&audma0 0x67>, <&audma1 0x68>;
1938 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
1942 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
1946 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
1950 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
1954 dmas = <&audma0 0xED>, <&audma1 0xEE>;
1958 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
1962 dmas = <&audma0 0x6f>, <&audma1 0x70>;
1966 dmas = <&audma0 0x21>, <&audma1 0x22>;
1970 dmas = <&audma0 0x23>, <&audma1 0x24>;
1974 dmas = <&audma0 0x25>, <&audma1 0x26>;
1978 dmas = <&audma0 0x27>, <&audma1 0x28>;
1982 dmas = <&audma0 0x29>, <&audma1 0x2A>;
1986 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
1990 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
1994 dmas = <&audma0 0x71>, <&audma1 0x72>;
1998 dmas = <&audma0 0x17>, <&audma1 0x18>;
2002 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2006 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2010 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2014 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2018 dmas = <&audma0 0x31>, <&audma1 0x32>;
2022 dmas = <&audma0 0x33>, <&audma1 0x34>;
2026 dmas = <&audma0 0x73>, <&audma1 0x74>;
2030 dmas = <&audma0 0x75>, <&audma1 0x76>;
2034 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2038 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2042 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2046 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2050 dmas = <&audma0 0x81>, <&audma1 0x82>;
2054 dmas = <&audma0 0x83>, <&audma1 0x84>;
2058 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2062 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2066 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2070 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2079 reg = <0 0xec700000 0 0x10000>;
2108 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
2121 reg = <0 0xec720000 0 0x10000>;
2163 reg = <0 0xee000000 0 0xc00>;
2174 reg = <0 0xee020000 0 0x400>;
2184 reg = <0 0xee080000 0 0x100>;
2196 reg = <0 0xee0a0000 0 0x100>;
2208 reg = <0 0xee080100 0 0x100>;
2221 reg = <0 0xee0a0100 0 0x100>;
2235 reg = <0 0xee080200 0 0x700>;
2247 reg = <0 0xee0a0200 0 0x700>;
2258 reg = <0 0xee100000 0 0x2000>;
2270 reg = <0 0xee120000 0 0x2000>;
2282 reg = <0 0xee140000 0 0x2000>;
2294 reg = <0 0xee160000 0 0x2000>;
2306 #address-cells = <0>;
2308 reg = <0x0 0xf1010000 0 0x1000>,
2309 <0x0 0xf1020000 0 0x20000>,
2310 <0x0 0xf1040000 0 0x20000>,
2311 <0x0 0xf1060000 0 0x20000>;
2323 reg = <0 0xfe000000 0 0x80000>;
2326 bus-range = <0x00 0xff>;
2328 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2329 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2330 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2331 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2333 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2338 interrupt-map-mask = <0 0 0 0>;
2339 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2350 reg = <0 0xee800000 0 0x80000>;
2353 bus-range = <0x00 0xff>;
2355 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2356 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2357 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2358 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2360 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2365 interrupt-map-mask = <0 0 0 0>;
2366 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2377 reg = <0x0 0xfe000000 0 0x80000>,
2378 <0x0 0xfe100000 0 0x100000>,
2379 <0x0 0xfe200000 0 0x200000>,
2380 <0x0 0x30000000 0 0x8000000>,
2381 <0x0 0x38000000 0 0x8000000>;
2396 reg = <0x0 0xee800000 0 0x80000>,
2397 <0x0 0xee900000 0 0x100000>,
2398 <0x0 0xeea00000 0 0x200000>,
2399 <0x0 0xc0000000 0 0x8000000>,
2400 <0x0 0xc8000000 0 0x8000000>;
2414 reg = <0 0xfe940000 0 0x2400>;
2424 reg = <0 0xfe950000 0 0x200>;
2432 reg = <0 0xfe96f000 0 0x200>;
2440 reg = <0 0xfea27000 0 0x200>;
2449 reg = <0 0xfea2f000 0 0x200>;
2458 reg = <0 0xfea37000 0 0x200>;
2467 reg = <0 0xfe9af000 0 0x200>;
2476 reg = <0 0xfe960000 0 0x8000>;
2487 reg = <0 0xfea20000 0 0x5000>;
2498 reg = <0 0xfea28000 0 0x5000>;
2509 reg = <0 0xfea30000 0 0x5000>;
2520 reg = <0 0xfe9a0000 0 0x8000>;
2531 reg = <0 0xfea80000 0 0x10000>;
2540 #size-cells = <0>;
2544 #size-cells = <0>;
2548 csi20vin0: endpoint@0 {
2549 reg = <0>;
2586 reg = <0 0xfeaa0000 0 0x10000>;
2595 #size-cells = <0>;
2599 #size-cells = <0>;
2603 csi40vin0: endpoint@0 {
2604 reg = <0>;
2643 reg = <0 0xfead0000 0 0x10000>;
2654 #size-cells = <0>;
2655 port@0 {
2656 reg = <0>;
2673 reg = <0 0xfeb00000 0 0x70000>;
2679 clock-names = "du.0", "du.1", "du.2";
2681 reset-names = "du.0", "du.2";
2684 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
2688 #size-cells = <0>;
2690 port@0 {
2691 reg = <0>;
2712 reg = <0 0xfeb90000 0 0x14>;
2720 #size-cells = <0>;
2722 port@0 {
2723 reg = <0>;
2738 reg = <0 0xfff00044 0 4>;
2746 thermal-sensors = <&tsc 0>;
2782 cooling-device = <&a57_0 0 2>;
2787 cooling-device = <&a53_0 0 2>;
2818 #clock-cells = <0>;
2819 clock-frequency = <0>;
2824 #clock-cells = <0>;
2825 clock-frequency = <0>;