Lines Matching +full:adreno +full:- +full:gmu
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/interconnect/qcom,osm-l3.h>
11 #include <dt-bindings/mailbox/qcom-ipcc.h>
12 #include <dt-bindings/power/qcom-aoss-qmp.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
15 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&intc>;
20 #address-cells = <2>;
21 #size-cells = <2>;
69 xo_board: xo-board {
70 compatible = "fixed-clock";
71 #clock-cells = <0>;
72 clock-frequency = <38400000>;
73 clock-output-names = "xo_board";
76 sleep_clk: sleep-clk {
77 compatible = "fixed-clock";
78 clock-frequency = <32768>;
79 #clock-cells = <0>;
84 #address-cells = <2>;
85 #size-cells = <0>;
91 enable-method = "psci";
92 next-level-cache = <&L2_0>;
93 qcom,freq-domain = <&cpufreq_hw 0>;
94 #cooling-cells = <2>;
95 L2_0: l2-cache {
97 next-level-cache = <&L3_0>;
98 L3_0: l3-cache {
108 enable-method = "psci";
109 next-level-cache = <&L2_100>;
110 qcom,freq-domain = <&cpufreq_hw 0>;
111 #cooling-cells = <2>;
112 L2_100: l2-cache {
114 next-level-cache = <&L3_0>;
122 enable-method = "psci";
123 next-level-cache = <&L2_200>;
124 qcom,freq-domain = <&cpufreq_hw 0>;
125 #cooling-cells = <2>;
126 L2_200: l2-cache {
128 next-level-cache = <&L3_0>;
136 enable-method = "psci";
137 next-level-cache = <&L2_300>;
138 qcom,freq-domain = <&cpufreq_hw 0>;
139 #cooling-cells = <2>;
140 L2_300: l2-cache {
142 next-level-cache = <&L3_0>;
150 enable-method = "psci";
151 next-level-cache = <&L2_400>;
152 qcom,freq-domain = <&cpufreq_hw 1>;
153 #cooling-cells = <2>;
154 L2_400: l2-cache {
156 next-level-cache = <&L3_0>;
164 enable-method = "psci";
165 next-level-cache = <&L2_500>;
166 qcom,freq-domain = <&cpufreq_hw 1>;
167 #cooling-cells = <2>;
168 L2_500: l2-cache {
170 next-level-cache = <&L3_0>;
179 enable-method = "psci";
180 next-level-cache = <&L2_600>;
181 qcom,freq-domain = <&cpufreq_hw 1>;
182 #cooling-cells = <2>;
183 L2_600: l2-cache {
185 next-level-cache = <&L3_0>;
193 enable-method = "psci";
194 next-level-cache = <&L2_700>;
195 qcom,freq-domain = <&cpufreq_hw 2>;
196 #cooling-cells = <2>;
197 L2_700: l2-cache {
199 next-level-cache = <&L3_0>;
207 #reset-cells = <1>;
218 compatible = "arm,armv8-pmuv3";
223 compatible = "arm,psci-1.0";
227 reserved-memory {
228 #address-cells = <2>;
229 #size-cells = <2>;
234 no-map;
239 no-map;
243 compatible = "qcom,cmd-db";
245 no-map;
250 no-map;
255 no-map;
260 no-map;
265 no-map;
270 no-map;
275 no-map;
280 no-map;
285 no-map;
290 no-map;
295 no-map;
300 no-map;
305 no-map;
310 no-map;
315 no-map;
320 no-map;
326 memory-region = <&smem_mem>;
330 smp2p-adsp {
333 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
339 qcom,local-pid = <0>;
340 qcom,remote-pid = <2>;
342 smp2p_adsp_out: master-kernel {
343 qcom,entry-name = "master-kernel";
344 #qcom,smem-state-cells = <1>;
347 smp2p_adsp_in: slave-kernel {
348 qcom,entry-name = "slave-kernel";
349 interrupt-controller;
350 #interrupt-cells = <2>;
354 smp2p-cdsp {
357 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
363 qcom,local-pid = <0>;
364 qcom,remote-pid = <5>;
366 smp2p_cdsp_out: master-kernel {
367 qcom,entry-name = "master-kernel";
368 #qcom,smem-state-cells = <1>;
371 smp2p_cdsp_in: slave-kernel {
372 qcom,entry-name = "slave-kernel";
373 interrupt-controller;
374 #interrupt-cells = <2>;
378 smp2p-slpi {
381 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
387 qcom,local-pid = <0>;
388 qcom,remote-pid = <3>;
390 smp2p_slpi_out: master-kernel {
391 qcom,entry-name = "master-kernel";
392 #qcom,smem-state-cells = <1>;
395 smp2p_slpi_in: slave-kernel {
396 qcom,entry-name = "slave-kernel";
397 interrupt-controller;
398 #interrupt-cells = <2>;
403 #address-cells = <2>;
404 #size-cells = <2>;
406 dma-ranges = <0 0 0 0 0x10 0>;
407 compatible = "simple-bus";
409 gcc: clock-controller@100000 {
410 compatible = "qcom,gcc-sm8250";
412 #clock-cells = <1>;
413 #reset-cells = <1>;
414 #power-domain-cells = <1>;
415 clock-names = "bi_tcxo",
424 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
427 interrupt-controller;
428 #interrupt-cells = <3>;
429 #mbox-cells = <2>;
432 qup_opp_table: qup-opp-table {
433 compatible = "operating-points-v2";
435 opp-50000000 {
436 opp-hz = /bits/ 64 <50000000>;
437 required-opps = <&rpmhpd_opp_min_svs>;
440 opp-75000000 {
441 opp-hz = /bits/ 64 <75000000>;
442 required-opps = <&rpmhpd_opp_low_svs>;
445 opp-120000000 {
446 opp-hz = /bits/ 64 <120000000>;
447 required-opps = <&rpmhpd_opp_svs>;
452 compatible = "qcom,geni-se-qup";
454 clock-names = "m-ahb", "s-ahb";
457 #address-cells = <2>;
458 #size-cells = <2>;
463 compatible = "qcom,geni-i2c";
465 clock-names = "se";
467 pinctrl-names = "default";
468 pinctrl-0 = <&qup_i2c14_default>;
470 #address-cells = <1>;
471 #size-cells = <0>;
476 compatible = "qcom,geni-spi";
478 clock-names = "se";
480 pinctrl-names = "default";
481 pinctrl-0 = <&qup_spi14_default>;
483 #address-cells = <1>;
484 #size-cells = <0>;
485 power-domains = <&rpmhpd SM8250_CX>;
486 operating-points-v2 = <&qup_opp_table>;
491 compatible = "qcom,geni-i2c";
493 clock-names = "se";
495 pinctrl-names = "default";
496 pinctrl-0 = <&qup_i2c15_default>;
498 #address-cells = <1>;
499 #size-cells = <0>;
504 compatible = "qcom,geni-spi";
506 clock-names = "se";
508 pinctrl-names = "default";
509 pinctrl-0 = <&qup_spi15_default>;
511 #address-cells = <1>;
512 #size-cells = <0>;
513 power-domains = <&rpmhpd SM8250_CX>;
514 operating-points-v2 = <&qup_opp_table>;
519 compatible = "qcom,geni-i2c";
521 clock-names = "se";
523 pinctrl-names = "default";
524 pinctrl-0 = <&qup_i2c16_default>;
526 #address-cells = <1>;
527 #size-cells = <0>;
532 compatible = "qcom,geni-spi";
534 clock-names = "se";
536 pinctrl-names = "default";
537 pinctrl-0 = <&qup_spi16_default>;
539 #address-cells = <1>;
540 #size-cells = <0>;
541 power-domains = <&rpmhpd SM8250_CX>;
542 operating-points-v2 = <&qup_opp_table>;
547 compatible = "qcom,geni-i2c";
549 clock-names = "se";
551 pinctrl-names = "default";
552 pinctrl-0 = <&qup_i2c17_default>;
554 #address-cells = <1>;
555 #size-cells = <0>;
560 compatible = "qcom,geni-spi";
562 clock-names = "se";
564 pinctrl-names = "default";
565 pinctrl-0 = <&qup_spi17_default>;
567 #address-cells = <1>;
568 #size-cells = <0>;
569 power-domains = <&rpmhpd SM8250_CX>;
570 operating-points-v2 = <&qup_opp_table>;
575 compatible = "qcom,geni-uart";
577 clock-names = "se";
579 pinctrl-names = "default";
580 pinctrl-0 = <&qup_uart17_default>;
582 power-domains = <&rpmhpd SM8250_CX>;
583 operating-points-v2 = <&qup_opp_table>;
588 compatible = "qcom,geni-i2c";
590 clock-names = "se";
592 pinctrl-names = "default";
593 pinctrl-0 = <&qup_i2c18_default>;
595 #address-cells = <1>;
596 #size-cells = <0>;
601 compatible = "qcom,geni-spi";
603 clock-names = "se";
605 pinctrl-names = "default";
606 pinctrl-0 = <&qup_spi18_default>;
608 #address-cells = <1>;
609 #size-cells = <0>;
610 power-domains = <&rpmhpd SM8250_CX>;
611 operating-points-v2 = <&qup_opp_table>;
616 compatible = "qcom,geni-uart";
618 clock-names = "se";
620 pinctrl-names = "default";
621 pinctrl-0 = <&qup_uart18_default>;
623 power-domains = <&rpmhpd SM8250_CX>;
624 operating-points-v2 = <&qup_opp_table>;
629 compatible = "qcom,geni-i2c";
631 clock-names = "se";
633 pinctrl-names = "default";
634 pinctrl-0 = <&qup_i2c19_default>;
636 #address-cells = <1>;
637 #size-cells = <0>;
642 compatible = "qcom,geni-spi";
644 clock-names = "se";
646 pinctrl-names = "default";
647 pinctrl-0 = <&qup_spi19_default>;
649 #address-cells = <1>;
650 #size-cells = <0>;
651 power-domains = <&rpmhpd SM8250_CX>;
652 operating-points-v2 = <&qup_opp_table>;
658 compatible = "qcom,geni-se-qup";
660 clock-names = "m-ahb", "s-ahb";
663 #address-cells = <2>;
664 #size-cells = <2>;
669 compatible = "qcom,geni-i2c";
671 clock-names = "se";
673 pinctrl-names = "default";
674 pinctrl-0 = <&qup_i2c0_default>;
676 #address-cells = <1>;
677 #size-cells = <0>;
682 compatible = "qcom,geni-spi";
684 clock-names = "se";
686 pinctrl-names = "default";
687 pinctrl-0 = <&qup_spi0_default>;
689 #address-cells = <1>;
690 #size-cells = <0>;
691 power-domains = <&rpmhpd SM8250_CX>;
692 operating-points-v2 = <&qup_opp_table>;
697 compatible = "qcom,geni-i2c";
699 clock-names = "se";
701 pinctrl-names = "default";
702 pinctrl-0 = <&qup_i2c1_default>;
704 #address-cells = <1>;
705 #size-cells = <0>;
710 compatible = "qcom,geni-spi";
712 clock-names = "se";
714 pinctrl-names = "default";
715 pinctrl-0 = <&qup_spi1_default>;
717 #address-cells = <1>;
718 #size-cells = <0>;
719 power-domains = <&rpmhpd SM8250_CX>;
720 operating-points-v2 = <&qup_opp_table>;
725 compatible = "qcom,geni-i2c";
727 clock-names = "se";
729 pinctrl-names = "default";
730 pinctrl-0 = <&qup_i2c2_default>;
732 #address-cells = <1>;
733 #size-cells = <0>;
738 compatible = "qcom,geni-spi";
740 clock-names = "se";
742 pinctrl-names = "default";
743 pinctrl-0 = <&qup_spi2_default>;
745 #address-cells = <1>;
746 #size-cells = <0>;
747 power-domains = <&rpmhpd SM8250_CX>;
748 operating-points-v2 = <&qup_opp_table>;
753 compatible = "qcom,geni-debug-uart";
755 clock-names = "se";
757 pinctrl-names = "default";
758 pinctrl-0 = <&qup_uart2_default>;
760 power-domains = <&rpmhpd SM8250_CX>;
761 operating-points-v2 = <&qup_opp_table>;
766 compatible = "qcom,geni-i2c";
768 clock-names = "se";
770 pinctrl-names = "default";
771 pinctrl-0 = <&qup_i2c3_default>;
773 #address-cells = <1>;
774 #size-cells = <0>;
779 compatible = "qcom,geni-spi";
781 clock-names = "se";
783 pinctrl-names = "default";
784 pinctrl-0 = <&qup_spi3_default>;
786 #address-cells = <1>;
787 #size-cells = <0>;
788 power-domains = <&rpmhpd SM8250_CX>;
789 operating-points-v2 = <&qup_opp_table>;
794 compatible = "qcom,geni-i2c";
796 clock-names = "se";
798 pinctrl-names = "default";
799 pinctrl-0 = <&qup_i2c4_default>;
801 #address-cells = <1>;
802 #size-cells = <0>;
807 compatible = "qcom,geni-spi";
809 clock-names = "se";
811 pinctrl-names = "default";
812 pinctrl-0 = <&qup_spi4_default>;
814 #address-cells = <1>;
815 #size-cells = <0>;
816 power-domains = <&rpmhpd SM8250_CX>;
817 operating-points-v2 = <&qup_opp_table>;
822 compatible = "qcom,geni-i2c";
824 clock-names = "se";
826 pinctrl-names = "default";
827 pinctrl-0 = <&qup_i2c5_default>;
829 #address-cells = <1>;
830 #size-cells = <0>;
835 compatible = "qcom,geni-spi";
837 clock-names = "se";
839 pinctrl-names = "default";
840 pinctrl-0 = <&qup_spi5_default>;
842 #address-cells = <1>;
843 #size-cells = <0>;
844 power-domains = <&rpmhpd SM8250_CX>;
845 operating-points-v2 = <&qup_opp_table>;
850 compatible = "qcom,geni-i2c";
852 clock-names = "se";
854 pinctrl-names = "default";
855 pinctrl-0 = <&qup_i2c6_default>;
857 #address-cells = <1>;
858 #size-cells = <0>;
863 compatible = "qcom,geni-spi";
865 clock-names = "se";
867 pinctrl-names = "default";
868 pinctrl-0 = <&qup_spi6_default>;
870 #address-cells = <1>;
871 #size-cells = <0>;
872 power-domains = <&rpmhpd SM8250_CX>;
873 operating-points-v2 = <&qup_opp_table>;
878 compatible = "qcom,geni-uart";
880 clock-names = "se";
882 pinctrl-names = "default";
883 pinctrl-0 = <&qup_uart6_default>;
885 power-domains = <&rpmhpd SM8250_CX>;
886 operating-points-v2 = <&qup_opp_table>;
891 compatible = "qcom,geni-i2c";
893 clock-names = "se";
895 pinctrl-names = "default";
896 pinctrl-0 = <&qup_i2c7_default>;
898 #address-cells = <1>;
899 #size-cells = <0>;
904 compatible = "qcom,geni-spi";
906 clock-names = "se";
908 pinctrl-names = "default";
909 pinctrl-0 = <&qup_spi7_default>;
911 #address-cells = <1>;
912 #size-cells = <0>;
913 power-domains = <&rpmhpd SM8250_CX>;
914 operating-points-v2 = <&qup_opp_table>;
920 compatible = "qcom,geni-se-qup";
922 clock-names = "m-ahb", "s-ahb";
925 #address-cells = <2>;
926 #size-cells = <2>;
931 compatible = "qcom,geni-i2c";
933 clock-names = "se";
935 pinctrl-names = "default";
936 pinctrl-0 = <&qup_i2c8_default>;
938 #address-cells = <1>;
939 #size-cells = <0>;
944 compatible = "qcom,geni-spi";
946 clock-names = "se";
948 pinctrl-names = "default";
949 pinctrl-0 = <&qup_spi8_default>;
951 #address-cells = <1>;
952 #size-cells = <0>;
953 power-domains = <&rpmhpd SM8250_CX>;
954 operating-points-v2 = <&qup_opp_table>;
959 compatible = "qcom,geni-i2c";
961 clock-names = "se";
963 pinctrl-names = "default";
964 pinctrl-0 = <&qup_i2c9_default>;
966 #address-cells = <1>;
967 #size-cells = <0>;
972 compatible = "qcom,geni-spi";
974 clock-names = "se";
976 pinctrl-names = "default";
977 pinctrl-0 = <&qup_spi9_default>;
979 #address-cells = <1>;
980 #size-cells = <0>;
981 power-domains = <&rpmhpd SM8250_CX>;
982 operating-points-v2 = <&qup_opp_table>;
987 compatible = "qcom,geni-i2c";
989 clock-names = "se";
991 pinctrl-names = "default";
992 pinctrl-0 = <&qup_i2c10_default>;
994 #address-cells = <1>;
995 #size-cells = <0>;
1000 compatible = "qcom,geni-spi";
1002 clock-names = "se";
1004 pinctrl-names = "default";
1005 pinctrl-0 = <&qup_spi10_default>;
1007 #address-cells = <1>;
1008 #size-cells = <0>;
1009 power-domains = <&rpmhpd SM8250_CX>;
1010 operating-points-v2 = <&qup_opp_table>;
1015 compatible = "qcom,geni-i2c";
1017 clock-names = "se";
1019 pinctrl-names = "default";
1020 pinctrl-0 = <&qup_i2c11_default>;
1022 #address-cells = <1>;
1023 #size-cells = <0>;
1028 compatible = "qcom,geni-spi";
1030 clock-names = "se";
1032 pinctrl-names = "default";
1033 pinctrl-0 = <&qup_spi11_default>;
1035 #address-cells = <1>;
1036 #size-cells = <0>;
1037 power-domains = <&rpmhpd SM8250_CX>;
1038 operating-points-v2 = <&qup_opp_table>;
1043 compatible = "qcom,geni-i2c";
1045 clock-names = "se";
1047 pinctrl-names = "default";
1048 pinctrl-0 = <&qup_i2c12_default>;
1050 #address-cells = <1>;
1051 #size-cells = <0>;
1056 compatible = "qcom,geni-spi";
1058 clock-names = "se";
1060 pinctrl-names = "default";
1061 pinctrl-0 = <&qup_spi12_default>;
1063 #address-cells = <1>;
1064 #size-cells = <0>;
1065 power-domains = <&rpmhpd SM8250_CX>;
1066 operating-points-v2 = <&qup_opp_table>;
1071 compatible = "qcom,geni-debug-uart";
1073 clock-names = "se";
1075 pinctrl-names = "default";
1076 pinctrl-0 = <&qup_uart12_default>;
1078 power-domains = <&rpmhpd SM8250_CX>;
1079 operating-points-v2 = <&qup_opp_table>;
1084 compatible = "qcom,geni-i2c";
1086 clock-names = "se";
1088 pinctrl-names = "default";
1089 pinctrl-0 = <&qup_i2c13_default>;
1091 #address-cells = <1>;
1092 #size-cells = <0>;
1097 compatible = "qcom,geni-spi";
1099 clock-names = "se";
1101 pinctrl-names = "default";
1102 pinctrl-0 = <&qup_spi13_default>;
1104 #address-cells = <1>;
1105 #size-cells = <0>;
1106 power-domains = <&rpmhpd SM8250_CX>;
1107 operating-points-v2 = <&qup_opp_table>;
1113 compatible = "qcom,sm8250-config-noc";
1115 #interconnect-cells = <1>;
1116 qcom,bcm-voters = <&apps_bcm_voter>;
1120 compatible = "qcom,sm8250-system-noc";
1122 #interconnect-cells = <1>;
1123 qcom,bcm-voters = <&apps_bcm_voter>;
1127 compatible = "qcom,sm8250-mc-virt";
1129 #interconnect-cells = <1>;
1130 qcom,bcm-voters = <&apps_bcm_voter>;
1134 compatible = "qcom,sm8250-aggre1-noc";
1136 #interconnect-cells = <1>;
1137 qcom,bcm-voters = <&apps_bcm_voter>;
1141 compatible = "qcom,sm8250-aggre2-noc";
1143 #interconnect-cells = <1>;
1144 qcom,bcm-voters = <&apps_bcm_voter>;
1148 compatible = "qcom,sm8250-compute-noc";
1150 #interconnect-cells = <1>;
1151 qcom,bcm-voters = <&apps_bcm_voter>;
1155 compatible = "qcom,sm8250-mmss-noc";
1157 #interconnect-cells = <1>;
1158 qcom,bcm-voters = <&apps_bcm_voter>;
1162 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
1163 "jedec,ufs-2.0";
1167 phy-names = "ufsphy";
1168 lanes-per-direction = <2>;
1169 #reset-cells = <1>;
1171 reset-names = "rst";
1173 power-domains = <&gcc UFS_PHY_GDSC>;
1175 clock-names =
1193 freq-table-hz =
1207 compatible = "qcom,sm8250-qmp-ufs-phy";
1209 #address-cells = <2>;
1210 #size-cells = <2>;
1212 clock-names = "ref",
1218 reset-names = "ufsphy";
1227 #phy-cells = <0>;
1232 compatible = "qcom,sm8250-ipa-virt";
1234 #interconnect-cells = <1>;
1235 qcom,bcm-voters = <&apps_bcm_voter>;
1239 compatible = "qcom,tcsr-mutex";
1241 #hwlock-cells = <1>;
1250 compatible = "qcom,adreno-650.2",
1251 "qcom,adreno",
1253 #stream-id-cells = <16>;
1256 reg-names = "kgsl_3d0_reg_memory";
1262 operating-points-v2 = <&gpu_opp_table>;
1264 qcom,gmu = <&gmu>;
1266 zap-shader {
1267 memory-region = <&gpu_mem>;
1271 gpu_opp_table: opp-table {
1272 compatible = "operating-points-v2";
1274 opp-670000000 {
1275 opp-hz = /bits/ 64 <670000000>;
1276 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1279 opp-587000000 {
1280 opp-hz = /bits/ 64 <587000000>;
1281 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1284 opp-525000000 {
1285 opp-hz = /bits/ 64 <525000000>;
1286 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1289 opp-490000000 {
1290 opp-hz = /bits/ 64 <490000000>;
1291 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1294 opp-441600000 {
1295 opp-hz = /bits/ 64 <441600000>;
1296 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
1299 opp-400000000 {
1300 opp-hz = /bits/ 64 <400000000>;
1301 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1304 opp-305000000 {
1305 opp-hz = /bits/ 64 <305000000>;
1306 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1311 gmu: gmu@3d6a000 { label
1312 compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
1318 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
1322 interrupt-names = "hfi", "gmu";
1329 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
1331 power-domains = <&gpucc GPU_CX_GDSC>,
1333 power-domain-names = "cx", "gx";
1337 operating-points-v2 = <&gmu_opp_table>;
1339 gmu_opp_table: opp-table {
1340 compatible = "operating-points-v2";
1342 opp-200000000 {
1343 opp-hz = /bits/ 64 <200000000>;
1344 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1349 gpucc: clock-controller@3d90000 {
1350 compatible = "qcom,sm8250-gpucc";
1355 clock-names = "bi_tcxo",
1358 #clock-cells = <1>;
1359 #reset-cells = <1>;
1360 #power-domain-cells = <1>;
1364 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
1366 #iommu-cells = <2>;
1367 #global-interrupts = <2>;
1381 clock-names = "ahb", "bus", "iface";
1383 power-domains = <&gpucc GPU_CX_GDSC>;
1387 compatible = "qcom,sm8250-slpi-pas";
1390 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
1395 interrupt-names = "wdog", "fatal", "ready",
1396 "handover", "stop-ack";
1399 clock-names = "xo";
1401 power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
1404 power-domain-names = "load_state", "lcx", "lmx";
1406 memory-region = <&slpi_mem>;
1408 qcom,smem-states = <&smp2p_slpi_out 0>;
1409 qcom,smem-state-names = "stop";
1413 glink-edge {
1414 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
1421 qcom,remote-pid = <3>;
1426 compatible = "qcom,sm8250-cdsp-pas";
1429 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
1434 interrupt-names = "wdog", "fatal", "ready",
1435 "handover", "stop-ack";
1438 clock-names = "xo";
1440 power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
1442 power-domain-names = "load_state", "cx";
1444 memory-region = <&cdsp_mem>;
1446 qcom,smem-states = <&smp2p_cdsp_out 0>;
1447 qcom,smem-state-names = "stop";
1451 glink-edge {
1452 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
1459 qcom,remote-pid = <5>;
1464 compatible = "qcom,sm8250-dc-noc";
1466 #interconnect-cells = <1>;
1467 qcom,bcm-voters = <&apps_bcm_voter>;
1471 compatible = "qcom,sm8250-gem-noc";
1473 #interconnect-cells = <1>;
1474 qcom,bcm-voters = <&apps_bcm_voter>;
1478 compatible = "qcom,sm8250-npu-noc";
1480 #interconnect-cells = <1>;
1481 qcom,bcm-voters = <&apps_bcm_voter>;
1484 pdc: interrupt-controller@b220000 {
1485 compatible = "qcom,sm8250-pdc", "qcom,pdc";
1487 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
1489 #interrupt-cells = <2>;
1490 interrupt-parent = <&intc>;
1491 interrupt-controller;
1494 tsens0: thermal-sensor@c263000 {
1495 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
1501 interrupt-names = "uplow", "critical";
1502 #thermal-sensor-cells = <1>;
1505 tsens1: thermal-sensor@c265000 {
1506 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
1512 interrupt-names = "uplow", "critical";
1513 #thermal-sensor-cells = <1>;
1517 compatible = "qcom,sm8250-aoss-qmp";
1519 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
1525 #clock-cells = <0>;
1526 #power-domain-cells = <1>;
1530 compatible = "qcom,spmi-pmic-arb";
1536 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1537 interrupt-names = "periph_irq";
1538 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1541 #address-cells = <2>;
1542 #size-cells = <0>;
1543 interrupt-controller;
1544 #interrupt-cells = <4>;
1548 compatible = "qcom,sm8250-pinctrl";
1552 reg-names = "west", "south", "north";
1554 gpio-controller;
1555 #gpio-cells = <2>;
1556 interrupt-controller;
1557 #interrupt-cells = <2>;
1558 gpio-ranges = <&tlmm 0 0 180>;
1559 wakeup-parent = <&pdc>;
1561 qup_i2c0_default: qup-i2c0-default {
1569 drive-strength = <2>;
1570 bias-disable;
1574 qup_i2c1_default: qup-i2c1-default {
1582 drive-strength = <2>;
1583 bias-disable;
1587 qup_i2c2_default: qup-i2c2-default {
1595 drive-strength = <2>;
1596 bias-disable;
1600 qup_i2c3_default: qup-i2c3-default {
1608 drive-strength = <2>;
1609 bias-disable;
1613 qup_i2c4_default: qup-i2c4-default {
1621 drive-strength = <2>;
1622 bias-disable;
1626 qup_i2c5_default: qup-i2c5-default {
1634 drive-strength = <2>;
1635 bias-disable;
1639 qup_i2c6_default: qup-i2c6-default {
1647 drive-strength = <2>;
1648 bias-disable;
1652 qup_i2c7_default: qup-i2c7-default {
1660 drive-strength = <2>;
1661 bias-disable;
1665 qup_i2c8_default: qup-i2c8-default {
1673 drive-strength = <2>;
1674 bias-disable;
1678 qup_i2c9_default: qup-i2c9-default {
1686 drive-strength = <2>;
1687 bias-disable;
1691 qup_i2c10_default: qup-i2c10-default {
1699 drive-strength = <2>;
1700 bias-disable;
1704 qup_i2c11_default: qup-i2c11-default {
1712 drive-strength = <2>;
1713 bias-disable;
1717 qup_i2c12_default: qup-i2c12-default {
1725 drive-strength = <2>;
1726 bias-disable;
1730 qup_i2c13_default: qup-i2c13-default {
1738 drive-strength = <2>;
1739 bias-disable;
1743 qup_i2c14_default: qup-i2c14-default {
1751 drive-strength = <2>;
1752 bias-disable;
1756 qup_i2c15_default: qup-i2c15-default {
1764 drive-strength = <2>;
1765 bias-disable;
1769 qup_i2c16_default: qup-i2c16-default {
1777 drive-strength = <2>;
1778 bias-disable;
1782 qup_i2c17_default: qup-i2c17-default {
1790 drive-strength = <2>;
1791 bias-disable;
1795 qup_i2c18_default: qup-i2c18-default {
1803 drive-strength = <2>;
1804 bias-disable;
1808 qup_i2c19_default: qup-i2c19-default {
1816 drive-strength = <2>;
1817 bias-disable;
1821 qup_spi0_default: qup-spi0-default {
1831 drive-strength = <6>;
1832 bias-disable;
1836 qup_spi1_default: qup-spi1-default {
1846 drive-strength = <6>;
1847 bias-disable;
1851 qup_spi2_default: qup-spi2-default {
1861 drive-strength = <6>;
1862 bias-disable;
1866 qup_spi3_default: qup-spi3-default {
1876 drive-strength = <6>;
1877 bias-disable;
1881 qup_spi4_default: qup-spi4-default {
1891 drive-strength = <6>;
1892 bias-disable;
1896 qup_spi5_default: qup-spi5-default {
1906 drive-strength = <6>;
1907 bias-disable;
1911 qup_spi6_default: qup-spi6-default {
1921 drive-strength = <6>;
1922 bias-disable;
1926 qup_spi7_default: qup-spi7-default {
1936 drive-strength = <6>;
1937 bias-disable;
1941 qup_spi8_default: qup-spi8-default {
1951 drive-strength = <6>;
1952 bias-disable;
1956 qup_spi9_default: qup-spi9-default {
1966 drive-strength = <6>;
1967 bias-disable;
1971 qup_spi10_default: qup-spi10-default {
1981 drive-strength = <6>;
1982 bias-disable;
1986 qup_spi11_default: qup-spi11-default {
1996 drive-strength = <6>;
1997 bias-disable;
2001 qup_spi12_default: qup-spi12-default {
2011 drive-strength = <6>;
2012 bias-disable;
2016 qup_spi13_default: qup-spi13-default {
2026 drive-strength = <6>;
2027 bias-disable;
2031 qup_spi14_default: qup-spi14-default {
2041 drive-strength = <6>;
2042 bias-disable;
2046 qup_spi15_default: qup-spi15-default {
2056 drive-strength = <6>;
2057 bias-disable;
2061 qup_spi16_default: qup-spi16-default {
2071 drive-strength = <6>;
2072 bias-disable;
2076 qup_spi17_default: qup-spi17-default {
2086 drive-strength = <6>;
2087 bias-disable;
2091 qup_spi18_default: qup-spi18-default {
2101 drive-strength = <6>;
2102 bias-disable;
2106 qup_spi19_default: qup-spi19-default {
2116 drive-strength = <6>;
2117 bias-disable;
2121 qup_uart2_default: qup-uart2-default {
2128 qup_uart6_default: qup-uart6-default {
2136 qup_uart12_default: qup-uart12-default {
2143 qup_uart17_default: qup-uart17-default {
2151 qup_uart18_default: qup-uart18-default {
2160 compatible = "qcom,sm8250-adsp-pas";
2163 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
2168 interrupt-names = "wdog", "fatal", "ready",
2169 "handover", "stop-ack";
2172 clock-names = "xo";
2174 power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
2177 power-domain-names = "load_state", "lcx", "lmx";
2179 memory-region = <&adsp_mem>;
2181 qcom,smem-states = <&smp2p_adsp_out 0>;
2182 qcom,smem-state-names = "stop";
2186 glink-edge {
2187 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2194 qcom,remote-pid = <2>;
2198 intc: interrupt-controller@17a00000 {
2199 compatible = "arm,gic-v3";
2200 #interrupt-cells = <3>;
2201 interrupt-controller;
2208 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
2214 #address-cells = <2>;
2215 #size-cells = <2>;
2217 compatible = "arm,armv7-timer-mem";
2219 clock-frequency = <19200000>;
2222 frame-number = <0>;
2230 frame-number = <1>;
2237 frame-number = <2>;
2244 frame-number = <3>;
2251 frame-number = <4>;
2258 frame-number = <5>;
2265 frame-number = <6>;
2274 compatible = "qcom,rpmh-rsc";
2278 reg-names = "drv-0", "drv-1", "drv-2";
2282 qcom,tcs-offset = <0xd00>;
2283 qcom,drv-id = <2>;
2284 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
2287 rpmhcc: clock-controller {
2288 compatible = "qcom,sm8250-rpmh-clk";
2289 #clock-cells = <1>;
2290 clock-names = "xo";
2294 rpmhpd: power-controller {
2295 compatible = "qcom,sm8250-rpmhpd";
2296 #power-domain-cells = <1>;
2297 operating-points-v2 = <&rpmhpd_opp_table>;
2299 rpmhpd_opp_table: opp-table {
2300 compatible = "operating-points-v2";
2303 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
2307 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2311 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2315 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2319 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2323 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2327 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2331 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
2335 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2339 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2345 compatible = "qcom,bcm-voter";
2350 compatible = "qcom,sm8250-epss-l3";
2354 clock-names = "xo", "alternate";
2356 #interconnect-cells = <1>;
2360 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
2364 reg-names = "freq-domain0", "freq-domain1",
2365 "freq-domain2";
2368 clock-names = "xo", "alternate";
2370 #freq-domain-cells = <1>;
2375 compatible = "arm,armv8-timer";
2386 thermal-zones {
2387 cpu0-thermal {
2388 polling-delay-passive = <250>;
2389 polling-delay = <1000>;
2391 thermal-sensors = <&tsens0 1>;
2394 cpu0_alert0: trip-point0 {
2400 cpu0_alert1: trip-point1 {
2413 cooling-maps {
2416 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2423 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2431 cpu1-thermal {
2432 polling-delay-passive = <250>;
2433 polling-delay = <1000>;
2435 thermal-sensors = <&tsens0 2>;
2438 cpu1_alert0: trip-point0 {
2444 cpu1_alert1: trip-point1 {
2457 cooling-maps {
2460 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2467 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2475 cpu2-thermal {
2476 polling-delay-passive = <250>;
2477 polling-delay = <1000>;
2479 thermal-sensors = <&tsens0 3>;
2482 cpu2_alert0: trip-point0 {
2488 cpu2_alert1: trip-point1 {
2501 cooling-maps {
2504 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2511 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2519 cpu3-thermal {
2520 polling-delay-passive = <250>;
2521 polling-delay = <1000>;
2523 thermal-sensors = <&tsens0 4>;
2526 cpu3_alert0: trip-point0 {
2532 cpu3_alert1: trip-point1 {
2545 cooling-maps {
2548 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2555 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2563 cpu4-top-thermal {
2564 polling-delay-passive = <250>;
2565 polling-delay = <1000>;
2567 thermal-sensors = <&tsens0 7>;
2570 cpu4_top_alert0: trip-point0 {
2576 cpu4_top_alert1: trip-point1 {
2589 cooling-maps {
2592 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2599 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2607 cpu5-top-thermal {
2608 polling-delay-passive = <250>;
2609 polling-delay = <1000>;
2611 thermal-sensors = <&tsens0 8>;
2614 cpu5_top_alert0: trip-point0 {
2620 cpu5_top_alert1: trip-point1 {
2633 cooling-maps {
2636 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2643 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2651 cpu6-top-thermal {
2652 polling-delay-passive = <250>;
2653 polling-delay = <1000>;
2655 thermal-sensors = <&tsens0 9>;
2658 cpu6_top_alert0: trip-point0 {
2664 cpu6_top_alert1: trip-point1 {
2677 cooling-maps {
2680 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2687 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2695 cpu7-top-thermal {
2696 polling-delay-passive = <250>;
2697 polling-delay = <1000>;
2699 thermal-sensors = <&tsens0 10>;
2702 cpu7_top_alert0: trip-point0 {
2708 cpu7_top_alert1: trip-point1 {
2721 cooling-maps {
2724 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2731 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2739 cpu4-bottom-thermal {
2740 polling-delay-passive = <250>;
2741 polling-delay = <1000>;
2743 thermal-sensors = <&tsens0 11>;
2746 cpu4_bottom_alert0: trip-point0 {
2752 cpu4_bottom_alert1: trip-point1 {
2765 cooling-maps {
2768 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2775 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2783 cpu5-bottom-thermal {
2784 polling-delay-passive = <250>;
2785 polling-delay = <1000>;
2787 thermal-sensors = <&tsens0 12>;
2790 cpu5_bottom_alert0: trip-point0 {
2796 cpu5_bottom_alert1: trip-point1 {
2809 cooling-maps {
2812 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2819 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2827 cpu6-bottom-thermal {
2828 polling-delay-passive = <250>;
2829 polling-delay = <1000>;
2831 thermal-sensors = <&tsens0 13>;
2834 cpu6_bottom_alert0: trip-point0 {
2840 cpu6_bottom_alert1: trip-point1 {
2853 cooling-maps {
2856 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2863 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2871 cpu7-bottom-thermal {
2872 polling-delay-passive = <250>;
2873 polling-delay = <1000>;
2875 thermal-sensors = <&tsens0 14>;
2878 cpu7_bottom_alert0: trip-point0 {
2884 cpu7_bottom_alert1: trip-point1 {
2897 cooling-maps {
2900 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2907 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2915 aoss0-thermal {
2916 polling-delay-passive = <250>;
2917 polling-delay = <1000>;
2919 thermal-sensors = <&tsens0 0>;
2922 aoss0_alert0: trip-point0 {
2930 cluster0-thermal {
2931 polling-delay-passive = <250>;
2932 polling-delay = <1000>;
2934 thermal-sensors = <&tsens0 5>;
2937 cluster0_alert0: trip-point0 {
2950 cluster1-thermal {
2951 polling-delay-passive = <250>;
2952 polling-delay = <1000>;
2954 thermal-sensors = <&tsens0 6>;
2957 cluster1_alert0: trip-point0 {
2970 gpu-thermal-top {
2971 polling-delay-passive = <250>;
2972 polling-delay = <1000>;
2974 thermal-sensors = <&tsens0 15>;
2977 gpu1_alert0: trip-point0 {
2985 aoss1-thermal {
2986 polling-delay-passive = <250>;
2987 polling-delay = <1000>;
2989 thermal-sensors = <&tsens1 0>;
2992 aoss1_alert0: trip-point0 {
3000 wlan-thermal {
3001 polling-delay-passive = <250>;
3002 polling-delay = <1000>;
3004 thermal-sensors = <&tsens1 1>;
3007 wlan_alert0: trip-point0 {
3015 video-thermal {
3016 polling-delay-passive = <250>;
3017 polling-delay = <1000>;
3019 thermal-sensors = <&tsens1 2>;
3022 video_alert0: trip-point0 {
3030 mem-thermal {
3031 polling-delay-passive = <250>;
3032 polling-delay = <1000>;
3034 thermal-sensors = <&tsens1 3>;
3037 mem_alert0: trip-point0 {
3045 q6-hvx-thermal {
3046 polling-delay-passive = <250>;
3047 polling-delay = <1000>;
3049 thermal-sensors = <&tsens1 4>;
3052 q6_hvx_alert0: trip-point0 {
3060 camera-thermal {
3061 polling-delay-passive = <250>;
3062 polling-delay = <1000>;
3064 thermal-sensors = <&tsens1 5>;
3067 camera_alert0: trip-point0 {
3075 compute-thermal {
3076 polling-delay-passive = <250>;
3077 polling-delay = <1000>;
3079 thermal-sensors = <&tsens1 6>;
3082 compute_alert0: trip-point0 {
3090 npu-thermal {
3091 polling-delay-passive = <250>;
3092 polling-delay = <1000>;
3094 thermal-sensors = <&tsens1 7>;
3097 npu_alert0: trip-point0 {
3105 gpu-thermal-bottom {
3106 polling-delay-passive = <250>;
3107 polling-delay = <1000>;
3109 thermal-sensors = <&tsens1 8>;
3112 gpu2_alert0: trip-point0 {