Lines Matching +full:0 +full:x01740000
71 #clock-cells = <0>;
79 #clock-cells = <0>;
85 #size-cells = <0>;
87 CPU0: cpu@0 {
90 reg = <0x0 0x0>;
93 qcom,freq-domain = <&cpufreq_hw 0>;
107 reg = <0x0 0x100>;
110 qcom,freq-domain = <&cpufreq_hw 0>;
121 reg = <0x0 0x200>;
124 qcom,freq-domain = <&cpufreq_hw 0>;
135 reg = <0x0 0x300>;
138 qcom,freq-domain = <&cpufreq_hw 0>;
149 reg = <0x0 0x400>;
163 reg = <0x0 0x500>;
178 reg = <0x0 0x600>;
192 reg = <0x0 0x700>;
214 reg = <0x0 0x80000000 0x0 0x0>;
233 reg = <0x0 0x80000000 0x0 0x600000>;
238 reg = <0x0 0x80700000 0x0 0x160000>;
244 reg = <0x0 0x80860000 0x0 0x20000>;
249 reg = <0x0 0x80900000 0x0 0x200000>;
254 reg = <0x0 0x80b00000 0x0 0x5300000>;
259 reg = <0x0 0x86200000 0x0 0x500000>;
264 reg = <0x0 0x86700000 0x0 0x100000>;
269 reg = <0x0 0x86800000 0x0 0x10000>;
274 reg = <0x0 0x86810000 0x0 0xa000>;
279 reg = <0x0 0x8681a000 0x0 0x2000>;
284 reg = <0x0 0x86900000 0x0 0x500000>;
289 reg = <0x0 0x86e00000 0x0 0x500000>;
294 reg = <0x0 0x87300000 0x0 0x500000>;
299 reg = <0x0 0x87800000 0x0 0x1400000>;
304 reg = <0x0 0x88c00000 0x0 0x1500000>;
309 reg = <0x0 0x8a100000 0x0 0x1d00000>;
314 reg = <0x0 0x8be00000 0x0 0x100000>;
319 reg = <0x0 0x8bf00000 0x0 0x4600000>;
339 qcom,local-pid = <0>;
363 qcom,local-pid = <0>;
387 qcom,local-pid = <0>;
402 soc: soc@0 {
405 ranges = <0 0 0 0 0x10 0>;
406 dma-ranges = <0 0 0 0 0x10 0>;
411 reg = <0x0 0x00100000 0x0 0x1f0000>;
425 reg = <0 0x00408000 0 0x1000>;
453 reg = <0x0 0x008c0000 0x0 0x6000>;
464 reg = <0 0x00880000 0 0x4000>;
468 pinctrl-0 = <&qup_i2c14_default>;
471 #size-cells = <0>;
477 reg = <0 0x00880000 0 0x4000>;
481 pinctrl-0 = <&qup_spi14_default>;
484 #size-cells = <0>;
492 reg = <0 0x00884000 0 0x4000>;
496 pinctrl-0 = <&qup_i2c15_default>;
499 #size-cells = <0>;
505 reg = <0 0x00884000 0 0x4000>;
509 pinctrl-0 = <&qup_spi15_default>;
512 #size-cells = <0>;
520 reg = <0 0x00888000 0 0x4000>;
524 pinctrl-0 = <&qup_i2c16_default>;
527 #size-cells = <0>;
533 reg = <0 0x00888000 0 0x4000>;
537 pinctrl-0 = <&qup_spi16_default>;
540 #size-cells = <0>;
548 reg = <0 0x0088c000 0 0x4000>;
552 pinctrl-0 = <&qup_i2c17_default>;
555 #size-cells = <0>;
561 reg = <0 0x0088c000 0 0x4000>;
565 pinctrl-0 = <&qup_spi17_default>;
568 #size-cells = <0>;
576 reg = <0 0x0088c000 0 0x4000>;
580 pinctrl-0 = <&qup_uart17_default>;
589 reg = <0 0x00890000 0 0x4000>;
593 pinctrl-0 = <&qup_i2c18_default>;
596 #size-cells = <0>;
602 reg = <0 0x00890000 0 0x4000>;
606 pinctrl-0 = <&qup_spi18_default>;
609 #size-cells = <0>;
617 reg = <0 0x00890000 0 0x4000>;
621 pinctrl-0 = <&qup_uart18_default>;
630 reg = <0 0x00894000 0 0x4000>;
634 pinctrl-0 = <&qup_i2c19_default>;
637 #size-cells = <0>;
643 reg = <0 0x00894000 0 0x4000>;
647 pinctrl-0 = <&qup_spi19_default>;
650 #size-cells = <0>;
659 reg = <0x0 0x009c0000 0x0 0x6000>;
670 reg = <0 0x00980000 0 0x4000>;
674 pinctrl-0 = <&qup_i2c0_default>;
677 #size-cells = <0>;
683 reg = <0 0x00980000 0 0x4000>;
687 pinctrl-0 = <&qup_spi0_default>;
690 #size-cells = <0>;
698 reg = <0 0x00984000 0 0x4000>;
702 pinctrl-0 = <&qup_i2c1_default>;
705 #size-cells = <0>;
711 reg = <0 0x00984000 0 0x4000>;
715 pinctrl-0 = <&qup_spi1_default>;
718 #size-cells = <0>;
726 reg = <0 0x00988000 0 0x4000>;
730 pinctrl-0 = <&qup_i2c2_default>;
733 #size-cells = <0>;
739 reg = <0 0x00988000 0 0x4000>;
743 pinctrl-0 = <&qup_spi2_default>;
746 #size-cells = <0>;
754 reg = <0 0x00988000 0 0x4000>;
758 pinctrl-0 = <&qup_uart2_default>;
767 reg = <0 0x0098c000 0 0x4000>;
771 pinctrl-0 = <&qup_i2c3_default>;
774 #size-cells = <0>;
780 reg = <0 0x0098c000 0 0x4000>;
784 pinctrl-0 = <&qup_spi3_default>;
787 #size-cells = <0>;
795 reg = <0 0x00990000 0 0x4000>;
799 pinctrl-0 = <&qup_i2c4_default>;
802 #size-cells = <0>;
808 reg = <0 0x00990000 0 0x4000>;
812 pinctrl-0 = <&qup_spi4_default>;
815 #size-cells = <0>;
823 reg = <0 0x00994000 0 0x4000>;
827 pinctrl-0 = <&qup_i2c5_default>;
830 #size-cells = <0>;
836 reg = <0 0x00994000 0 0x4000>;
840 pinctrl-0 = <&qup_spi5_default>;
843 #size-cells = <0>;
851 reg = <0 0x00998000 0 0x4000>;
855 pinctrl-0 = <&qup_i2c6_default>;
858 #size-cells = <0>;
864 reg = <0 0x00998000 0 0x4000>;
868 pinctrl-0 = <&qup_spi6_default>;
871 #size-cells = <0>;
879 reg = <0 0x00998000 0 0x4000>;
883 pinctrl-0 = <&qup_uart6_default>;
892 reg = <0 0x0099c000 0 0x4000>;
896 pinctrl-0 = <&qup_i2c7_default>;
899 #size-cells = <0>;
905 reg = <0 0x0099c000 0 0x4000>;
909 pinctrl-0 = <&qup_spi7_default>;
912 #size-cells = <0>;
921 reg = <0x0 0x00ac0000 0x0 0x6000>;
932 reg = <0 0x00a80000 0 0x4000>;
936 pinctrl-0 = <&qup_i2c8_default>;
939 #size-cells = <0>;
945 reg = <0 0x00a80000 0 0x4000>;
949 pinctrl-0 = <&qup_spi8_default>;
952 #size-cells = <0>;
960 reg = <0 0x00a84000 0 0x4000>;
964 pinctrl-0 = <&qup_i2c9_default>;
967 #size-cells = <0>;
973 reg = <0 0x00a84000 0 0x4000>;
977 pinctrl-0 = <&qup_spi9_default>;
980 #size-cells = <0>;
988 reg = <0 0x00a88000 0 0x4000>;
992 pinctrl-0 = <&qup_i2c10_default>;
995 #size-cells = <0>;
1001 reg = <0 0x00a88000 0 0x4000>;
1005 pinctrl-0 = <&qup_spi10_default>;
1008 #size-cells = <0>;
1016 reg = <0 0x00a8c000 0 0x4000>;
1020 pinctrl-0 = <&qup_i2c11_default>;
1023 #size-cells = <0>;
1029 reg = <0 0x00a8c000 0 0x4000>;
1033 pinctrl-0 = <&qup_spi11_default>;
1036 #size-cells = <0>;
1044 reg = <0 0x00a90000 0 0x4000>;
1048 pinctrl-0 = <&qup_i2c12_default>;
1051 #size-cells = <0>;
1057 reg = <0 0x00a90000 0 0x4000>;
1061 pinctrl-0 = <&qup_spi12_default>;
1064 #size-cells = <0>;
1072 reg = <0x0 0x00a90000 0x0 0x4000>;
1076 pinctrl-0 = <&qup_uart12_default>;
1085 reg = <0 0x00a94000 0 0x4000>;
1089 pinctrl-0 = <&qup_i2c13_default>;
1092 #size-cells = <0>;
1098 reg = <0 0x00a94000 0 0x4000>;
1102 pinctrl-0 = <&qup_spi13_default>;
1105 #size-cells = <0>;
1114 reg = <0 0x01500000 0 0xa580>;
1121 reg = <0 0x01620000 0 0x1c200>;
1128 reg = <0 0x0163d000 0 0x1000>;
1135 reg = <0 0x016e0000 0 0x1f180>;
1142 reg = <0 0x01700000 0 0x33000>;
1149 reg = <0 0x01733000 0 0xa180>;
1156 reg = <0 0x01740000 0 0x1f080>;
1164 reg = <0 0x01d84000 0 0x3000>;
1195 <0 0>,
1196 <0 0>,
1198 <0 0>,
1199 <0 0>,
1200 <0 0>,
1201 <0 0>;
1208 reg = <0 0x01d87000 0 0x1c0>;
1217 resets = <&ufs_mem_hc 0>;
1222 reg = <0 0x01d87400 0 0x108>,
1223 <0 0x01d87600 0 0x1e0>,
1224 <0 0x01d87c00 0 0x1dc>,
1225 <0 0x01d87800 0 0x108>,
1226 <0 0x01d87a00 0 0x1e0>;
1227 #phy-cells = <0>;
1233 reg = <0 0x01e00000 0 0x1000>;
1240 reg = <0x0 0x01f40000 0x0 0x40000>;
1255 reg = <0 0x03d00000 0 0x40000>;
1260 iommus = <&adreno_smmu 0 0x401>;
1314 reg = <0 0x03d6a000 0 0x30000>,
1315 <0 0x3de0000 0 0x10000>,
1316 <0 0xb290000 0 0x10000>,
1317 <0 0xb490000 0 0x10000>;
1335 iommus = <&adreno_smmu 5 0x400>;
1351 reg = <0 0x03d90000 0 0x9000>;
1365 reg = <0 0x03da0000 0 0x10000>;
1388 reg = <0 0x05c00000 0 0x4000>;
1391 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
1408 qcom,smem-states = <&smp2p_slpi_out 0>;
1427 reg = <0 0x08300000 0 0x10000>;
1430 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
1446 qcom,smem-states = <&smp2p_cdsp_out 0>;
1465 reg = <0 0x090c0000 0 0x4200>;
1472 reg = <0 0x09100000 0 0xb4000>;
1479 reg = <0 0x09990000 0 0x1600>;
1486 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
1487 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
1496 reg = <0 0x0c263000 0 0x1ff>, /* TM */
1497 <0 0x0c222000 0 0x1ff>; /* SROT */
1507 reg = <0 0x0c265000 0 0x1ff>, /* TM */
1508 <0 0x0c223000 0 0x1ff>; /* SROT */
1518 reg = <0 0x0c300000 0 0x100000>;
1525 #clock-cells = <0>;
1531 reg = <0x0 0x0c440000 0x0 0x0001100>,
1532 <0x0 0x0c600000 0x0 0x2000000>,
1533 <0x0 0x0e600000 0x0 0x0100000>,
1534 <0x0 0x0e700000 0x0 0x00a0000>,
1535 <0x0 0x0c40a000 0x0 0x0026000>;
1539 qcom,ee = <0>;
1540 qcom,channel = <0>;
1542 #size-cells = <0>;
1549 reg = <0 0x0f100000 0 0x300000>,
1550 <0 0x0f500000 0 0x300000>,
1551 <0 0x0f900000 0 0x300000>;
1558 gpio-ranges = <&tlmm 0 0 180>;
2161 reg = <0 0x17300000 0 0x100>;
2164 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2181 qcom,smem-states = <&smp2p_adsp_out 0>;
2202 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
2203 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
2209 reg = <0 0x17c10000 0 0x1000>;
2218 reg = <0x0 0x17c20000 0x0 0x1000>;
2222 frame-number = <0>;
2225 reg = <0x0 0x17c21000 0x0 0x1000>,
2226 <0x0 0x17c22000 0x0 0x1000>;
2232 reg = <0x0 0x17c23000 0x0 0x1000>;
2239 reg = <0x0 0x17c25000 0x0 0x1000>;
2246 reg = <0x0 0x17c27000 0x0 0x1000>;
2253 reg = <0x0 0x17c29000 0x0 0x1000>;
2260 reg = <0x0 0x17c2b000 0x0 0x1000>;
2267 reg = <0x0 0x17c2d000 0x0 0x1000>;
2275 reg = <0x0 0x18200000 0x0 0x10000>,
2276 <0x0 0x18210000 0x0 0x10000>,
2277 <0x0 0x18220000 0x0 0x10000>;
2278 reg-names = "drv-0", "drv-1", "drv-2";
2282 qcom,tcs-offset = <0xd00>;
2351 reg = <0 0x18590000 0 0x1000>;
2361 reg = <0 0x18591000 0 0x1000>,
2362 <0 0x18592000 0 0x1000>,
2363 <0 0x18593000 0 0x1000>;
2919 thermal-sensors = <&tsens0 0>;
2989 thermal-sensors = <&tsens1 0>;