Lines Matching +full:adreno +full:- +full:gmu
1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/power/qcom-aoss-qmp.h>
9 #include <dt-bindings/power/qcom-rpmpd.h>
10 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
13 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
15 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&intc>;
20 #address-cells = <2>;
21 #size-cells = <2>;
26 xo_board: xo-board {
27 compatible = "fixed-clock";
28 #clock-cells = <0>;
29 clock-frequency = <38400000>;
30 clock-output-names = "xo_board";
33 sleep_clk: sleep-clk {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <32764>;
37 clock-output-names = "sleep_clk";
42 #address-cells = <2>;
43 #size-cells = <0>;
49 enable-method = "psci";
50 next-level-cache = <&L2_0>;
51 qcom,freq-domain = <&cpufreq_hw 0>;
52 #cooling-cells = <2>;
53 L2_0: l2-cache {
55 next-level-cache = <&L3_0>;
56 L3_0: l3-cache {
66 enable-method = "psci";
67 next-level-cache = <&L2_100>;
68 qcom,freq-domain = <&cpufreq_hw 0>;
69 #cooling-cells = <2>;
70 L2_100: l2-cache {
72 next-level-cache = <&L3_0>;
81 enable-method = "psci";
82 next-level-cache = <&L2_200>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
84 #cooling-cells = <2>;
85 L2_200: l2-cache {
87 next-level-cache = <&L3_0>;
95 enable-method = "psci";
96 next-level-cache = <&L2_300>;
97 qcom,freq-domain = <&cpufreq_hw 0>;
98 #cooling-cells = <2>;
99 L2_300: l2-cache {
101 next-level-cache = <&L3_0>;
109 enable-method = "psci";
110 next-level-cache = <&L2_400>;
111 qcom,freq-domain = <&cpufreq_hw 1>;
112 #cooling-cells = <2>;
113 L2_400: l2-cache {
115 next-level-cache = <&L3_0>;
123 enable-method = "psci";
124 next-level-cache = <&L2_500>;
125 qcom,freq-domain = <&cpufreq_hw 1>;
126 #cooling-cells = <2>;
127 L2_500: l2-cache {
129 next-level-cache = <&L3_0>;
137 enable-method = "psci";
138 next-level-cache = <&L2_600>;
139 qcom,freq-domain = <&cpufreq_hw 1>;
140 #cooling-cells = <2>;
141 L2_600: l2-cache {
143 next-level-cache = <&L3_0>;
151 enable-method = "psci";
152 next-level-cache = <&L2_700>;
153 qcom,freq-domain = <&cpufreq_hw 2>;
154 #cooling-cells = <2>;
155 L2_700: l2-cache {
157 next-level-cache = <&L3_0>;
164 compatible = "qcom,scm-sm8150", "qcom,scm";
165 #reset-cells = <1>;
170 compatible = "qcom,tcsr-mutex";
172 #hwlock-cells = <1>;
182 compatible = "arm,armv8-pmuv3";
187 compatible = "arm,psci-1.0";
191 reserved-memory {
192 #address-cells = <2>;
193 #size-cells = <2>;
198 no-map;
203 no-map;
208 no-map;
212 compatible = "qcom,cmd-db";
214 no-map;
219 no-map;
224 no-map;
228 compatible = "qcom,rmtfs-mem";
230 no-map;
232 qcom,client-id = <1>;
238 no-map;
243 no-map;
248 no-map;
253 no-map;
258 no-map;
263 no-map;
268 no-map;
273 no-map;
278 no-map;
283 no-map;
288 no-map;
293 no-map;
298 no-map;
304 memory-region = <&smem_mem>;
308 smp2p-cdsp {
316 qcom,local-pid = <0>;
317 qcom,remote-pid = <5>;
319 cdsp_smp2p_out: master-kernel {
320 qcom,entry-name = "master-kernel";
321 #qcom,smem-state-cells = <1>;
324 cdsp_smp2p_in: slave-kernel {
325 qcom,entry-name = "slave-kernel";
327 interrupt-controller;
328 #interrupt-cells = <2>;
332 smp2p-lpass {
340 qcom,local-pid = <0>;
341 qcom,remote-pid = <2>;
343 adsp_smp2p_out: master-kernel {
344 qcom,entry-name = "master-kernel";
345 #qcom,smem-state-cells = <1>;
348 adsp_smp2p_in: slave-kernel {
349 qcom,entry-name = "slave-kernel";
351 interrupt-controller;
352 #interrupt-cells = <2>;
356 smp2p-mpss {
364 qcom,local-pid = <0>;
365 qcom,remote-pid = <1>;
367 modem_smp2p_out: master-kernel {
368 qcom,entry-name = "master-kernel";
369 #qcom,smem-state-cells = <1>;
372 modem_smp2p_in: slave-kernel {
373 qcom,entry-name = "slave-kernel";
375 interrupt-controller;
376 #interrupt-cells = <2>;
380 smp2p-slpi {
388 qcom,local-pid = <0>;
389 qcom,remote-pid = <3>;
391 slpi_smp2p_out: master-kernel {
392 qcom,entry-name = "master-kernel";
393 #qcom,smem-state-cells = <1>;
396 slpi_smp2p_in: slave-kernel {
397 qcom,entry-name = "slave-kernel";
399 interrupt-controller;
400 #interrupt-cells = <2>;
405 #address-cells = <2>;
406 #size-cells = <2>;
408 dma-ranges = <0 0 0 0 0x10 0>;
409 compatible = "simple-bus";
411 gcc: clock-controller@100000 {
412 compatible = "qcom,gcc-sm8150";
414 #clock-cells = <1>;
415 #reset-cells = <1>;
416 #power-domain-cells = <1>;
417 clock-names = "bi_tcxo",
424 compatible = "qcom,geni-se-qup";
426 clock-names = "m-ahb", "s-ahb";
429 #address-cells = <2>;
430 #size-cells = <2>;
435 compatible = "qcom,geni-debug-uart";
437 clock-names = "se";
445 compatible = "qcom,sm8150-config-noc";
447 #interconnect-cells = <1>;
448 qcom,bcm-voters = <&apps_bcm_voter>;
452 compatible = "qcom,sm8150-system-noc";
454 #interconnect-cells = <1>;
455 qcom,bcm-voters = <&apps_bcm_voter>;
459 compatible = "qcom,sm8150-mc-virt";
461 #interconnect-cells = <1>;
462 qcom,bcm-voters = <&apps_bcm_voter>;
466 compatible = "qcom,sm8150-aggre1-noc";
468 #interconnect-cells = <1>;
469 qcom,bcm-voters = <&apps_bcm_voter>;
473 compatible = "qcom,sm8150-aggre2-noc";
475 #interconnect-cells = <1>;
476 qcom,bcm-voters = <&apps_bcm_voter>;
480 compatible = "qcom,sm8150-compute-noc";
482 #interconnect-cells = <1>;
483 qcom,bcm-voters = <&apps_bcm_voter>;
487 compatible = "qcom,sm8150-mmss-noc";
489 #interconnect-cells = <1>;
490 qcom,bcm-voters = <&apps_bcm_voter>;
494 compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
495 "jedec,ufs-2.0";
499 phy-names = "ufsphy";
500 lanes-per-direction = <2>;
501 #reset-cells = <1>;
503 reset-names = "rst";
505 clock-names =
523 freq-table-hz =
537 compatible = "qcom,sm8150-qmp-ufs-phy";
539 #address-cells = <2>;
540 #size-cells = <2>;
542 clock-names = "ref",
548 reset-names = "ufsphy";
557 #phy-cells = <0>;
562 compatible = "qcom,sm8150-ipa-virt";
564 #interconnect-cells = <1>;
565 qcom,bcm-voters = <&apps_bcm_voter>;
574 compatible = "qcom,sm8150-slpi-pas";
577 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
582 interrupt-names = "wdog", "fatal", "ready",
583 "handover", "stop-ack";
586 clock-names = "xo";
588 power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
591 power-domain-names = "load_state", "lcx", "lmx";
593 memory-region = <&slpi_mem>;
595 qcom,smem-states = <&slpi_smp2p_out 0>;
596 qcom,smem-state-names = "stop";
600 glink-edge {
603 qcom,remote-pid = <3>;
614 compatible = "qcom,adreno-640.1",
615 "qcom,adreno",
617 #stream-id-cells = <16>;
620 reg-names = "kgsl_3d0_reg_memory";
626 operating-points-v2 = <&gpu_opp_table>;
628 qcom,gmu = <&gmu>;
630 zap-shader {
631 memory-region = <&gpu_mem>;
635 gpu_opp_table: opp-table {
636 compatible = "operating-points-v2";
638 opp-675000000 {
639 opp-hz = /bits/ 64 <675000000>;
640 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
643 opp-585000000 {
644 opp-hz = /bits/ 64 <585000000>;
645 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
648 opp-499200000 {
649 opp-hz = /bits/ 64 <499200000>;
650 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
653 opp-427000000 {
654 opp-hz = /bits/ 64 <427000000>;
655 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
658 opp-345000000 {
659 opp-hz = /bits/ 64 <345000000>;
660 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
663 opp-257000000 {
664 opp-hz = /bits/ 64 <257000000>;
665 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
670 gmu: gmu@2c6a000 { label
671 compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
676 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
680 interrupt-names = "hfi", "gmu";
687 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
689 power-domains = <&gpucc GPU_CX_GDSC>,
691 power-domain-names = "cx", "gx";
695 operating-points-v2 = <&gmu_opp_table>;
697 gmu_opp_table: opp-table {
698 compatible = "operating-points-v2";
700 opp-200000000 {
701 opp-hz = /bits/ 64 <200000000>;
702 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
707 gpucc: clock-controller@2c90000 {
708 compatible = "qcom,sm8150-gpucc";
713 clock-names = "bi_tcxo",
716 #clock-cells = <1>;
717 #reset-cells = <1>;
718 #power-domain-cells = <1>;
722 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
724 #iommu-cells = <2>;
725 #global-interrupts = <1>;
738 clock-names = "ahb", "bus", "iface";
740 power-domains = <&gpucc GPU_CX_GDSC>;
744 compatible = "qcom,sm8150-pinctrl";
749 reg-names = "west", "east", "north", "south";
751 gpio-ranges = <&tlmm 0 0 175>;
752 gpio-controller;
753 #gpio-cells = <2>;
754 interrupt-controller;
755 #interrupt-cells = <2>;
759 compatible = "qcom,sm8150-mpss-pas";
762 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
768 interrupt-names = "wdog", "fatal", "ready", "handover",
769 "stop-ack", "shutdown-ack";
772 clock-names = "xo";
774 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
777 power-domain-names = "load_state", "cx", "mss";
779 memory-region = <&mpss_mem>;
781 qcom,smem-states = <&modem_smp2p_out 0>;
782 qcom,smem-state-names = "stop";
784 glink-edge {
787 qcom,remote-pid = <1>;
793 compatible = "qcom,sm8150-cdsp-pas";
796 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
801 interrupt-names = "wdog", "fatal", "ready",
802 "handover", "stop-ack";
805 clock-names = "xo";
807 power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
809 power-domain-names = "load_state", "cx";
811 memory-region = <&cdsp_mem>;
813 qcom,smem-states = <&cdsp_smp2p_out 0>;
814 qcom,smem-state-names = "stop";
818 glink-edge {
821 qcom,remote-pid = <5>;
827 compatible = "qcom,sm8150-usb-hs-phy",
828 "qcom,usb-snps-hs-7nm-phy";
831 #phy-cells = <0>;
834 clock-names = "ref";
840 compatible = "qcom,sm8150-qmp-usb3-phy";
843 reg-names = "reg-base", "dp_com";
845 #clock-cells = <1>;
846 #address-cells = <2>;
847 #size-cells = <2>;
854 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
858 reset-names = "phy", "common";
867 #phy-cells = <0>;
869 clock-names = "pipe0";
870 clock-output-names = "usb3_phy_pipe_clk_src";
875 compatible = "qcom,sm8150-dc-noc";
877 #interconnect-cells = <1>;
878 qcom,bcm-voters = <&apps_bcm_voter>;
882 compatible = "qcom,sm8150-gem-noc";
884 #interconnect-cells = <1>;
885 qcom,bcm-voters = <&apps_bcm_voter>;
889 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
892 #address-cells = <2>;
893 #size-cells = <2>;
895 dma-ranges;
903 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
906 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
908 assigned-clock-rates = <19200000>, <200000000>;
914 interrupt-names = "hs_phy_irq", "ss_phy_irq",
917 power-domains = <&gcc USB30_PRIM_GDSC>;
928 phy-names = "usb2-phy", "usb3-phy";
933 compatible = "qcom,sm8150-camnoc-virt";
935 #interconnect-cells = <1>;
936 qcom,bcm-voters = <&apps_bcm_voter>;
939 aoss_qmp: power-controller@c300000 {
940 compatible = "qcom,sm8150-aoss-qmp";
945 #clock-cells = <0>;
946 #power-domain-cells = <1>;
949 tsens0: thermal-sensor@c263000 {
950 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
956 interrupt-names = "uplow", "critical";
957 #thermal-sensor-cells = <1>;
960 tsens1: thermal-sensor@c265000 {
961 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
967 interrupt-names = "uplow", "critical";
968 #thermal-sensor-cells = <1>;
972 compatible = "qcom,spmi-pmic-arb";
978 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
979 interrupt-names = "periph_irq";
983 #address-cells = <2>;
984 #size-cells = <0>;
985 interrupt-controller;
986 #interrupt-cells = <4>;
987 cell-index = <0>;
991 compatible = "qcom,sm8150-adsp-pas";
994 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
999 interrupt-names = "wdog", "fatal", "ready",
1000 "handover", "stop-ack";
1003 clock-names = "xo";
1005 power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
1007 power-domain-names = "load_state", "cx";
1009 memory-region = <&adsp_mem>;
1011 qcom,smem-states = <&adsp_smp2p_out 0>;
1012 qcom,smem-state-names = "stop";
1016 glink-edge {
1019 qcom,remote-pid = <2>;
1024 intc: interrupt-controller@17a00000 {
1025 compatible = "arm,gic-v3";
1026 interrupt-controller;
1027 #interrupt-cells = <3>;
1034 compatible = "qcom,sm8150-apss-shared";
1036 #mbox-cells = <1>;
1040 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
1046 #address-cells = <2>;
1047 #size-cells = <2>;
1049 compatible = "arm,armv7-timer-mem";
1051 clock-frequency = <19200000>;
1054 frame-number = <0>;
1062 frame-number = <1>;
1069 frame-number = <2>;
1076 frame-number = <3>;
1083 frame-number = <4>;
1090 frame-number = <5>;
1097 frame-number = <6>;
1106 compatible = "qcom,rpmh-rsc";
1110 reg-names = "drv-0", "drv-1", "drv-2";
1114 qcom,tcs-offset = <0xd00>;
1115 qcom,drv-id = <2>;
1116 qcom,tcs-config = <ACTIVE_TCS 2>,
1121 rpmhcc: clock-controller {
1122 compatible = "qcom,sm8150-rpmh-clk";
1123 #clock-cells = <1>;
1124 clock-names = "xo";
1128 rpmhpd: power-controller {
1129 compatible = "qcom,sm8150-rpmhpd";
1130 #power-domain-cells = <1>;
1131 operating-points-v2 = <&rpmhpd_opp_table>;
1133 rpmhpd_opp_table: opp-table {
1134 compatible = "operating-points-v2";
1137 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1141 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1145 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1149 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1153 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1157 opp-level = <224>;
1161 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1165 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1169 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1173 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1177 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1183 compatible = "qcom,bcm-voter";
1188 compatible = "qcom,sm8150-osm-l3";
1192 clock-names = "xo", "alternate";
1194 #interconnect-cells = <1>;
1198 compatible = "qcom,cpufreq-hw";
1201 reg-names = "freq-domain0", "freq-domain1",
1202 "freq-domain2";
1205 clock-names = "xo", "alternate";
1207 #freq-domain-cells = <1>;
1212 compatible = "arm,armv8-timer";
1219 thermal-zones {
1220 cpu0-thermal {
1221 polling-delay-passive = <250>;
1222 polling-delay = <1000>;
1224 thermal-sensors = <&tsens0 1>;
1227 cpu0_alert0: trip-point0 {
1233 cpu0_alert1: trip-point1 {
1246 cooling-maps {
1249 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1256 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1264 cpu1-thermal {
1265 polling-delay-passive = <250>;
1266 polling-delay = <1000>;
1268 thermal-sensors = <&tsens0 2>;
1271 cpu1_alert0: trip-point0 {
1277 cpu1_alert1: trip-point1 {
1290 cooling-maps {
1293 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1300 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1308 cpu2-thermal {
1309 polling-delay-passive = <250>;
1310 polling-delay = <1000>;
1312 thermal-sensors = <&tsens0 3>;
1315 cpu2_alert0: trip-point0 {
1321 cpu2_alert1: trip-point1 {
1334 cooling-maps {
1337 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1344 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1352 cpu3-thermal {
1353 polling-delay-passive = <250>;
1354 polling-delay = <1000>;
1356 thermal-sensors = <&tsens0 4>;
1359 cpu3_alert0: trip-point0 {
1365 cpu3_alert1: trip-point1 {
1378 cooling-maps {
1381 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1388 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1396 cpu4-top-thermal {
1397 polling-delay-passive = <250>;
1398 polling-delay = <1000>;
1400 thermal-sensors = <&tsens0 7>;
1403 cpu4_top_alert0: trip-point0 {
1409 cpu4_top_alert1: trip-point1 {
1422 cooling-maps {
1425 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1432 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1440 cpu5-top-thermal {
1441 polling-delay-passive = <250>;
1442 polling-delay = <1000>;
1444 thermal-sensors = <&tsens0 8>;
1447 cpu5_top_alert0: trip-point0 {
1453 cpu5_top_alert1: trip-point1 {
1466 cooling-maps {
1469 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1476 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1484 cpu6-top-thermal {
1485 polling-delay-passive = <250>;
1486 polling-delay = <1000>;
1488 thermal-sensors = <&tsens0 9>;
1491 cpu6_top_alert0: trip-point0 {
1497 cpu6_top_alert1: trip-point1 {
1510 cooling-maps {
1513 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1520 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1528 cpu7-top-thermal {
1529 polling-delay-passive = <250>;
1530 polling-delay = <1000>;
1532 thermal-sensors = <&tsens0 10>;
1535 cpu7_top_alert0: trip-point0 {
1541 cpu7_top_alert1: trip-point1 {
1554 cooling-maps {
1557 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1564 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1572 cpu4-bottom-thermal {
1573 polling-delay-passive = <250>;
1574 polling-delay = <1000>;
1576 thermal-sensors = <&tsens0 11>;
1579 cpu4_bottom_alert0: trip-point0 {
1585 cpu4_bottom_alert1: trip-point1 {
1598 cooling-maps {
1601 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1608 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1616 cpu5-bottom-thermal {
1617 polling-delay-passive = <250>;
1618 polling-delay = <1000>;
1620 thermal-sensors = <&tsens0 12>;
1623 cpu5_bottom_alert0: trip-point0 {
1629 cpu5_bottom_alert1: trip-point1 {
1642 cooling-maps {
1645 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1652 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1660 cpu6-bottom-thermal {
1661 polling-delay-passive = <250>;
1662 polling-delay = <1000>;
1664 thermal-sensors = <&tsens0 13>;
1667 cpu6_bottom_alert0: trip-point0 {
1673 cpu6_bottom_alert1: trip-point1 {
1686 cooling-maps {
1689 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1696 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1704 cpu7-bottom-thermal {
1705 polling-delay-passive = <250>;
1706 polling-delay = <1000>;
1708 thermal-sensors = <&tsens0 14>;
1711 cpu7_bottom_alert0: trip-point0 {
1717 cpu7_bottom_alert1: trip-point1 {
1730 cooling-maps {
1733 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1740 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1748 aoss0-thermal {
1749 polling-delay-passive = <250>;
1750 polling-delay = <1000>;
1752 thermal-sensors = <&tsens0 0>;
1755 aoss0_alert0: trip-point0 {
1763 cluster0-thermal {
1764 polling-delay-passive = <250>;
1765 polling-delay = <1000>;
1767 thermal-sensors = <&tsens0 5>;
1770 cluster0_alert0: trip-point0 {
1783 cluster1-thermal {
1784 polling-delay-passive = <250>;
1785 polling-delay = <1000>;
1787 thermal-sensors = <&tsens0 6>;
1790 cluster1_alert0: trip-point0 {
1803 gpu-thermal-top {
1804 polling-delay-passive = <250>;
1805 polling-delay = <1000>;
1807 thermal-sensors = <&tsens0 15>;
1810 gpu1_alert0: trip-point0 {
1818 aoss1-thermal {
1819 polling-delay-passive = <250>;
1820 polling-delay = <1000>;
1822 thermal-sensors = <&tsens1 0>;
1825 aoss1_alert0: trip-point0 {
1833 wlan-thermal {
1834 polling-delay-passive = <250>;
1835 polling-delay = <1000>;
1837 thermal-sensors = <&tsens1 1>;
1840 wlan_alert0: trip-point0 {
1848 video-thermal {
1849 polling-delay-passive = <250>;
1850 polling-delay = <1000>;
1852 thermal-sensors = <&tsens1 2>;
1855 video_alert0: trip-point0 {
1863 mem-thermal {
1864 polling-delay-passive = <250>;
1865 polling-delay = <1000>;
1867 thermal-sensors = <&tsens1 3>;
1870 mem_alert0: trip-point0 {
1878 q6-hvx-thermal {
1879 polling-delay-passive = <250>;
1880 polling-delay = <1000>;
1882 thermal-sensors = <&tsens1 4>;
1885 q6_hvx_alert0: trip-point0 {
1893 camera-thermal {
1894 polling-delay-passive = <250>;
1895 polling-delay = <1000>;
1897 thermal-sensors = <&tsens1 5>;
1900 camera_alert0: trip-point0 {
1908 compute-thermal {
1909 polling-delay-passive = <250>;
1910 polling-delay = <1000>;
1912 thermal-sensors = <&tsens1 6>;
1915 compute_alert0: trip-point0 {
1923 modem-thermal {
1924 polling-delay-passive = <250>;
1925 polling-delay = <1000>;
1927 thermal-sensors = <&tsens1 7>;
1930 modem_alert0: trip-point0 {
1938 npu-thermal {
1939 polling-delay-passive = <250>;
1940 polling-delay = <1000>;
1942 thermal-sensors = <&tsens1 8>;
1945 npu_alert0: trip-point0 {
1953 modem-vec-thermal {
1954 polling-delay-passive = <250>;
1955 polling-delay = <1000>;
1957 thermal-sensors = <&tsens1 9>;
1960 modem_vec_alert0: trip-point0 {
1968 modem-scl-thermal {
1969 polling-delay-passive = <250>;
1970 polling-delay = <1000>;
1972 thermal-sensors = <&tsens1 10>;
1975 modem_scl_alert0: trip-point0 {
1983 gpu-thermal-bottom {
1984 polling-delay-passive = <250>;
1985 polling-delay = <1000>;
1987 thermal-sensors = <&tsens1 11>;
1990 gpu2_alert0: trip-point0 {