Lines Matching +full:0 +full:xcd00
28 #clock-cells = <0>;
35 #clock-cells = <0>;
43 #size-cells = <0>;
45 CPU0: cpu@0 {
48 reg = <0x0 0x0>;
51 qcom,freq-domain = <&cpufreq_hw 0>;
65 reg = <0x0 0x100>;
68 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x200>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
94 reg = <0x0 0x300>;
97 qcom,freq-domain = <&cpufreq_hw 0>;
108 reg = <0x0 0x400>;
122 reg = <0x0 0x500>;
136 reg = <0x0 0x600>;
150 reg = <0x0 0x700>;
171 syscon = <&tcsr_mutex_regs 0 0x1000>;
178 reg = <0x0 0x80000000 0x0 0x0>;
197 reg = <0x0 0x85700000 0x0 0x600000>;
202 reg = <0x0 0x85d00000 0x0 0x140000>;
207 reg = <0x0 0x85f00000 0x0 0x20000>;
213 reg = <0x0 0x85f20000 0x0 0x20000>;
218 reg = <0x0 0x86000000 0x0 0x200000>;
223 reg = <0x0 0x86200000 0x0 0x3900000>;
229 reg = <0x0 0x89b00000 0x0 0x200000>;
237 reg = <0x0 0x8b700000 0x0 0x500000>;
242 reg = <0x0 0x8bc00000 0x0 0x180000>;
247 reg = <0x0 0x8bd80000 0x0 0x80000>;
252 reg = <0x0 0x8be00000 0x0 0x1a00000>;
257 reg = <0x0 0x8d800000 0x0 0x9600000>;
262 reg = <0x0 0x96e00000 0x0 0x500000>;
267 reg = <0x0 0x97300000 0x0 0x1400000>;
272 reg = <0x0 0x98700000 0x0 0x10000>;
277 reg = <0x0 0x98710000 0x0 0x5000>;
282 reg = <0x0 0x98715000 0x0 0x2000>;
287 reg = <0x0 0x98800000 0x0 0x100000>;
292 reg = <0x0 0x98900000 0x0 0x1400000>;
297 reg = <0x0 0x9e400000 0x0 0x1400000>;
316 qcom,local-pid = <0>;
340 qcom,local-pid = <0>;
364 qcom,local-pid = <0>;
388 qcom,local-pid = <0>;
404 soc: soc@0 {
407 ranges = <0 0 0 0 0x10 0>;
408 dma-ranges = <0 0 0 0 0x10 0>;
413 reg = <0x0 0x00100000 0x0 0x1f0000>;
425 reg = <0x0 0x00ac0000 0x0 0x6000>;
436 reg = <0x0 0x00a90000 0x0 0x4000>;
446 reg = <0 0x01500000 0 0x7400>;
453 reg = <0 0x01620000 0 0x19400>;
460 reg = <0 0x0163a000 0 0x1000>;
467 reg = <0 0x016e0000 0 0xd080>;
474 reg = <0 0x01700000 0 0x20000>;
481 reg = <0 0x01720000 0 0x7000>;
488 reg = <0 0x01740000 0 0x1c100>;
496 reg = <0 0x01d84000 0 0x2500>;
525 <0 0>,
526 <0 0>,
528 <0 0>,
529 <0 0>,
530 <0 0>,
531 <0 0>;
538 reg = <0 0x01d87000 0 0x1c0>;
547 resets = <&ufs_mem_hc 0>;
552 reg = <0 0x01d87400 0 0x108>,
553 <0 0x01d87600 0 0x1e0>,
554 <0 0x01d87c00 0 0x1dc>,
555 <0 0x01d87800 0 0x108>,
556 <0 0x01d87a00 0 0x1e0>;
557 #phy-cells = <0>;
563 reg = <0 0x01e00000 0 0x1000>;
570 reg = <0x0 0x01f40000 0x0 0x40000>;
575 reg = <0x0 0x02400000 0x0 0x4040>;
578 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
595 qcom,smem-states = <&slpi_smp2p_out 0>;
619 reg = <0 0x02c00000 0 0x40000>;
624 iommus = <&adreno_smmu 0 0x401>;
673 reg = <0 0x02c6a000 0 0x30000>,
674 <0 0x0b290000 0 0x10000>,
675 <0 0x0b490000 0 0x10000>;
693 iommus = <&adreno_smmu 5 0x400>;
709 reg = <0 0x02c90000 0 0x9000>;
723 reg = <0 0x02ca0000 0 0x10000>;
745 reg = <0x0 0x03100000 0x0 0x300000>,
746 <0x0 0x03500000 0x0 0x300000>,
747 <0x0 0x03900000 0x0 0x300000>,
748 <0x0 0x03D00000 0x0 0x300000>;
751 gpio-ranges = <&tlmm 0 0 175>;
760 reg = <0x0 0x04080000 0x0 0x4040>;
763 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
776 <&rpmhpd 0>;
781 qcom,smem-states = <&modem_smp2p_out 0>;
794 reg = <0x0 0x08300000 0x0 0x4040>;
797 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
813 qcom,smem-states = <&cdsp_smp2p_out 0>;
829 reg = <0 0x088e2000 0 0x400>;
831 #phy-cells = <0>;
841 reg = <0 0x088e9000 0 0x18c>,
842 <0 0x088e8000 0 0x10>;
861 reg = <0 0x088e9200 0 0x200>,
862 <0 0x088e9400 0 0x200>,
863 <0 0x088e9c00 0 0x218>,
864 <0 0x088e9600 0 0x200>,
865 <0 0x088e9800 0 0x200>,
866 <0 0x088e9a00 0 0x100>;
867 #phy-cells = <0>;
876 reg = <0 0x09160000 0 0x3200>;
883 reg = <0 0x09680000 0 0x3e200>;
890 reg = <0 0x0a6f8800 0 0x400>;
923 reg = <0 0x0a600000 0 0xcd00>;
934 reg = <0 0x0ac00000 0 0x1000>;
941 reg = <0x0 0x0c300000 0x0 0x100000>;
943 mboxes = <&apss_shared 0>;
945 #clock-cells = <0>;
951 reg = <0 0x0c263000 0 0x1ff>, /* TM */
952 <0 0x0c222000 0 0x1ff>; /* SROT */
962 reg = <0 0x0c265000 0 0x1ff>, /* TM */
963 <0 0x0c223000 0 0x1ff>; /* SROT */
973 reg = <0x0 0x0c440000 0x0 0x0001100>,
974 <0x0 0x0c600000 0x0 0x2000000>,
975 <0x0 0x0e600000 0x0 0x0100000>,
976 <0x0 0x0e700000 0x0 0x00a0000>,
977 <0x0 0x0c40a000 0x0 0x0026000>;
981 qcom,ee = <0>;
982 qcom,channel = <0>;
984 #size-cells = <0>;
987 cell-index = <0>;
992 reg = <0x0 0x17300000 0x0 0x4040>;
995 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1011 qcom,smem-states = <&adsp_smp2p_out 0>;
1028 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
1029 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
1035 reg = <0x0 0x17c00000 0x0 0x1000>;
1041 reg = <0 0x17c10000 0 0x1000>;
1050 reg = <0x0 0x17c20000 0x0 0x1000>;
1054 frame-number = <0>;
1057 reg = <0x0 0x17c21000 0x0 0x1000>,
1058 <0x0 0x17c22000 0x0 0x1000>;
1064 reg = <0x0 0x17c23000 0x0 0x1000>;
1071 reg = <0x0 0x17c25000 0x0 0x1000>;
1078 reg = <0x0 0x17c26000 0x0 0x1000>;
1085 reg = <0x0 0x17c29000 0x0 0x1000>;
1092 reg = <0x0 0x17c2b000 0x0 0x1000>;
1099 reg = <0x0 0x17c2d000 0x0 0x1000>;
1107 reg = <0x0 0x18200000 0x0 0x10000>,
1108 <0x0 0x18210000 0x0 0x10000>,
1109 <0x0 0x18220000 0x0 0x10000>;
1110 reg-names = "drv-0", "drv-1", "drv-2";
1114 qcom,tcs-offset = <0xd00>;
1119 <CONTROL_TCS 0>;
1189 reg = <0 0x18321000 0 0x1400>;
1199 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
1200 <0 0x18327800 0 0x1400>;
1216 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
1752 thermal-sensors = <&tsens0 0>;
1822 thermal-sensors = <&tsens1 0>;