Lines Matching +full:wcd9340 +full:- +full:gpio
1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
16 #include <dt-bindings/interconnect/qcom,sdm845.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/phy/phy-qcom-qusb2.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
21 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
22 #include <dt-bindings/soc/qcom,apr.h>
23 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
24 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
25 #include <dt-bindings/thermal/thermal.h>
28 interrupt-parent = <&intc>;
30 #address-cells = <2>;
31 #size-cells = <2>;
76 reserved-memory {
77 #address-cells = <2>;
78 #size-cells = <2>;
83 no-map;
88 no-map;
93 no-map;
97 compatible = "qcom,cmd-db";
99 no-map;
104 no-map;
109 no-map;
113 compatible = "qcom,rmtfs-mem";
115 no-map;
117 qcom,client-id = <1>;
123 no-map;
128 no-map;
133 no-map;
138 no-map;
143 no-map;
148 no-map;
153 no-map;
158 no-map;
163 no-map;
168 no-map;
173 no-map;
178 no-map;
183 no-map;
188 #address-cells = <2>;
189 #size-cells = <0>;
195 enable-method = "psci";
196 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
199 capacity-dmips-mhz = <607>;
200 dynamic-power-coefficient = <100>;
201 qcom,freq-domain = <&cpufreq_hw 0>;
202 operating-points-v2 = <&cpu0_opp_table>;
205 #cooling-cells = <2>;
206 next-level-cache = <&L2_0>;
207 L2_0: l2-cache {
209 next-level-cache = <&L3_0>;
210 L3_0: l3-cache {
220 enable-method = "psci";
221 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
224 capacity-dmips-mhz = <607>;
225 dynamic-power-coefficient = <100>;
226 qcom,freq-domain = <&cpufreq_hw 0>;
227 operating-points-v2 = <&cpu0_opp_table>;
230 #cooling-cells = <2>;
231 next-level-cache = <&L2_100>;
232 L2_100: l2-cache {
234 next-level-cache = <&L3_0>;
242 enable-method = "psci";
243 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
246 capacity-dmips-mhz = <607>;
247 dynamic-power-coefficient = <100>;
248 qcom,freq-domain = <&cpufreq_hw 0>;
249 operating-points-v2 = <&cpu0_opp_table>;
252 #cooling-cells = <2>;
253 next-level-cache = <&L2_200>;
254 L2_200: l2-cache {
256 next-level-cache = <&L3_0>;
264 enable-method = "psci";
265 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
268 capacity-dmips-mhz = <607>;
269 dynamic-power-coefficient = <100>;
270 qcom,freq-domain = <&cpufreq_hw 0>;
271 operating-points-v2 = <&cpu0_opp_table>;
274 #cooling-cells = <2>;
275 next-level-cache = <&L2_300>;
276 L2_300: l2-cache {
278 next-level-cache = <&L3_0>;
286 enable-method = "psci";
287 capacity-dmips-mhz = <1024>;
288 cpu-idle-states = <&BIG_CPU_SLEEP_0
291 dynamic-power-coefficient = <396>;
292 qcom,freq-domain = <&cpufreq_hw 1>;
293 operating-points-v2 = <&cpu4_opp_table>;
296 #cooling-cells = <2>;
297 next-level-cache = <&L2_400>;
298 L2_400: l2-cache {
300 next-level-cache = <&L3_0>;
308 enable-method = "psci";
309 capacity-dmips-mhz = <1024>;
310 cpu-idle-states = <&BIG_CPU_SLEEP_0
313 dynamic-power-coefficient = <396>;
314 qcom,freq-domain = <&cpufreq_hw 1>;
315 operating-points-v2 = <&cpu4_opp_table>;
318 #cooling-cells = <2>;
319 next-level-cache = <&L2_500>;
320 L2_500: l2-cache {
322 next-level-cache = <&L3_0>;
330 enable-method = "psci";
331 capacity-dmips-mhz = <1024>;
332 cpu-idle-states = <&BIG_CPU_SLEEP_0
335 dynamic-power-coefficient = <396>;
336 qcom,freq-domain = <&cpufreq_hw 1>;
337 operating-points-v2 = <&cpu4_opp_table>;
340 #cooling-cells = <2>;
341 next-level-cache = <&L2_600>;
342 L2_600: l2-cache {
344 next-level-cache = <&L3_0>;
352 enable-method = "psci";
353 capacity-dmips-mhz = <1024>;
354 cpu-idle-states = <&BIG_CPU_SLEEP_0
357 dynamic-power-coefficient = <396>;
358 qcom,freq-domain = <&cpufreq_hw 1>;
359 operating-points-v2 = <&cpu4_opp_table>;
362 #cooling-cells = <2>;
363 next-level-cache = <&L2_700>;
364 L2_700: l2-cache {
366 next-level-cache = <&L3_0>;
370 cpu-map {
406 idle-states {
407 entry-method = "psci";
409 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
410 compatible = "arm,idle-state";
411 idle-state-name = "little-power-down";
412 arm,psci-suspend-param = <0x40000003>;
413 entry-latency-us = <350>;
414 exit-latency-us = <461>;
415 min-residency-us = <1890>;
416 local-timer-stop;
419 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
420 compatible = "arm,idle-state";
421 idle-state-name = "little-rail-power-down";
422 arm,psci-suspend-param = <0x40000004>;
423 entry-latency-us = <360>;
424 exit-latency-us = <531>;
425 min-residency-us = <3934>;
426 local-timer-stop;
429 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
430 compatible = "arm,idle-state";
431 idle-state-name = "big-power-down";
432 arm,psci-suspend-param = <0x40000003>;
433 entry-latency-us = <264>;
434 exit-latency-us = <621>;
435 min-residency-us = <952>;
436 local-timer-stop;
439 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
440 compatible = "arm,idle-state";
441 idle-state-name = "big-rail-power-down";
442 arm,psci-suspend-param = <0x40000004>;
443 entry-latency-us = <702>;
444 exit-latency-us = <1061>;
445 min-residency-us = <4488>;
446 local-timer-stop;
449 CLUSTER_SLEEP_0: cluster-sleep-0 {
450 compatible = "arm,idle-state";
451 idle-state-name = "cluster-power-down";
452 arm,psci-suspend-param = <0x400000F4>;
453 entry-latency-us = <3263>;
454 exit-latency-us = <6562>;
455 min-residency-us = <9987>;
456 local-timer-stop;
462 compatible = "operating-points-v2";
463 opp-shared;
465 cpu0_opp1: opp-300000000 {
466 opp-hz = /bits/ 64 <300000000>;
467 opp-peak-kBps = <800000 4800000>;
470 cpu0_opp2: opp-403200000 {
471 opp-hz = /bits/ 64 <403200000>;
472 opp-peak-kBps = <800000 4800000>;
475 cpu0_opp3: opp-480000000 {
476 opp-hz = /bits/ 64 <480000000>;
477 opp-peak-kBps = <800000 6451200>;
480 cpu0_opp4: opp-576000000 {
481 opp-hz = /bits/ 64 <576000000>;
482 opp-peak-kBps = <800000 6451200>;
485 cpu0_opp5: opp-652800000 {
486 opp-hz = /bits/ 64 <652800000>;
487 opp-peak-kBps = <800000 7680000>;
490 cpu0_opp6: opp-748800000 {
491 opp-hz = /bits/ 64 <748800000>;
492 opp-peak-kBps = <1804000 9216000>;
495 cpu0_opp7: opp-825600000 {
496 opp-hz = /bits/ 64 <825600000>;
497 opp-peak-kBps = <1804000 9216000>;
500 cpu0_opp8: opp-902400000 {
501 opp-hz = /bits/ 64 <902400000>;
502 opp-peak-kBps = <1804000 10444800>;
505 cpu0_opp9: opp-979200000 {
506 opp-hz = /bits/ 64 <979200000>;
507 opp-peak-kBps = <1804000 11980800>;
510 cpu0_opp10: opp-1056000000 {
511 opp-hz = /bits/ 64 <1056000000>;
512 opp-peak-kBps = <1804000 11980800>;
515 cpu0_opp11: opp-1132800000 {
516 opp-hz = /bits/ 64 <1132800000>;
517 opp-peak-kBps = <2188000 13516800>;
520 cpu0_opp12: opp-1228800000 {
521 opp-hz = /bits/ 64 <1228800000>;
522 opp-peak-kBps = <2188000 15052800>;
525 cpu0_opp13: opp-1324800000 {
526 opp-hz = /bits/ 64 <1324800000>;
527 opp-peak-kBps = <2188000 16588800>;
530 cpu0_opp14: opp-1420800000 {
531 opp-hz = /bits/ 64 <1420800000>;
532 opp-peak-kBps = <3072000 18124800>;
535 cpu0_opp15: opp-1516800000 {
536 opp-hz = /bits/ 64 <1516800000>;
537 opp-peak-kBps = <3072000 19353600>;
540 cpu0_opp16: opp-1612800000 {
541 opp-hz = /bits/ 64 <1612800000>;
542 opp-peak-kBps = <4068000 19353600>;
545 cpu0_opp17: opp-1689600000 {
546 opp-hz = /bits/ 64 <1689600000>;
547 opp-peak-kBps = <4068000 20889600>;
550 cpu0_opp18: opp-1766400000 {
551 opp-hz = /bits/ 64 <1766400000>;
552 opp-peak-kBps = <4068000 22425600>;
557 compatible = "operating-points-v2";
558 opp-shared;
560 cpu4_opp1: opp-300000000 {
561 opp-hz = /bits/ 64 <300000000>;
562 opp-peak-kBps = <800000 4800000>;
565 cpu4_opp2: opp-403200000 {
566 opp-hz = /bits/ 64 <403200000>;
567 opp-peak-kBps = <800000 4800000>;
570 cpu4_opp3: opp-480000000 {
571 opp-hz = /bits/ 64 <480000000>;
572 opp-peak-kBps = <1804000 4800000>;
575 cpu4_opp4: opp-576000000 {
576 opp-hz = /bits/ 64 <576000000>;
577 opp-peak-kBps = <1804000 4800000>;
580 cpu4_opp5: opp-652800000 {
581 opp-hz = /bits/ 64 <652800000>;
582 opp-peak-kBps = <1804000 4800000>;
585 cpu4_opp6: opp-748800000 {
586 opp-hz = /bits/ 64 <748800000>;
587 opp-peak-kBps = <1804000 4800000>;
590 cpu4_opp7: opp-825600000 {
591 opp-hz = /bits/ 64 <825600000>;
592 opp-peak-kBps = <2188000 9216000>;
595 cpu4_opp8: opp-902400000 {
596 opp-hz = /bits/ 64 <902400000>;
597 opp-peak-kBps = <2188000 9216000>;
600 cpu4_opp9: opp-979200000 {
601 opp-hz = /bits/ 64 <979200000>;
602 opp-peak-kBps = <2188000 9216000>;
605 cpu4_opp10: opp-1056000000 {
606 opp-hz = /bits/ 64 <1056000000>;
607 opp-peak-kBps = <3072000 9216000>;
610 cpu4_opp11: opp-1132800000 {
611 opp-hz = /bits/ 64 <1132800000>;
612 opp-peak-kBps = <3072000 11980800>;
615 cpu4_opp12: opp-1209600000 {
616 opp-hz = /bits/ 64 <1209600000>;
617 opp-peak-kBps = <4068000 11980800>;
620 cpu4_opp13: opp-1286400000 {
621 opp-hz = /bits/ 64 <1286400000>;
622 opp-peak-kBps = <4068000 11980800>;
625 cpu4_opp14: opp-1363200000 {
626 opp-hz = /bits/ 64 <1363200000>;
627 opp-peak-kBps = <4068000 15052800>;
630 cpu4_opp15: opp-1459200000 {
631 opp-hz = /bits/ 64 <1459200000>;
632 opp-peak-kBps = <4068000 15052800>;
635 cpu4_opp16: opp-1536000000 {
636 opp-hz = /bits/ 64 <1536000000>;
637 opp-peak-kBps = <5412000 15052800>;
640 cpu4_opp17: opp-1612800000 {
641 opp-hz = /bits/ 64 <1612800000>;
642 opp-peak-kBps = <5412000 15052800>;
645 cpu4_opp18: opp-1689600000 {
646 opp-hz = /bits/ 64 <1689600000>;
647 opp-peak-kBps = <5412000 19353600>;
650 cpu4_opp19: opp-1766400000 {
651 opp-hz = /bits/ 64 <1766400000>;
652 opp-peak-kBps = <6220000 19353600>;
655 cpu4_opp20: opp-1843200000 {
656 opp-hz = /bits/ 64 <1843200000>;
657 opp-peak-kBps = <6220000 19353600>;
660 cpu4_opp21: opp-1920000000 {
661 opp-hz = /bits/ 64 <1920000000>;
662 opp-peak-kBps = <7216000 19353600>;
665 cpu4_opp22: opp-1996800000 {
666 opp-hz = /bits/ 64 <1996800000>;
667 opp-peak-kBps = <7216000 20889600>;
670 cpu4_opp23: opp-2092800000 {
671 opp-hz = /bits/ 64 <2092800000>;
672 opp-peak-kBps = <7216000 20889600>;
675 cpu4_opp24: opp-2169600000 {
676 opp-hz = /bits/ 64 <2169600000>;
677 opp-peak-kBps = <7216000 20889600>;
680 cpu4_opp25: opp-2246400000 {
681 opp-hz = /bits/ 64 <2246400000>;
682 opp-peak-kBps = <7216000 20889600>;
685 cpu4_opp26: opp-2323200000 {
686 opp-hz = /bits/ 64 <2323200000>;
687 opp-peak-kBps = <7216000 20889600>;
690 cpu4_opp27: opp-2400000000 {
691 opp-hz = /bits/ 64 <2400000000>;
692 opp-peak-kBps = <7216000 22425600>;
695 cpu4_opp28: opp-2476800000 {
696 opp-hz = /bits/ 64 <2476800000>;
697 opp-peak-kBps = <7216000 22425600>;
700 cpu4_opp29: opp-2553600000 {
701 opp-hz = /bits/ 64 <2553600000>;
702 opp-peak-kBps = <7216000 22425600>;
705 cpu4_opp30: opp-2649600000 {
706 opp-hz = /bits/ 64 <2649600000>;
707 opp-peak-kBps = <7216000 22425600>;
710 cpu4_opp31: opp-2745600000 {
711 opp-hz = /bits/ 64 <2745600000>;
712 opp-peak-kBps = <7216000 25497600>;
715 cpu4_opp32: opp-2803200000 {
716 opp-hz = /bits/ 64 <2803200000>;
717 opp-peak-kBps = <7216000 25497600>;
722 compatible = "arm,armv8-pmuv3";
727 compatible = "arm,armv8-timer";
735 xo_board: xo-board {
736 compatible = "fixed-clock";
737 #clock-cells = <0>;
738 clock-frequency = <38400000>;
739 clock-output-names = "xo_board";
742 sleep_clk: sleep-clk {
743 compatible = "fixed-clock";
744 #clock-cells = <0>;
745 clock-frequency = <32764>;
751 compatible = "qcom,scm-sdm845", "qcom,scm";
755 adsp_pas: remoteproc-adsp {
756 compatible = "qcom,sdm845-adsp-pas";
758 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
763 interrupt-names = "wdog", "fatal", "ready",
764 "handover", "stop-ack";
767 clock-names = "xo";
769 memory-region = <&adsp_mem>;
771 qcom,smem-states = <&adsp_smp2p_out 0>;
772 qcom,smem-state-names = "stop";
776 glink-edge {
779 qcom,remote-pid = <2>;
783 compatible = "qcom,apr-v2";
784 qcom,glink-channels = "apr_audio_svc";
785 qcom,apr-domain = <APR_DOMAIN_ADSP>;
786 #address-cells = <1>;
787 #size-cells = <0>;
790 apr-service@3 {
793 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
796 q6afe: apr-service@4 {
799 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
801 compatible = "qcom,q6afe-dais";
802 #address-cells = <1>;
803 #size-cells = <0>;
804 #sound-dai-cells = <1>;
808 q6asm: apr-service@7 {
811 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
813 compatible = "qcom,q6asm-dais";
814 #address-cells = <1>;
815 #size-cells = <0>;
816 #sound-dai-cells = <1>;
821 q6adm: apr-service@8 {
824 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
826 compatible = "qcom,q6adm-routing";
827 #sound-dai-cells = <0>;
834 qcom,glink-channels = "fastrpcglink-apps-dsp";
836 #address-cells = <1>;
837 #size-cells = <0>;
839 compute-cb@3 {
840 compatible = "qcom,fastrpc-compute-cb";
845 compute-cb@4 {
846 compatible = "qcom,fastrpc-compute-cb";
854 cdsp_pas: remoteproc-cdsp {
855 compatible = "qcom,sdm845-cdsp-pas";
857 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
862 interrupt-names = "wdog", "fatal", "ready",
863 "handover", "stop-ack";
866 clock-names = "xo";
868 memory-region = <&cdsp_mem>;
870 qcom,smem-states = <&cdsp_smp2p_out 0>;
871 qcom,smem-state-names = "stop";
875 glink-edge {
878 qcom,remote-pid = <5>;
882 qcom,glink-channels = "fastrpcglink-apps-dsp";
884 #address-cells = <1>;
885 #size-cells = <0>;
887 compute-cb@1 {
888 compatible = "qcom,fastrpc-compute-cb";
893 compute-cb@2 {
894 compatible = "qcom,fastrpc-compute-cb";
899 compute-cb@3 {
900 compatible = "qcom,fastrpc-compute-cb";
905 compute-cb@4 {
906 compatible = "qcom,fastrpc-compute-cb";
911 compute-cb@5 {
912 compatible = "qcom,fastrpc-compute-cb";
917 compute-cb@6 {
918 compatible = "qcom,fastrpc-compute-cb";
923 compute-cb@7 {
924 compatible = "qcom,fastrpc-compute-cb";
929 compute-cb@8 {
930 compatible = "qcom,fastrpc-compute-cb";
939 compatible = "qcom,tcsr-mutex";
941 #hwlock-cells = <1>;
946 memory-region = <&smem_mem>;
950 smp2p-cdsp {
958 qcom,local-pid = <0>;
959 qcom,remote-pid = <5>;
961 cdsp_smp2p_out: master-kernel {
962 qcom,entry-name = "master-kernel";
963 #qcom,smem-state-cells = <1>;
966 cdsp_smp2p_in: slave-kernel {
967 qcom,entry-name = "slave-kernel";
969 interrupt-controller;
970 #interrupt-cells = <2>;
974 smp2p-lpass {
982 qcom,local-pid = <0>;
983 qcom,remote-pid = <2>;
985 adsp_smp2p_out: master-kernel {
986 qcom,entry-name = "master-kernel";
987 #qcom,smem-state-cells = <1>;
990 adsp_smp2p_in: slave-kernel {
991 qcom,entry-name = "slave-kernel";
993 interrupt-controller;
994 #interrupt-cells = <2>;
998 smp2p-mpss {
1003 qcom,local-pid = <0>;
1004 qcom,remote-pid = <1>;
1006 modem_smp2p_out: master-kernel {
1007 qcom,entry-name = "master-kernel";
1008 #qcom,smem-state-cells = <1>;
1011 modem_smp2p_in: slave-kernel {
1012 qcom,entry-name = "slave-kernel";
1013 interrupt-controller;
1014 #interrupt-cells = <2>;
1017 ipa_smp2p_out: ipa-ap-to-modem {
1018 qcom,entry-name = "ipa";
1019 #qcom,smem-state-cells = <1>;
1022 ipa_smp2p_in: ipa-modem-to-ap {
1023 qcom,entry-name = "ipa";
1024 interrupt-controller;
1025 #interrupt-cells = <2>;
1029 smp2p-slpi {
1034 qcom,local-pid = <0>;
1035 qcom,remote-pid = <3>;
1037 slpi_smp2p_out: master-kernel {
1038 qcom,entry-name = "master-kernel";
1039 #qcom,smem-state-cells = <1>;
1042 slpi_smp2p_in: slave-kernel {
1043 qcom,entry-name = "slave-kernel";
1044 interrupt-controller;
1045 #interrupt-cells = <2>;
1050 compatible = "arm,psci-1.0";
1055 #address-cells = <2>;
1056 #size-cells = <2>;
1058 dma-ranges = <0 0 0 0 0x10 0>;
1059 compatible = "simple-bus";
1061 gcc: clock-controller@100000 {
1062 compatible = "qcom,gcc-sdm845";
1064 #clock-cells = <1>;
1065 #reset-cells = <1>;
1066 #power-domain-cells = <1>;
1072 #address-cells = <1>;
1073 #size-cells = <1>;
1075 qusb2p_hstx_trim: hstx-trim-primary@1eb {
1080 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1087 compatible = "qcom,prng-ee";
1090 clock-names = "core";
1093 qup_opp_table: qup-opp-table {
1094 compatible = "operating-points-v2";
1096 opp-50000000 {
1097 opp-hz = /bits/ 64 <50000000>;
1098 required-opps = <&rpmhpd_opp_min_svs>;
1101 opp-75000000 {
1102 opp-hz = /bits/ 64 <75000000>;
1103 required-opps = <&rpmhpd_opp_low_svs>;
1106 opp-100000000 {
1107 opp-hz = /bits/ 64 <100000000>;
1108 required-opps = <&rpmhpd_opp_svs>;
1111 opp-128000000 {
1112 opp-hz = /bits/ 64 <128000000>;
1113 required-opps = <&rpmhpd_opp_nom>;
1118 compatible = "qcom,geni-se-qup";
1120 clock-names = "m-ahb", "s-ahb";
1123 #address-cells = <2>;
1124 #size-cells = <2>;
1129 compatible = "qcom,geni-i2c";
1131 clock-names = "se";
1133 pinctrl-names = "default";
1134 pinctrl-0 = <&qup_i2c0_default>;
1136 #address-cells = <1>;
1137 #size-cells = <0>;
1138 power-domains = <&rpmhpd SDM845_CX>;
1139 operating-points-v2 = <&qup_opp_table>;
1144 compatible = "qcom,geni-spi";
1146 clock-names = "se";
1148 pinctrl-names = "default";
1149 pinctrl-0 = <&qup_spi0_default>;
1151 #address-cells = <1>;
1152 #size-cells = <0>;
1157 compatible = "qcom,geni-uart";
1159 clock-names = "se";
1161 pinctrl-names = "default";
1162 pinctrl-0 = <&qup_uart0_default>;
1164 power-domains = <&rpmhpd SDM845_CX>;
1165 operating-points-v2 = <&qup_opp_table>;
1170 compatible = "qcom,geni-i2c";
1172 clock-names = "se";
1174 pinctrl-names = "default";
1175 pinctrl-0 = <&qup_i2c1_default>;
1177 #address-cells = <1>;
1178 #size-cells = <0>;
1179 power-domains = <&rpmhpd SDM845_CX>;
1180 operating-points-v2 = <&qup_opp_table>;
1185 compatible = "qcom,geni-spi";
1187 clock-names = "se";
1189 pinctrl-names = "default";
1190 pinctrl-0 = <&qup_spi1_default>;
1192 #address-cells = <1>;
1193 #size-cells = <0>;
1198 compatible = "qcom,geni-uart";
1200 clock-names = "se";
1202 pinctrl-names = "default";
1203 pinctrl-0 = <&qup_uart1_default>;
1205 power-domains = <&rpmhpd SDM845_CX>;
1206 operating-points-v2 = <&qup_opp_table>;
1211 compatible = "qcom,geni-i2c";
1213 clock-names = "se";
1215 pinctrl-names = "default";
1216 pinctrl-0 = <&qup_i2c2_default>;
1218 #address-cells = <1>;
1219 #size-cells = <0>;
1220 power-domains = <&rpmhpd SDM845_CX>;
1221 operating-points-v2 = <&qup_opp_table>;
1226 compatible = "qcom,geni-spi";
1228 clock-names = "se";
1230 pinctrl-names = "default";
1231 pinctrl-0 = <&qup_spi2_default>;
1233 #address-cells = <1>;
1234 #size-cells = <0>;
1239 compatible = "qcom,geni-uart";
1241 clock-names = "se";
1243 pinctrl-names = "default";
1244 pinctrl-0 = <&qup_uart2_default>;
1246 power-domains = <&rpmhpd SDM845_CX>;
1247 operating-points-v2 = <&qup_opp_table>;
1252 compatible = "qcom,geni-i2c";
1254 clock-names = "se";
1256 pinctrl-names = "default";
1257 pinctrl-0 = <&qup_i2c3_default>;
1259 #address-cells = <1>;
1260 #size-cells = <0>;
1261 power-domains = <&rpmhpd SDM845_CX>;
1262 operating-points-v2 = <&qup_opp_table>;
1267 compatible = "qcom,geni-spi";
1269 clock-names = "se";
1271 pinctrl-names = "default";
1272 pinctrl-0 = <&qup_spi3_default>;
1274 #address-cells = <1>;
1275 #size-cells = <0>;
1280 compatible = "qcom,geni-uart";
1282 clock-names = "se";
1284 pinctrl-names = "default";
1285 pinctrl-0 = <&qup_uart3_default>;
1287 power-domains = <&rpmhpd SDM845_CX>;
1288 operating-points-v2 = <&qup_opp_table>;
1293 compatible = "qcom,geni-i2c";
1295 clock-names = "se";
1297 pinctrl-names = "default";
1298 pinctrl-0 = <&qup_i2c4_default>;
1300 #address-cells = <1>;
1301 #size-cells = <0>;
1302 power-domains = <&rpmhpd SDM845_CX>;
1303 operating-points-v2 = <&qup_opp_table>;
1308 compatible = "qcom,geni-spi";
1310 clock-names = "se";
1312 pinctrl-names = "default";
1313 pinctrl-0 = <&qup_spi4_default>;
1315 #address-cells = <1>;
1316 #size-cells = <0>;
1321 compatible = "qcom,geni-uart";
1323 clock-names = "se";
1325 pinctrl-names = "default";
1326 pinctrl-0 = <&qup_uart4_default>;
1328 power-domains = <&rpmhpd SDM845_CX>;
1329 operating-points-v2 = <&qup_opp_table>;
1334 compatible = "qcom,geni-i2c";
1336 clock-names = "se";
1338 pinctrl-names = "default";
1339 pinctrl-0 = <&qup_i2c5_default>;
1341 #address-cells = <1>;
1342 #size-cells = <0>;
1343 power-domains = <&rpmhpd SDM845_CX>;
1344 operating-points-v2 = <&qup_opp_table>;
1349 compatible = "qcom,geni-spi";
1351 clock-names = "se";
1353 pinctrl-names = "default";
1354 pinctrl-0 = <&qup_spi5_default>;
1356 #address-cells = <1>;
1357 #size-cells = <0>;
1362 compatible = "qcom,geni-uart";
1364 clock-names = "se";
1366 pinctrl-names = "default";
1367 pinctrl-0 = <&qup_uart5_default>;
1369 power-domains = <&rpmhpd SDM845_CX>;
1370 operating-points-v2 = <&qup_opp_table>;
1375 compatible = "qcom,geni-i2c";
1377 clock-names = "se";
1379 pinctrl-names = "default";
1380 pinctrl-0 = <&qup_i2c6_default>;
1382 #address-cells = <1>;
1383 #size-cells = <0>;
1384 power-domains = <&rpmhpd SDM845_CX>;
1385 operating-points-v2 = <&qup_opp_table>;
1390 compatible = "qcom,geni-spi";
1392 clock-names = "se";
1394 pinctrl-names = "default";
1395 pinctrl-0 = <&qup_spi6_default>;
1397 #address-cells = <1>;
1398 #size-cells = <0>;
1403 compatible = "qcom,geni-uart";
1405 clock-names = "se";
1407 pinctrl-names = "default";
1408 pinctrl-0 = <&qup_uart6_default>;
1410 power-domains = <&rpmhpd SDM845_CX>;
1411 operating-points-v2 = <&qup_opp_table>;
1416 compatible = "qcom,geni-i2c";
1418 clock-names = "se";
1420 pinctrl-names = "default";
1421 pinctrl-0 = <&qup_i2c7_default>;
1423 #address-cells = <1>;
1424 #size-cells = <0>;
1425 power-domains = <&rpmhpd SDM845_CX>;
1426 operating-points-v2 = <&qup_opp_table>;
1431 compatible = "qcom,geni-spi";
1433 clock-names = "se";
1435 pinctrl-names = "default";
1436 pinctrl-0 = <&qup_spi7_default>;
1438 #address-cells = <1>;
1439 #size-cells = <0>;
1444 compatible = "qcom,geni-uart";
1446 clock-names = "se";
1448 pinctrl-names = "default";
1449 pinctrl-0 = <&qup_uart7_default>;
1451 power-domains = <&rpmhpd SDM845_CX>;
1452 operating-points-v2 = <&qup_opp_table>;
1458 compatible = "qcom,geni-se-qup";
1460 clock-names = "m-ahb", "s-ahb";
1463 #address-cells = <2>;
1464 #size-cells = <2>;
1469 compatible = "qcom,geni-i2c";
1471 clock-names = "se";
1473 pinctrl-names = "default";
1474 pinctrl-0 = <&qup_i2c8_default>;
1476 #address-cells = <1>;
1477 #size-cells = <0>;
1478 power-domains = <&rpmhpd SDM845_CX>;
1479 operating-points-v2 = <&qup_opp_table>;
1484 compatible = "qcom,geni-spi";
1486 clock-names = "se";
1488 pinctrl-names = "default";
1489 pinctrl-0 = <&qup_spi8_default>;
1491 #address-cells = <1>;
1492 #size-cells = <0>;
1497 compatible = "qcom,geni-uart";
1499 clock-names = "se";
1501 pinctrl-names = "default";
1502 pinctrl-0 = <&qup_uart8_default>;
1504 power-domains = <&rpmhpd SDM845_CX>;
1505 operating-points-v2 = <&qup_opp_table>;
1510 compatible = "qcom,geni-i2c";
1512 clock-names = "se";
1514 pinctrl-names = "default";
1515 pinctrl-0 = <&qup_i2c9_default>;
1517 #address-cells = <1>;
1518 #size-cells = <0>;
1519 power-domains = <&rpmhpd SDM845_CX>;
1520 operating-points-v2 = <&qup_opp_table>;
1525 compatible = "qcom,geni-spi";
1527 clock-names = "se";
1529 pinctrl-names = "default";
1530 pinctrl-0 = <&qup_spi9_default>;
1532 #address-cells = <1>;
1533 #size-cells = <0>;
1538 compatible = "qcom,geni-debug-uart";
1540 clock-names = "se";
1542 pinctrl-names = "default";
1543 pinctrl-0 = <&qup_uart9_default>;
1545 power-domains = <&rpmhpd SDM845_CX>;
1546 operating-points-v2 = <&qup_opp_table>;
1551 compatible = "qcom,geni-i2c";
1553 clock-names = "se";
1555 pinctrl-names = "default";
1556 pinctrl-0 = <&qup_i2c10_default>;
1558 #address-cells = <1>;
1559 #size-cells = <0>;
1560 power-domains = <&rpmhpd SDM845_CX>;
1561 operating-points-v2 = <&qup_opp_table>;
1566 compatible = "qcom,geni-spi";
1568 clock-names = "se";
1570 pinctrl-names = "default";
1571 pinctrl-0 = <&qup_spi10_default>;
1573 #address-cells = <1>;
1574 #size-cells = <0>;
1579 compatible = "qcom,geni-uart";
1581 clock-names = "se";
1583 pinctrl-names = "default";
1584 pinctrl-0 = <&qup_uart10_default>;
1586 power-domains = <&rpmhpd SDM845_CX>;
1587 operating-points-v2 = <&qup_opp_table>;
1592 compatible = "qcom,geni-i2c";
1594 clock-names = "se";
1596 pinctrl-names = "default";
1597 pinctrl-0 = <&qup_i2c11_default>;
1599 #address-cells = <1>;
1600 #size-cells = <0>;
1601 power-domains = <&rpmhpd SDM845_CX>;
1602 operating-points-v2 = <&qup_opp_table>;
1607 compatible = "qcom,geni-spi";
1609 clock-names = "se";
1611 pinctrl-names = "default";
1612 pinctrl-0 = <&qup_spi11_default>;
1614 #address-cells = <1>;
1615 #size-cells = <0>;
1620 compatible = "qcom,geni-uart";
1622 clock-names = "se";
1624 pinctrl-names = "default";
1625 pinctrl-0 = <&qup_uart11_default>;
1627 power-domains = <&rpmhpd SDM845_CX>;
1628 operating-points-v2 = <&qup_opp_table>;
1633 compatible = "qcom,geni-i2c";
1635 clock-names = "se";
1637 pinctrl-names = "default";
1638 pinctrl-0 = <&qup_i2c12_default>;
1640 #address-cells = <1>;
1641 #size-cells = <0>;
1642 power-domains = <&rpmhpd SDM845_CX>;
1643 operating-points-v2 = <&qup_opp_table>;
1648 compatible = "qcom,geni-spi";
1650 clock-names = "se";
1652 pinctrl-names = "default";
1653 pinctrl-0 = <&qup_spi12_default>;
1655 #address-cells = <1>;
1656 #size-cells = <0>;
1661 compatible = "qcom,geni-uart";
1663 clock-names = "se";
1665 pinctrl-names = "default";
1666 pinctrl-0 = <&qup_uart12_default>;
1668 power-domains = <&rpmhpd SDM845_CX>;
1669 operating-points-v2 = <&qup_opp_table>;
1674 compatible = "qcom,geni-i2c";
1676 clock-names = "se";
1678 pinctrl-names = "default";
1679 pinctrl-0 = <&qup_i2c13_default>;
1681 #address-cells = <1>;
1682 #size-cells = <0>;
1683 power-domains = <&rpmhpd SDM845_CX>;
1684 operating-points-v2 = <&qup_opp_table>;
1689 compatible = "qcom,geni-spi";
1691 clock-names = "se";
1693 pinctrl-names = "default";
1694 pinctrl-0 = <&qup_spi13_default>;
1696 #address-cells = <1>;
1697 #size-cells = <0>;
1702 compatible = "qcom,geni-uart";
1704 clock-names = "se";
1706 pinctrl-names = "default";
1707 pinctrl-0 = <&qup_uart13_default>;
1709 power-domains = <&rpmhpd SDM845_CX>;
1710 operating-points-v2 = <&qup_opp_table>;
1715 compatible = "qcom,geni-i2c";
1717 clock-names = "se";
1719 pinctrl-names = "default";
1720 pinctrl-0 = <&qup_i2c14_default>;
1722 #address-cells = <1>;
1723 #size-cells = <0>;
1724 power-domains = <&rpmhpd SDM845_CX>;
1725 operating-points-v2 = <&qup_opp_table>;
1730 compatible = "qcom,geni-spi";
1732 clock-names = "se";
1734 pinctrl-names = "default";
1735 pinctrl-0 = <&qup_spi14_default>;
1737 #address-cells = <1>;
1738 #size-cells = <0>;
1743 compatible = "qcom,geni-uart";
1745 clock-names = "se";
1747 pinctrl-names = "default";
1748 pinctrl-0 = <&qup_uart14_default>;
1750 power-domains = <&rpmhpd SDM845_CX>;
1751 operating-points-v2 = <&qup_opp_table>;
1756 compatible = "qcom,geni-i2c";
1758 clock-names = "se";
1760 pinctrl-names = "default";
1761 pinctrl-0 = <&qup_i2c15_default>;
1763 #address-cells = <1>;
1764 #size-cells = <0>;
1765 power-domains = <&rpmhpd SDM845_CX>;
1766 operating-points-v2 = <&qup_opp_table>;
1771 compatible = "qcom,geni-spi";
1773 clock-names = "se";
1775 pinctrl-names = "default";
1776 pinctrl-0 = <&qup_spi15_default>;
1778 #address-cells = <1>;
1779 #size-cells = <0>;
1784 compatible = "qcom,geni-uart";
1786 clock-names = "se";
1788 pinctrl-names = "default";
1789 pinctrl-0 = <&qup_uart15_default>;
1791 power-domains = <&rpmhpd SDM845_CX>;
1792 operating-points-v2 = <&qup_opp_table>;
1797 system-cache-controller@1100000 {
1798 compatible = "qcom,sdm845-llcc";
1800 reg-names = "llcc_base", "llcc_broadcast_base";
1805 compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
1810 reg-names = "parf", "dbi", "elbi", "config";
1812 linux,pci-domain = <0>;
1813 bus-range = <0x00 0xff>;
1814 num-lanes = <1>;
1816 #address-cells = <3>;
1817 #size-cells = <2>;
1823 interrupt-names = "msi";
1824 #interrupt-cells = <1>;
1825 interrupt-map-mask = <0 0 0 0x7>;
1826 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1838 clock-names = "pipe",
1847 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
1865 reset-names = "pci";
1867 power-domains = <&gcc PCIE_0_GDSC>;
1870 phy-names = "pciephy";
1876 compatible = "qcom,sdm845-qmp-pcie-phy";
1878 #address-cells = <2>;
1879 #size-cells = <2>;
1885 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1888 reset-names = "phy";
1890 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
1891 assigned-clock-rates = <100000000>;
1901 clock-names = "pipe0";
1903 #phy-cells = <0>;
1904 clock-output-names = "pcie_0_pipe_clk";
1909 compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
1914 reg-names = "parf", "dbi", "elbi", "config";
1916 linux,pci-domain = <1>;
1917 bus-range = <0x00 0xff>;
1918 num-lanes = <1>;
1920 #address-cells = <3>;
1921 #size-cells = <2>;
1927 interrupt-names = "msi";
1928 #interrupt-cells = <1>;
1929 interrupt-map-mask = <0 0 0 0x7>;
1930 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1943 clock-names = "pipe",
1952 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1953 assigned-clock-rates = <19200000>;
1956 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1974 reset-names = "pci";
1976 power-domains = <&gcc PCIE_1_GDSC>;
1979 phy-names = "pciephy";
1985 compatible = "qcom,sdm845-qhp-pcie-phy";
1987 #address-cells = <2>;
1988 #size-cells = <2>;
1994 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1997 reset-names = "phy";
1999 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2000 assigned-clock-rates = <100000000>;
2009 clock-names = "pipe0";
2011 #phy-cells = <0>;
2012 clock-output-names = "pcie_1_pipe_clk";
2017 compatible = "qcom,sdm845-mem-noc";
2019 #interconnect-cells = <2>;
2020 qcom,bcm-voters = <&apps_bcm_voter>;
2024 compatible = "qcom,sdm845-dc-noc";
2026 #interconnect-cells = <2>;
2027 qcom,bcm-voters = <&apps_bcm_voter>;
2031 compatible = "qcom,sdm845-config-noc";
2033 #interconnect-cells = <2>;
2034 qcom,bcm-voters = <&apps_bcm_voter>;
2038 compatible = "qcom,sdm845-system-noc";
2040 #interconnect-cells = <2>;
2041 qcom,bcm-voters = <&apps_bcm_voter>;
2045 compatible = "qcom,sdm845-aggre1-noc";
2047 #interconnect-cells = <2>;
2048 qcom,bcm-voters = <&apps_bcm_voter>;
2052 compatible = "qcom,sdm845-aggre2-noc";
2054 #interconnect-cells = <2>;
2055 qcom,bcm-voters = <&apps_bcm_voter>;
2059 compatible = "qcom,sdm845-mmss-noc";
2061 #interconnect-cells = <2>;
2062 qcom,bcm-voters = <&apps_bcm_voter>;
2066 compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2067 "jedec,ufs-2.0";
2070 reg-names = "std", "ice";
2073 phy-names = "ufsphy";
2074 lanes-per-direction = <2>;
2075 power-domains = <&gcc UFS_PHY_GDSC>;
2076 #reset-cells = <1>;
2078 reset-names = "rst";
2082 clock-names =
2102 freq-table-hz =
2117 compatible = "qcom,sdm845-qmp-ufs-phy";
2119 #address-cells = <2>;
2120 #size-cells = <2>;
2122 clock-names = "ref",
2128 reset-names = "ufsphy";
2137 #phy-cells = <0>;
2142 compatible = "qcom,sdm845-ipa";
2148 reg-names = "ipa-reg",
2149 "ipa-shared",
2152 interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>,
2156 interrupt-names = "ipa",
2158 "ipa-clock-query",
2159 "ipa-setup-ready";
2162 clock-names = "core";
2167 interconnect-names = "memory",
2171 qcom,smem-states = <&ipa_smp2p_out 0>,
2173 qcom,smem-state-names = "ipa-clock-enabled-valid",
2174 "ipa-clock-enabled";
2176 modem-remoteproc = <&mss_pil>;
2187 compatible = "qcom,sdm845-pinctrl";
2190 gpio-controller;
2191 #gpio-cells = <2>;
2192 interrupt-controller;
2193 #interrupt-cells = <2>;
2194 gpio-ranges = <&tlmm 0 0 150>;
2195 wakeup-parent = <&pdc_intc>;
2197 cci0_default: cci0-default {
2202 bias-pull-up;
2203 drive-strength = <2>; /* 2 mA */
2206 cci0_sleep: cci0-sleep {
2211 drive-strength = <2>; /* 2 mA */
2212 bias-pull-down;
2215 cci1_default: cci1-default {
2220 bias-pull-up;
2221 drive-strength = <2>; /* 2 mA */
2224 cci1_sleep: cci1-sleep {
2229 drive-strength = <2>; /* 2 mA */
2230 bias-pull-down;
2233 qspi_clk: qspi-clk {
2240 qspi_cs0: qspi-cs0 {
2247 qspi_cs1: qspi-cs1 {
2254 qspi_data01: qspi-data01 {
2255 pinmux-data {
2261 qspi_data12: qspi-data12 {
2262 pinmux-data {
2268 qup_i2c0_default: qup-i2c0-default {
2275 qup_i2c1_default: qup-i2c1-default {
2282 qup_i2c2_default: qup-i2c2-default {
2289 qup_i2c3_default: qup-i2c3-default {
2296 qup_i2c4_default: qup-i2c4-default {
2303 qup_i2c5_default: qup-i2c5-default {
2310 qup_i2c6_default: qup-i2c6-default {
2317 qup_i2c7_default: qup-i2c7-default {
2324 qup_i2c8_default: qup-i2c8-default {
2331 qup_i2c9_default: qup-i2c9-default {
2338 qup_i2c10_default: qup-i2c10-default {
2345 qup_i2c11_default: qup-i2c11-default {
2352 qup_i2c12_default: qup-i2c12-default {
2359 qup_i2c13_default: qup-i2c13-default {
2366 qup_i2c14_default: qup-i2c14-default {
2373 qup_i2c15_default: qup-i2c15-default {
2380 qup_spi0_default: qup-spi0-default {
2388 qup_spi1_default: qup-spi1-default {
2396 qup_spi2_default: qup-spi2-default {
2404 qup_spi3_default: qup-spi3-default {
2412 qup_spi4_default: qup-spi4-default {
2420 qup_spi5_default: qup-spi5-default {
2428 qup_spi6_default: qup-spi6-default {
2436 qup_spi7_default: qup-spi7-default {
2444 qup_spi8_default: qup-spi8-default {
2452 qup_spi9_default: qup-spi9-default {
2460 qup_spi10_default: qup-spi10-default {
2468 qup_spi11_default: qup-spi11-default {
2476 qup_spi12_default: qup-spi12-default {
2484 qup_spi13_default: qup-spi13-default {
2492 qup_spi14_default: qup-spi14-default {
2500 qup_spi15_default: qup-spi15-default {
2508 qup_uart0_default: qup-uart0-default {
2515 qup_uart1_default: qup-uart1-default {
2522 qup_uart2_default: qup-uart2-default {
2529 qup_uart3_default: qup-uart3-default {
2536 qup_uart4_default: qup-uart4-default {
2543 qup_uart5_default: qup-uart5-default {
2550 qup_uart6_default: qup-uart6-default {
2557 qup_uart7_default: qup-uart7-default {
2564 qup_uart8_default: qup-uart8-default {
2571 qup_uart9_default: qup-uart9-default {
2578 qup_uart10_default: qup-uart10-default {
2585 qup_uart11_default: qup-uart11-default {
2592 qup_uart12_default: qup-uart12-default {
2599 qup_uart13_default: qup-uart13-default {
2606 qup_uart14_default: qup-uart14-default {
2613 qup_uart15_default: qup-uart15-default {
2623 function = "gpio";
2628 drive-strength = <2>;
2629 bias-pull-down;
2630 input-enable;
2642 drive-strength = <8>;
2643 bias-disable;
2644 output-high;
2651 function = "gpio";
2656 drive-strength = <2>;
2657 bias-pull-down;
2658 input-enable;
2670 drive-strength = <8>;
2671 bias-disable;
2678 function = "gpio";
2683 drive-strength = <2>;
2684 bias-pull-down;
2685 input-enable;
2697 drive-strength = <8>;
2698 bias-disable;
2705 function = "gpio";
2710 drive-strength = <2>;
2711 bias-pull-down;
2712 input-enable;
2724 drive-strength = <8>;
2725 bias-disable;
2732 function = "gpio";
2737 drive-strength = <2>;
2738 bias-pull-down;
2739 input-enable;
2751 drive-strength = <8>;
2752 bias-disable;
2758 compatible = "qcom,sdm845-mss-pil";
2760 reg-names = "qdsp6", "rmb";
2762 interrupts-extended =
2769 interrupt-names = "wdog", "fatal", "ready",
2770 "handover", "stop-ack",
2771 "shutdown-ack";
2781 clock-names = "iface", "bus", "mem", "gpll0_mss",
2784 qcom,smem-states = <&modem_smp2p_out 0>;
2785 qcom,smem-state-names = "stop";
2789 reset-names = "mss_restart", "pdc_reset";
2791 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
2793 power-domains = <&aoss_qmp 2>,
2797 power-domain-names = "load_state", "cx", "mx", "mss";
2800 memory-region = <&mba_region>;
2804 memory-region = <&mpss_region>;
2807 glink-edge {
2810 qcom,remote-pid = <1>;
2815 gpucc: clock-controller@5090000 {
2816 compatible = "qcom,sdm845-gpucc";
2818 #clock-cells = <1>;
2819 #reset-cells = <1>;
2820 #power-domain-cells = <1>;
2824 clock-names = "bi_tcxo",
2830 compatible = "arm,coresight-stm", "arm,primecell";
2833 reg-names = "stm-base", "stm-stimulus-base";
2836 clock-names = "apb_pclk";
2838 out-ports {
2841 remote-endpoint =
2849 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2853 clock-names = "apb_pclk";
2855 out-ports {
2858 remote-endpoint =
2864 in-ports {
2865 #address-cells = <1>;
2866 #size-cells = <0>;
2871 remote-endpoint = <&stm_out>;
2878 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2882 clock-names = "apb_pclk";
2884 out-ports {
2887 remote-endpoint =
2893 in-ports {
2894 #address-cells = <1>;
2895 #size-cells = <0>;
2900 remote-endpoint =
2908 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2912 clock-names = "apb_pclk";
2914 out-ports {
2917 remote-endpoint = <&etf_in>;
2922 in-ports {
2923 #address-cells = <1>;
2924 #size-cells = <0>;
2929 remote-endpoint =
2937 remote-endpoint =
2945 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2949 clock-names = "apb_pclk";
2951 out-ports {
2954 remote-endpoint = <&etr_in>;
2959 in-ports {
2962 remote-endpoint = <&etf_out>;
2969 compatible = "arm,coresight-tmc", "arm,primecell";
2973 clock-names = "apb_pclk";
2975 out-ports {
2978 remote-endpoint =
2984 in-ports {
2985 #address-cells = <1>;
2986 #size-cells = <0>;
2991 remote-endpoint =
2999 compatible = "arm,coresight-tmc", "arm,primecell";
3003 clock-names = "apb_pclk";
3004 arm,scatter-gather;
3006 in-ports {
3009 remote-endpoint =
3017 compatible = "arm,coresight-etm4x", "arm,primecell";
3023 clock-names = "apb_pclk";
3024 arm,coresight-loses-context-with-cpu;
3026 out-ports {
3029 remote-endpoint =
3037 compatible = "arm,coresight-etm4x", "arm,primecell";
3043 clock-names = "apb_pclk";
3044 arm,coresight-loses-context-with-cpu;
3046 out-ports {
3049 remote-endpoint =
3057 compatible = "arm,coresight-etm4x", "arm,primecell";
3063 clock-names = "apb_pclk";
3064 arm,coresight-loses-context-with-cpu;
3066 out-ports {
3069 remote-endpoint =
3077 compatible = "arm,coresight-etm4x", "arm,primecell";
3083 clock-names = "apb_pclk";
3084 arm,coresight-loses-context-with-cpu;
3086 out-ports {
3089 remote-endpoint =
3097 compatible = "arm,coresight-etm4x", "arm,primecell";
3103 clock-names = "apb_pclk";
3104 arm,coresight-loses-context-with-cpu;
3106 out-ports {
3109 remote-endpoint =
3117 compatible = "arm,coresight-etm4x", "arm,primecell";
3123 clock-names = "apb_pclk";
3124 arm,coresight-loses-context-with-cpu;
3126 out-ports {
3129 remote-endpoint =
3137 compatible = "arm,coresight-etm4x", "arm,primecell";
3143 clock-names = "apb_pclk";
3144 arm,coresight-loses-context-with-cpu;
3146 out-ports {
3149 remote-endpoint =
3157 compatible = "arm,coresight-etm4x", "arm,primecell";
3163 clock-names = "apb_pclk";
3164 arm,coresight-loses-context-with-cpu;
3166 out-ports {
3169 remote-endpoint =
3177 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3181 clock-names = "apb_pclk";
3183 out-ports {
3186 remote-endpoint =
3192 in-ports {
3193 #address-cells = <1>;
3194 #size-cells = <0>;
3199 remote-endpoint =
3207 remote-endpoint =
3215 remote-endpoint =
3223 remote-endpoint =
3231 remote-endpoint =
3239 remote-endpoint =
3247 remote-endpoint =
3255 remote-endpoint =
3263 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3267 clock-names = "apb_pclk";
3269 out-ports {
3272 remote-endpoint =
3278 in-ports {
3281 remote-endpoint =
3289 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3294 interrupt-names = "hc_irq", "pwr_irq";
3298 clock-names = "iface", "core";
3300 power-domains = <&rpmhpd SDM845_CX>;
3301 operating-points-v2 = <&sdhc2_opp_table>;
3305 sdhc2_opp_table: sdhc2-opp-table {
3306 compatible = "operating-points-v2";
3308 opp-9600000 {
3309 opp-hz = /bits/ 64 <9600000>;
3310 required-opps = <&rpmhpd_opp_min_svs>;
3313 opp-19200000 {
3314 opp-hz = /bits/ 64 <19200000>;
3315 required-opps = <&rpmhpd_opp_low_svs>;
3318 opp-100000000 {
3319 opp-hz = /bits/ 64 <100000000>;
3320 required-opps = <&rpmhpd_opp_svs>;
3323 opp-201500000 {
3324 opp-hz = /bits/ 64 <201500000>;
3325 required-opps = <&rpmhpd_opp_svs_l1>;
3330 qspi_opp_table: qspi-opp-table {
3331 compatible = "operating-points-v2";
3333 opp-19200000 {
3334 opp-hz = /bits/ 64 <19200000>;
3335 required-opps = <&rpmhpd_opp_min_svs>;
3338 opp-100000000 {
3339 opp-hz = /bits/ 64 <100000000>;
3340 required-opps = <&rpmhpd_opp_low_svs>;
3343 opp-150000000 {
3344 opp-hz = /bits/ 64 <150000000>;
3345 required-opps = <&rpmhpd_opp_svs>;
3348 opp-300000000 {
3349 opp-hz = /bits/ 64 <300000000>;
3350 required-opps = <&rpmhpd_opp_nom>;
3355 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3357 #address-cells = <1>;
3358 #size-cells = <0>;
3362 clock-names = "iface", "core";
3363 power-domains = <&rpmhpd SDM845_CX>;
3364 operating-points-v2 = <&qspi_opp_table>;
3369 compatible = "qcom,slim-ngd-v2.1.0";
3373 qcom,apps-ch-pipes = <0x780000>;
3374 qcom,ea-pc = <0x270>;
3378 dma-names = "rx", "tx", "tx2", "rx2";
3381 #address-cells = <1>;
3382 #size-cells = <0>;
3386 #address-cells = <2>;
3387 #size-cells = <0>;
3394 wcd9340: codec@1{ label
3397 slim-ifc-dev = <&wcd9340_ifd>;
3399 #sound-dai-cells = <1>;
3401 interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
3402 interrupt-controller;
3403 #interrupt-cells = <1>;
3405 #clock-cells = <0>;
3406 clock-frequency = <9600000>;
3407 clock-output-names = "mclk";
3408 qcom,micbias1-millivolt = <1800>;
3409 qcom,micbias2-millivolt = <1800>;
3410 qcom,micbias3-millivolt = <1800>;
3411 qcom,micbias4-millivolt = <1800>;
3413 #address-cells = <1>;
3414 #size-cells = <1>;
3416 wcdgpio: gpio-controller@42 {
3417 compatible = "qcom,wcd9340-gpio";
3418 gpio-controller;
3419 #gpio-cells = <2>;
3424 compatible = "qcom,soundwire-v1.3.0";
3426 interrupts-extended = <&wcd9340 20>;
3428 qcom,dout-ports = <6>;
3429 qcom,din-ports = <2>;
3430 qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
3431 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
3432 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
3434 #sound-dai-cells = <1>;
3435 clocks = <&wcd9340>;
3436 clock-names = "iface";
3437 #address-cells = <2>;
3438 #size-cells = <0>;
3450 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3453 #phy-cells = <0>;
3457 clock-names = "cfg_ahb", "ref";
3461 nvmem-cells = <&qusb2p_hstx_trim>;
3465 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3468 #phy-cells = <0>;
3472 clock-names = "cfg_ahb", "ref";
3476 nvmem-cells = <&qusb2s_hstx_trim>;
3480 compatible = "qcom,sdm845-qmp-usb3-phy";
3483 reg-names = "reg-base", "dp_com";
3485 #clock-cells = <1>;
3486 #address-cells = <2>;
3487 #size-cells = <2>;
3494 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
3498 reset-names = "phy", "common";
3507 #phy-cells = <0>;
3509 clock-names = "pipe0";
3510 clock-output-names = "usb3_phy_pipe_clk_src";
3515 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
3518 #clock-cells = <1>;
3519 #address-cells = <2>;
3520 #size-cells = <2>;
3527 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
3531 reset-names = "phy", "common";
3538 #phy-cells = <0>;
3540 clock-names = "pipe0";
3541 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3546 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
3549 #address-cells = <2>;
3550 #size-cells = <2>;
3552 dma-ranges;
3559 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3562 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3564 assigned-clock-rates = <19200000>, <150000000>;
3570 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3573 power-domains = <&gcc USB30_PRIM_GDSC>;
3579 interconnect-names = "usb-ddr", "apps-usb";
3589 phy-names = "usb2-phy", "usb3-phy";
3594 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
3597 #address-cells = <2>;
3598 #size-cells = <2>;
3600 dma-ranges;
3607 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3610 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3612 assigned-clock-rates = <19200000>, <150000000>;
3618 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3621 power-domains = <&gcc USB30_SEC_GDSC>;
3627 interconnect-names = "usb-ddr", "apps-usb";
3637 phy-names = "usb2-phy", "usb3-phy";
3641 venus: video-codec@aa00000 {
3642 compatible = "qcom,sdm845-venus-v2";
3645 power-domains = <&videocc VENUS_GDSC>,
3649 power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
3650 operating-points-v2 = <&venus_opp_table>;
3658 clock-names = "core", "iface", "bus",
3663 memory-region = <&venus_mem>;
3665 video-core0 {
3666 compatible = "venus-decoder";
3669 video-core1 {
3670 compatible = "venus-encoder";
3673 venus_opp_table: venus-opp-table {
3674 compatible = "operating-points-v2";
3676 opp-100000000 {
3677 opp-hz = /bits/ 64 <100000000>;
3678 required-opps = <&rpmhpd_opp_min_svs>;
3681 opp-200000000 {
3682 opp-hz = /bits/ 64 <200000000>;
3683 required-opps = <&rpmhpd_opp_low_svs>;
3686 opp-320000000 {
3687 opp-hz = /bits/ 64 <320000000>;
3688 required-opps = <&rpmhpd_opp_svs>;
3691 opp-380000000 {
3692 opp-hz = /bits/ 64 <380000000>;
3693 required-opps = <&rpmhpd_opp_svs_l1>;
3696 opp-444000000 {
3697 opp-hz = /bits/ 64 <444000000>;
3698 required-opps = <&rpmhpd_opp_nom>;
3701 opp-533000097 {
3702 opp-hz = /bits/ 64 <533000097>;
3703 required-opps = <&rpmhpd_opp_turbo>;
3708 videocc: clock-controller@ab00000 {
3709 compatible = "qcom,sdm845-videocc";
3712 clock-names = "bi_tcxo";
3713 #clock-cells = <1>;
3714 #power-domain-cells = <1>;
3715 #reset-cells = <1>;
3719 compatible = "qcom,sdm845-cci";
3720 #address-cells = <1>;
3721 #size-cells = <0>;
3725 power-domains = <&clock_camcc TITAN_TOP_GDSC>;
3733 clock-names = "camnoc_axi",
3740 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
3742 assigned-clock-rates = <80000000>, <37500000>;
3744 pinctrl-names = "default", "sleep";
3745 pinctrl-0 = <&cci0_default &cci1_default>;
3746 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
3750 cci_i2c0: i2c-bus@0 {
3752 clock-frequency = <1000000>;
3753 #address-cells = <1>;
3754 #size-cells = <0>;
3757 cci_i2c1: i2c-bus@1 {
3759 clock-frequency = <1000000>;
3760 #address-cells = <1>;
3761 #size-cells = <0>;
3765 clock_camcc: clock-controller@ad00000 {
3766 compatible = "qcom,sdm845-camcc";
3768 #clock-cells = <1>;
3769 #reset-cells = <1>;
3770 #power-domain-cells = <1>;
3773 dsi_opp_table: dsi-opp-table {
3774 compatible = "operating-points-v2";
3776 opp-19200000 {
3777 opp-hz = /bits/ 64 <19200000>;
3778 required-opps = <&rpmhpd_opp_min_svs>;
3781 opp-180000000 {
3782 opp-hz = /bits/ 64 <180000000>;
3783 required-opps = <&rpmhpd_opp_low_svs>;
3786 opp-275000000 {
3787 opp-hz = /bits/ 64 <275000000>;
3788 required-opps = <&rpmhpd_opp_svs>;
3791 opp-328580000 {
3792 opp-hz = /bits/ 64 <328580000>;
3793 required-opps = <&rpmhpd_opp_svs_l1>;
3796 opp-358000000 {
3797 opp-hz = /bits/ 64 <358000000>;
3798 required-opps = <&rpmhpd_opp_nom>;
3803 compatible = "qcom,sdm845-mdss";
3805 reg-names = "mdss";
3807 power-domains = <&dispcc MDSS_GDSC>;
3812 clock-names = "iface", "bus", "core";
3814 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
3815 assigned-clock-rates = <300000000>;
3818 interrupt-controller;
3819 #interrupt-cells = <1>;
3823 interconnect-names = "mdp0-mem", "mdp1-mem";
3830 #address-cells = <2>;
3831 #size-cells = <2>;
3835 compatible = "qcom,sdm845-dpu";
3838 reg-names = "mdp", "vbif";
3844 clock-names = "iface", "bus", "core", "vsync";
3846 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
3848 assigned-clock-rates = <300000000>,
3850 operating-points-v2 = <&mdp_opp_table>;
3851 power-domains = <&rpmhpd SDM845_CX>;
3853 interrupt-parent = <&mdss>;
3859 #address-cells = <1>;
3860 #size-cells = <0>;
3865 remote-endpoint = <&dsi0_in>;
3872 remote-endpoint = <&dsi1_in>;
3877 mdp_opp_table: mdp-opp-table {
3878 compatible = "operating-points-v2";
3880 opp-19200000 {
3881 opp-hz = /bits/ 64 <19200000>;
3882 required-opps = <&rpmhpd_opp_min_svs>;
3885 opp-171428571 {
3886 opp-hz = /bits/ 64 <171428571>;
3887 required-opps = <&rpmhpd_opp_low_svs>;
3890 opp-344000000 {
3891 opp-hz = /bits/ 64 <344000000>;
3892 required-opps = <&rpmhpd_opp_svs_l1>;
3895 opp-430000000 {
3896 opp-hz = /bits/ 64 <430000000>;
3897 required-opps = <&rpmhpd_opp_nom>;
3903 compatible = "qcom,mdss-dsi-ctrl";
3905 reg-names = "dsi_ctrl";
3907 interrupt-parent = <&mdss>;
3916 clock-names = "byte",
3922 operating-points-v2 = <&dsi_opp_table>;
3923 power-domains = <&rpmhpd SDM845_CX>;
3926 phy-names = "dsi";
3931 #address-cells = <1>;
3932 #size-cells = <0>;
3937 remote-endpoint = <&dpu_intf1_out>;
3949 dsi0_phy: dsi-phy@ae94400 {
3950 compatible = "qcom,dsi-phy-10nm";
3954 reg-names = "dsi_phy",
3958 #clock-cells = <1>;
3959 #phy-cells = <0>;
3963 clock-names = "iface", "ref";
3969 compatible = "qcom,mdss-dsi-ctrl";
3971 reg-names = "dsi_ctrl";
3973 interrupt-parent = <&mdss>;
3982 clock-names = "byte",
3988 operating-points-v2 = <&dsi_opp_table>;
3989 power-domains = <&rpmhpd SDM845_CX>;
3992 phy-names = "dsi";
3997 #address-cells = <1>;
3998 #size-cells = <0>;
4003 remote-endpoint = <&dpu_intf2_out>;
4015 dsi1_phy: dsi-phy@ae96400 {
4016 compatible = "qcom,dsi-phy-10nm";
4020 reg-names = "dsi_phy",
4024 #clock-cells = <1>;
4025 #phy-cells = <0>;
4029 clock-names = "iface", "ref";
4036 compatible = "qcom,adreno-630.2", "qcom,adreno";
4037 #stream-id-cells = <16>;
4040 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4051 operating-points-v2 = <&gpu_opp_table>;
4056 interconnect-names = "gfx-mem";
4058 gpu_opp_table: opp-table {
4059 compatible = "operating-points-v2";
4061 opp-710000000 {
4062 opp-hz = /bits/ 64 <710000000>;
4063 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4064 opp-peak-kBps = <7216000>;
4067 opp-675000000 {
4068 opp-hz = /bits/ 64 <675000000>;
4069 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4070 opp-peak-kBps = <7216000>;
4073 opp-596000000 {
4074 opp-hz = /bits/ 64 <596000000>;
4075 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4076 opp-peak-kBps = <6220000>;
4079 opp-520000000 {
4080 opp-hz = /bits/ 64 <520000000>;
4081 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4082 opp-peak-kBps = <6220000>;
4085 opp-414000000 {
4086 opp-hz = /bits/ 64 <414000000>;
4087 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4088 opp-peak-kBps = <4068000>;
4091 opp-342000000 {
4092 opp-hz = /bits/ 64 <342000000>;
4093 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4094 opp-peak-kBps = <2724000>;
4097 opp-257000000 {
4098 opp-hz = /bits/ 64 <257000000>;
4099 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4100 opp-peak-kBps = <1648000>;
4106 compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
4108 #iommu-cells = <1>;
4109 #global-interrupts = <2>;
4122 clock-names = "bus", "iface";
4124 power-domains = <&gpucc GPU_CX_GDSC>;
4128 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4133 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4137 interrupt-names = "hfi", "gmu";
4143 clock-names = "gmu", "cxo", "axi", "memnoc";
4145 power-domains = <&gpucc GPU_CX_GDSC>,
4147 power-domain-names = "cx", "gx";
4151 operating-points-v2 = <&gmu_opp_table>;
4153 gmu_opp_table: opp-table {
4154 compatible = "operating-points-v2";
4156 opp-400000000 {
4157 opp-hz = /bits/ 64 <400000000>;
4158 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4161 opp-200000000 {
4162 opp-hz = /bits/ 64 <200000000>;
4163 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4168 dispcc: clock-controller@af00000 {
4169 compatible = "qcom,sdm845-dispcc";
4180 clock-names = "bi_tcxo",
4189 #clock-cells = <1>;
4190 #reset-cells = <1>;
4191 #power-domain-cells = <1>;
4194 pdc_intc: interrupt-controller@b220000 {
4195 compatible = "qcom,sdm845-pdc", "qcom,pdc";
4197 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4198 #interrupt-cells = <2>;
4199 interrupt-parent = <&intc>;
4200 interrupt-controller;
4203 pdc_reset: reset-controller@b2e0000 {
4204 compatible = "qcom,sdm845-pdc-global";
4206 #reset-cells = <1>;
4209 tsens0: thermal-sensor@c263000 {
4210 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4216 interrupt-names = "uplow", "critical";
4217 #thermal-sensor-cells = <1>;
4220 tsens1: thermal-sensor@c265000 {
4221 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4227 interrupt-names = "uplow", "critical";
4228 #thermal-sensor-cells = <1>;
4231 aoss_reset: reset-controller@c2a0000 {
4232 compatible = "qcom,sdm845-aoss-cc";
4234 #reset-cells = <1>;
4238 compatible = "qcom,sdm845-aoss-qmp";
4243 #clock-cells = <0>;
4244 #power-domain-cells = <1>;
4247 #cooling-cells = <2>;
4251 #cooling-cells = <2>;
4256 compatible = "qcom,spmi-pmic-arb";
4262 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4263 interrupt-names = "periph_irq";
4267 #address-cells = <2>;
4268 #size-cells = <0>;
4269 interrupt-controller;
4270 #interrupt-cells = <4>;
4271 cell-index = <0>;
4275 compatible = "simple-mfd";
4278 #address-cells = <1>;
4279 #size-cells = <1>;
4283 pil-reloc@94c {
4284 compatible = "qcom,pil-reloc-info";
4290 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
4292 #iommu-cells = <2>;
4293 #global-interrupts = <1>;
4361 lpasscc: clock-controller@17014000 {
4362 compatible = "qcom,sdm845-lpasscc";
4364 reg-names = "cc", "qdsp6ss";
4365 #clock-cells = <1>;
4370 compatible = "qcom,sdm845-gladiator-noc";
4372 #interconnect-cells = <2>;
4373 qcom,bcm-voters = <&apps_bcm_voter>;
4377 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
4383 compatible = "qcom,sdm845-apss-shared";
4385 #mbox-cells = <1>;
4390 compatible = "qcom,rpmh-rsc";
4394 reg-names = "drv-0", "drv-1", "drv-2";
4398 qcom,tcs-offset = <0xd00>;
4399 qcom,drv-id = <2>;
4400 qcom,tcs-config = <ACTIVE_TCS 2>,
4405 apps_bcm_voter: bcm-voter {
4406 compatible = "qcom,bcm-voter";
4409 rpmhcc: clock-controller {
4410 compatible = "qcom,sdm845-rpmh-clk";
4411 #clock-cells = <1>;
4412 clock-names = "xo";
4416 rpmhpd: power-controller {
4417 compatible = "qcom,sdm845-rpmhpd";
4418 #power-domain-cells = <1>;
4419 operating-points-v2 = <&rpmhpd_opp_table>;
4421 rpmhpd_opp_table: opp-table {
4422 compatible = "operating-points-v2";
4425 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4429 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4433 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4437 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4441 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4445 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4449 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4453 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4457 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4461 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4467 intc: interrupt-controller@17a00000 {
4468 compatible = "arm,gic-v3";
4469 #address-cells = <2>;
4470 #size-cells = <2>;
4472 #interrupt-cells = <3>;
4473 interrupt-controller;
4478 msi-controller@17a40000 {
4479 compatible = "arm,gic-v3-its";
4480 msi-controller;
4481 #msi-cells = <1>;
4488 compatible = "qcom,bam-v1.7.0";
4489 qcom,controlled-remotely;
4491 num-channels = <31>;
4493 #dma-cells = <1>;
4495 qcom,num-ees = <2>;
4500 #address-cells = <2>;
4501 #size-cells = <2>;
4503 compatible = "arm,armv7-timer-mem";
4507 frame-number = <0>;
4515 frame-number = <1>;
4522 frame-number = <2>;
4529 frame-number = <3>;
4536 frame-number = <4>;
4543 frame-number = <5>;
4550 frame-number = <6>;
4558 compatible = "qcom,sdm845-osm-l3";
4562 clock-names = "xo", "alternate";
4564 #interconnect-cells = <1>;
4568 compatible = "qcom,cpufreq-hw";
4570 reg-names = "freq-domain0", "freq-domain1";
4573 clock-names = "xo", "alternate";
4575 #freq-domain-cells = <1>;
4579 compatible = "qcom,wcn3990-wifi";
4582 reg-names = "membase";
4583 memory-region = <&wlan_msa_mem>;
4584 clock-names = "cxo_ref_clk_pin";
4603 thermal-zones {
4604 cpu0-thermal {
4605 polling-delay-passive = <250>;
4606 polling-delay = <1000>;
4608 thermal-sensors = <&tsens0 1>;
4611 cpu0_alert0: trip-point0 {
4617 cpu0_alert1: trip-point1 {
4630 cooling-maps {
4633 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4640 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4648 cpu1-thermal {
4649 polling-delay-passive = <250>;
4650 polling-delay = <1000>;
4652 thermal-sensors = <&tsens0 2>;
4655 cpu1_alert0: trip-point0 {
4661 cpu1_alert1: trip-point1 {
4674 cooling-maps {
4677 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4684 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4692 cpu2-thermal {
4693 polling-delay-passive = <250>;
4694 polling-delay = <1000>;
4696 thermal-sensors = <&tsens0 3>;
4699 cpu2_alert0: trip-point0 {
4705 cpu2_alert1: trip-point1 {
4718 cooling-maps {
4721 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4728 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4736 cpu3-thermal {
4737 polling-delay-passive = <250>;
4738 polling-delay = <1000>;
4740 thermal-sensors = <&tsens0 4>;
4743 cpu3_alert0: trip-point0 {
4749 cpu3_alert1: trip-point1 {
4762 cooling-maps {
4765 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4772 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4780 cpu4-thermal {
4781 polling-delay-passive = <250>;
4782 polling-delay = <1000>;
4784 thermal-sensors = <&tsens0 7>;
4787 cpu4_alert0: trip-point0 {
4793 cpu4_alert1: trip-point1 {
4806 cooling-maps {
4809 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4816 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4824 cpu5-thermal {
4825 polling-delay-passive = <250>;
4826 polling-delay = <1000>;
4828 thermal-sensors = <&tsens0 8>;
4831 cpu5_alert0: trip-point0 {
4837 cpu5_alert1: trip-point1 {
4850 cooling-maps {
4853 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4860 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4868 cpu6-thermal {
4869 polling-delay-passive = <250>;
4870 polling-delay = <1000>;
4872 thermal-sensors = <&tsens0 9>;
4875 cpu6_alert0: trip-point0 {
4881 cpu6_alert1: trip-point1 {
4894 cooling-maps {
4897 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4904 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4912 cpu7-thermal {
4913 polling-delay-passive = <250>;
4914 polling-delay = <1000>;
4916 thermal-sensors = <&tsens0 10>;
4919 cpu7_alert0: trip-point0 {
4925 cpu7_alert1: trip-point1 {
4938 cooling-maps {
4941 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4948 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4956 aoss0-thermal {
4957 polling-delay-passive = <250>;
4958 polling-delay = <1000>;
4960 thermal-sensors = <&tsens0 0>;
4963 aoss0_alert0: trip-point0 {
4971 cluster0-thermal {
4972 polling-delay-passive = <250>;
4973 polling-delay = <1000>;
4975 thermal-sensors = <&tsens0 5>;
4978 cluster0_alert0: trip-point0 {
4991 cluster1-thermal {
4992 polling-delay-passive = <250>;
4993 polling-delay = <1000>;
4995 thermal-sensors = <&tsens0 6>;
4998 cluster1_alert0: trip-point0 {
5011 gpu-thermal-top {
5012 polling-delay-passive = <250>;
5013 polling-delay = <1000>;
5015 thermal-sensors = <&tsens0 11>;
5018 gpu1_alert0: trip-point0 {
5026 gpu-thermal-bottom {
5027 polling-delay-passive = <250>;
5028 polling-delay = <1000>;
5030 thermal-sensors = <&tsens0 12>;
5033 gpu2_alert0: trip-point0 {
5041 aoss1-thermal {
5042 polling-delay-passive = <250>;
5043 polling-delay = <1000>;
5045 thermal-sensors = <&tsens1 0>;
5048 aoss1_alert0: trip-point0 {
5056 q6-modem-thermal {
5057 polling-delay-passive = <250>;
5058 polling-delay = <1000>;
5060 thermal-sensors = <&tsens1 1>;
5063 q6_modem_alert0: trip-point0 {
5071 mem-thermal {
5072 polling-delay-passive = <250>;
5073 polling-delay = <1000>;
5075 thermal-sensors = <&tsens1 2>;
5078 mem_alert0: trip-point0 {
5086 wlan-thermal {
5087 polling-delay-passive = <250>;
5088 polling-delay = <1000>;
5090 thermal-sensors = <&tsens1 3>;
5093 wlan_alert0: trip-point0 {
5101 q6-hvx-thermal {
5102 polling-delay-passive = <250>;
5103 polling-delay = <1000>;
5105 thermal-sensors = <&tsens1 4>;
5108 q6_hvx_alert0: trip-point0 {
5116 camera-thermal {
5117 polling-delay-passive = <250>;
5118 polling-delay = <1000>;
5120 thermal-sensors = <&tsens1 5>;
5123 camera_alert0: trip-point0 {
5131 video-thermal {
5132 polling-delay-passive = <250>;
5133 polling-delay = <1000>;
5135 thermal-sensors = <&tsens1 6>;
5138 video_alert0: trip-point0 {
5146 modem-thermal {
5147 polling-delay-passive = <250>;
5148 polling-delay = <1000>;
5150 thermal-sensors = <&tsens1 7>;
5153 modem_alert0: trip-point0 {