Lines Matching +full:0 +full:x5000000
73 reg = <0 0x80000000 0 0>;
82 reg = <0 0x85700000 0 0x600000>;
87 reg = <0 0x85e00000 0 0x100000>;
92 reg = <0 0x85fc0000 0 0x20000>;
98 reg = <0x0 0x85fe0000 0 0x20000>;
103 reg = <0x0 0x86000000 0 0x200000>;
108 reg = <0 0x86200000 0 0x2d00000>;
114 reg = <0 0x88f00000 0 0x200000>;
122 reg = <0 0x8ab00000 0 0x1400000>;
127 reg = <0 0x8bf00000 0 0x500000>;
132 reg = <0 0x8c400000 0 0x10000>;
137 reg = <0 0x8c410000 0 0x5000>;
142 reg = <0 0x8c415000 0 0x2000>;
147 reg = <0 0x8c500000 0 0x1a00000>;
152 reg = <0 0x8df00000 0 0x100000>;
157 reg = <0 0x8e000000 0 0x7800000>;
162 reg = <0 0x95800000 0 0x500000>;
167 reg = <0 0x95d00000 0 0x800000>;
172 reg = <0 0x96500000 0 0x200000>;
177 reg = <0 0x96700000 0 0x1400000>;
182 reg = <0 0x97b00000 0 0x100000>;
189 #size-cells = <0>;
191 CPU0: cpu@0 {
194 reg = <0x0 0x0>;
201 qcom,freq-domain = <&cpufreq_hw 0>;
219 reg = <0x0 0x100>;
226 qcom,freq-domain = <&cpufreq_hw 0>;
241 reg = <0x0 0x200>;
248 qcom,freq-domain = <&cpufreq_hw 0>;
263 reg = <0x0 0x300>;
270 qcom,freq-domain = <&cpufreq_hw 0>;
285 reg = <0x0 0x400>;
307 reg = <0x0 0x500>;
329 reg = <0x0 0x600>;
351 reg = <0x0 0x700>;
409 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
412 arm,psci-suspend-param = <0x40000003>;
419 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
422 arm,psci-suspend-param = <0x40000004>;
429 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
432 arm,psci-suspend-param = <0x40000003>;
442 arm,psci-suspend-param = <0x40000004>;
449 CLUSTER_SLEEP_0: cluster-sleep-0 {
452 arm,psci-suspend-param = <0x400000F4>;
731 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
737 #clock-cells = <0>;
744 #clock-cells = <0>;
759 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
771 qcom,smem-states = <&adsp_smp2p_out 0>;
787 #size-cells = <0>;
803 #size-cells = <0>;
815 #size-cells = <0>;
817 iommus = <&apps_smmu 0x1821 0x0>;
827 #sound-dai-cells = <0>;
837 #size-cells = <0>;
842 iommus = <&apps_smmu 0x1823 0x0>;
848 iommus = <&apps_smmu 0x1824 0x0>;
858 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
870 qcom,smem-states = <&cdsp_smp2p_out 0>;
885 #size-cells = <0>;
890 iommus = <&apps_smmu 0x1401 0x30>;
896 iommus = <&apps_smmu 0x1402 0x30>;
902 iommus = <&apps_smmu 0x1403 0x30>;
908 iommus = <&apps_smmu 0x1404 0x30>;
914 iommus = <&apps_smmu 0x1405 0x30>;
920 iommus = <&apps_smmu 0x1406 0x30>;
926 iommus = <&apps_smmu 0x1407 0x30>;
932 iommus = <&apps_smmu 0x1408 0x30>;
940 syscon = <&tcsr_mutex_regs 0 0x1000>;
958 qcom,local-pid = <0>;
982 qcom,local-pid = <0>;
1003 qcom,local-pid = <0>;
1034 qcom,local-pid = <0>;
1054 soc: soc@0 {
1057 ranges = <0 0 0 0 0x10 0>;
1058 dma-ranges = <0 0 0 0 0x10 0>;
1063 reg = <0 0x00100000 0 0x1f0000>;
1071 reg = <0 0x00784000 0 0x8ff>;
1076 reg = <0x1eb 0x1>;
1081 reg = <0x1eb 0x2>;
1088 reg = <0 0x00793000 0 0x1000>;
1119 reg = <0 0x008c0000 0 0x6000>;
1130 reg = <0 0x00880000 0 0x4000>;
1134 pinctrl-0 = <&qup_i2c0_default>;
1137 #size-cells = <0>;
1145 reg = <0 0x00880000 0 0x4000>;
1149 pinctrl-0 = <&qup_spi0_default>;
1152 #size-cells = <0>;
1158 reg = <0 0x00880000 0 0x4000>;
1162 pinctrl-0 = <&qup_uart0_default>;
1171 reg = <0 0x00884000 0 0x4000>;
1175 pinctrl-0 = <&qup_i2c1_default>;
1178 #size-cells = <0>;
1186 reg = <0 0x00884000 0 0x4000>;
1190 pinctrl-0 = <&qup_spi1_default>;
1193 #size-cells = <0>;
1199 reg = <0 0x00884000 0 0x4000>;
1203 pinctrl-0 = <&qup_uart1_default>;
1212 reg = <0 0x00888000 0 0x4000>;
1216 pinctrl-0 = <&qup_i2c2_default>;
1219 #size-cells = <0>;
1227 reg = <0 0x00888000 0 0x4000>;
1231 pinctrl-0 = <&qup_spi2_default>;
1234 #size-cells = <0>;
1240 reg = <0 0x00888000 0 0x4000>;
1244 pinctrl-0 = <&qup_uart2_default>;
1253 reg = <0 0x0088c000 0 0x4000>;
1257 pinctrl-0 = <&qup_i2c3_default>;
1260 #size-cells = <0>;
1268 reg = <0 0x0088c000 0 0x4000>;
1272 pinctrl-0 = <&qup_spi3_default>;
1275 #size-cells = <0>;
1281 reg = <0 0x0088c000 0 0x4000>;
1285 pinctrl-0 = <&qup_uart3_default>;
1294 reg = <0 0x00890000 0 0x4000>;
1298 pinctrl-0 = <&qup_i2c4_default>;
1301 #size-cells = <0>;
1309 reg = <0 0x00890000 0 0x4000>;
1313 pinctrl-0 = <&qup_spi4_default>;
1316 #size-cells = <0>;
1322 reg = <0 0x00890000 0 0x4000>;
1326 pinctrl-0 = <&qup_uart4_default>;
1335 reg = <0 0x00894000 0 0x4000>;
1339 pinctrl-0 = <&qup_i2c5_default>;
1342 #size-cells = <0>;
1350 reg = <0 0x00894000 0 0x4000>;
1354 pinctrl-0 = <&qup_spi5_default>;
1357 #size-cells = <0>;
1363 reg = <0 0x00894000 0 0x4000>;
1367 pinctrl-0 = <&qup_uart5_default>;
1376 reg = <0 0x00898000 0 0x4000>;
1380 pinctrl-0 = <&qup_i2c6_default>;
1383 #size-cells = <0>;
1391 reg = <0 0x00898000 0 0x4000>;
1395 pinctrl-0 = <&qup_spi6_default>;
1398 #size-cells = <0>;
1404 reg = <0 0x00898000 0 0x4000>;
1408 pinctrl-0 = <&qup_uart6_default>;
1417 reg = <0 0x0089c000 0 0x4000>;
1421 pinctrl-0 = <&qup_i2c7_default>;
1424 #size-cells = <0>;
1432 reg = <0 0x0089c000 0 0x4000>;
1436 pinctrl-0 = <&qup_spi7_default>;
1439 #size-cells = <0>;
1445 reg = <0 0x0089c000 0 0x4000>;
1449 pinctrl-0 = <&qup_uart7_default>;
1459 reg = <0 0x00ac0000 0 0x6000>;
1470 reg = <0 0x00a80000 0 0x4000>;
1474 pinctrl-0 = <&qup_i2c8_default>;
1477 #size-cells = <0>;
1485 reg = <0 0x00a80000 0 0x4000>;
1489 pinctrl-0 = <&qup_spi8_default>;
1492 #size-cells = <0>;
1498 reg = <0 0x00a80000 0 0x4000>;
1502 pinctrl-0 = <&qup_uart8_default>;
1511 reg = <0 0x00a84000 0 0x4000>;
1515 pinctrl-0 = <&qup_i2c9_default>;
1518 #size-cells = <0>;
1526 reg = <0 0x00a84000 0 0x4000>;
1530 pinctrl-0 = <&qup_spi9_default>;
1533 #size-cells = <0>;
1539 reg = <0 0x00a84000 0 0x4000>;
1543 pinctrl-0 = <&qup_uart9_default>;
1552 reg = <0 0x00a88000 0 0x4000>;
1556 pinctrl-0 = <&qup_i2c10_default>;
1559 #size-cells = <0>;
1567 reg = <0 0x00a88000 0 0x4000>;
1571 pinctrl-0 = <&qup_spi10_default>;
1574 #size-cells = <0>;
1580 reg = <0 0x00a88000 0 0x4000>;
1584 pinctrl-0 = <&qup_uart10_default>;
1593 reg = <0 0x00a8c000 0 0x4000>;
1597 pinctrl-0 = <&qup_i2c11_default>;
1600 #size-cells = <0>;
1608 reg = <0 0x00a8c000 0 0x4000>;
1612 pinctrl-0 = <&qup_spi11_default>;
1615 #size-cells = <0>;
1621 reg = <0 0x00a8c000 0 0x4000>;
1625 pinctrl-0 = <&qup_uart11_default>;
1634 reg = <0 0x00a90000 0 0x4000>;
1638 pinctrl-0 = <&qup_i2c12_default>;
1641 #size-cells = <0>;
1649 reg = <0 0x00a90000 0 0x4000>;
1653 pinctrl-0 = <&qup_spi12_default>;
1656 #size-cells = <0>;
1662 reg = <0 0x00a90000 0 0x4000>;
1666 pinctrl-0 = <&qup_uart12_default>;
1675 reg = <0 0x00a94000 0 0x4000>;
1679 pinctrl-0 = <&qup_i2c13_default>;
1682 #size-cells = <0>;
1690 reg = <0 0x00a94000 0 0x4000>;
1694 pinctrl-0 = <&qup_spi13_default>;
1697 #size-cells = <0>;
1703 reg = <0 0x00a94000 0 0x4000>;
1707 pinctrl-0 = <&qup_uart13_default>;
1716 reg = <0 0x00a98000 0 0x4000>;
1720 pinctrl-0 = <&qup_i2c14_default>;
1723 #size-cells = <0>;
1731 reg = <0 0x00a98000 0 0x4000>;
1735 pinctrl-0 = <&qup_spi14_default>;
1738 #size-cells = <0>;
1744 reg = <0 0x00a98000 0 0x4000>;
1748 pinctrl-0 = <&qup_uart14_default>;
1757 reg = <0 0x00a9c000 0 0x4000>;
1761 pinctrl-0 = <&qup_i2c15_default>;
1764 #size-cells = <0>;
1772 reg = <0 0x00a9c000 0 0x4000>;
1776 pinctrl-0 = <&qup_spi15_default>;
1779 #size-cells = <0>;
1785 reg = <0 0x00a9c000 0 0x4000>;
1789 pinctrl-0 = <&qup_uart15_default>;
1799 reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
1806 reg = <0 0x01c00000 0 0x2000>,
1807 <0 0x60000000 0 0xf1d>,
1808 <0 0x60000f20 0 0xa8>,
1809 <0 0x60100000 0 0x100000>;
1812 linux,pci-domain = <0>;
1813 bus-range = <0x00 0xff>;
1819 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1820 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>;
1825 interrupt-map-mask = <0 0 0 0x7>;
1826 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1827 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1828 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1829 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1846 iommus = <&apps_smmu 0x1c10 0xf>;
1847 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
1848 <0x100 &apps_smmu 0x1c11 0x1>,
1849 <0x200 &apps_smmu 0x1c12 0x1>,
1850 <0x300 &apps_smmu 0x1c13 0x1>,
1851 <0x400 &apps_smmu 0x1c14 0x1>,
1852 <0x500 &apps_smmu 0x1c15 0x1>,
1853 <0x600 &apps_smmu 0x1c16 0x1>,
1854 <0x700 &apps_smmu 0x1c17 0x1>,
1855 <0x800 &apps_smmu 0x1c18 0x1>,
1856 <0x900 &apps_smmu 0x1c19 0x1>,
1857 <0xa00 &apps_smmu 0x1c1a 0x1>,
1858 <0xb00 &apps_smmu 0x1c1b 0x1>,
1859 <0xc00 &apps_smmu 0x1c1c 0x1>,
1860 <0xd00 &apps_smmu 0x1c1d 0x1>,
1861 <0xe00 &apps_smmu 0x1c1e 0x1>,
1862 <0xf00 &apps_smmu 0x1c1f 0x1>;
1877 reg = <0 0x01c06000 0 0x18c>;
1896 reg = <0 0x01c06200 0 0x128>,
1897 <0 0x01c06400 0 0x1fc>,
1898 <0 0x01c06800 0 0x218>,
1899 <0 0x01c06600 0 0x70>;
1903 #phy-cells = <0>;
1910 reg = <0 0x01c08000 0 0x2000>,
1911 <0 0x40000000 0 0xf1d>,
1912 <0 0x40000f20 0 0xa8>,
1913 <0 0x40100000 0 0x100000>;
1917 bus-range = <0x00 0xff>;
1923 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
1924 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1929 interrupt-map-mask = <0 0 0 0x7>;
1930 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1931 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1932 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1933 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1955 iommus = <&apps_smmu 0x1c00 0xf>;
1956 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1957 <0x100 &apps_smmu 0x1c01 0x1>,
1958 <0x200 &apps_smmu 0x1c02 0x1>,
1959 <0x300 &apps_smmu 0x1c03 0x1>,
1960 <0x400 &apps_smmu 0x1c04 0x1>,
1961 <0x500 &apps_smmu 0x1c05 0x1>,
1962 <0x600 &apps_smmu 0x1c06 0x1>,
1963 <0x700 &apps_smmu 0x1c07 0x1>,
1964 <0x800 &apps_smmu 0x1c08 0x1>,
1965 <0x900 &apps_smmu 0x1c09 0x1>,
1966 <0xa00 &apps_smmu 0x1c0a 0x1>,
1967 <0xb00 &apps_smmu 0x1c0b 0x1>,
1968 <0xc00 &apps_smmu 0x1c0c 0x1>,
1969 <0xd00 &apps_smmu 0x1c0d 0x1>,
1970 <0xe00 &apps_smmu 0x1c0e 0x1>,
1971 <0xf00 &apps_smmu 0x1c0f 0x1>;
1986 reg = <0 0x01c0a000 0 0x800>;
2005 reg = <0 0x01c0a800 0 0x800>,
2006 <0 0x01c0a800 0 0x800>,
2007 <0 0x01c0b800 0 0x400>;
2011 #phy-cells = <0>;
2018 reg = <0 0x01380000 0 0x27200>;
2025 reg = <0 0x014e0000 0 0x400>;
2032 reg = <0 0x01500000 0 0x5080>;
2039 reg = <0 0x01620000 0 0x18080>;
2046 reg = <0 0x016e0000 0 0x15080>;
2053 reg = <0 0x01700000 0 0x1f300>;
2060 reg = <0 0x01740000 0 0x1c100>;
2068 reg = <0 0x01d84000 0 0x2500>,
2069 <0 0x01d90000 0 0x8000>;
2080 iommus = <&apps_smmu 0x100 0xf>;
2104 <0 0>,
2105 <0 0>,
2107 <0 0>,
2108 <0 0>,
2109 <0 0>,
2110 <0 0>,
2111 <0 300000000>;
2118 reg = <0 0x01d87000 0 0x18c>;
2127 resets = <&ufs_mem_hc 0>;
2132 reg = <0 0x01d87400 0 0x108>,
2133 <0 0x01d87600 0 0x1e0>,
2134 <0 0x01d87c00 0 0x1dc>,
2135 <0 0x01d87800 0 0x108>,
2136 <0 0x01d87a00 0 0x1e0>;
2137 #phy-cells = <0>;
2144 iommus = <&apps_smmu 0x720 0x3>;
2145 reg = <0 0x1e40000 0 0x7000>,
2146 <0 0x1e47000 0 0x2000>,
2147 <0 0x1e04000 0 0x2c000>;
2152 interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>,
2153 <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>,
2154 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2164 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
2165 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
2166 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2171 qcom,smem-states = <&ipa_smp2p_out 0>,
2183 reg = <0 0x01f40000 0 0x40000>;
2188 reg = <0 0x03400000 0 0xc00000>;
2194 gpio-ranges = <&tlmm 0 0 150>;
2759 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
2764 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2784 qcom,smem-states = <&modem_smp2p_out 0>;
2791 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
2817 reg = <0 0x05090000 0 0x9000>;
2831 reg = <0 0x06002000 0 0x1000>,
2832 <0 0x16280000 0 0x180000>;
2850 reg = <0 0x06041000 0 0x1000>;
2866 #size-cells = <0>;
2879 reg = <0 0x06043000 0 0x1000>;
2895 #size-cells = <0>;
2909 reg = <0 0x06045000 0 0x1000>;
2924 #size-cells = <0>;
2926 port@0 {
2927 reg = <0>;
2946 reg = <0 0x06046000 0 0x1000>;
2970 reg = <0 0x06047000 0 0x1000>;
2986 #size-cells = <0>;
3000 reg = <0 0x06048000 0 0x1000>;
3018 reg = <0 0x07040000 0 0x1000>;
3038 reg = <0 0x07140000 0 0x1000>;
3058 reg = <0 0x07240000 0 0x1000>;
3078 reg = <0 0x07340000 0 0x1000>;
3098 reg = <0 0x07440000 0 0x1000>;
3118 reg = <0 0x07540000 0 0x1000>;
3138 reg = <0 0x07640000 0 0x1000>;
3158 reg = <0 0x07740000 0 0x1000>;
3178 reg = <0 0x07800000 0 0x1000>;
3194 #size-cells = <0>;
3196 port@0 {
3197 reg = <0>;
3264 reg = <0 0x07810000 0 0x1000>;
3290 reg = <0 0x08804000 0 0x1000>;
3299 iommus = <&apps_smmu 0xa0 0xf>;
3356 reg = <0 0x088df000 0 0x600>;
3358 #size-cells = <0>;
3370 reg = <0 0x171c0000 0 0x2c000>;
3373 qcom,apps-ch-pipes = <0x780000>;
3374 qcom,ea-pc = <0x270>;
3380 iommus = <&apps_smmu 0x1806 0x0>;
3382 #size-cells = <0>;
3387 #size-cells = <0>;
3389 wcd9340_ifd: ifd@0{
3391 reg = <0 0>;
3396 reg = <1 0>;
3405 #clock-cells = <0>;
3420 reg = <0x42 0x2>;
3425 reg = <0xc85 0x40>;
3430 qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
3431 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
3432 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
3438 #size-cells = <0>;
3451 reg = <0 0x088e2000 0 0x400>;
3453 #phy-cells = <0>;
3466 reg = <0 0x088e3000 0 0x400>;
3468 #phy-cells = <0>;
3481 reg = <0 0x088e9000 0 0x18c>,
3482 <0 0x088e8000 0 0x10>;
3501 reg = <0 0x088e9200 0 0x128>,
3502 <0 0x088e9400 0 0x200>,
3503 <0 0x088e9c00 0 0x218>,
3504 <0 0x088e9600 0 0x128>,
3505 <0 0x088e9800 0 0x200>,
3506 <0 0x088e9a00 0 0x100>;
3507 #phy-cells = <0>;
3516 reg = <0 0x088eb000 0 0x18c>;
3534 reg = <0 0x088eb200 0 0x128>,
3535 <0 0x088eb400 0 0x1fc>,
3536 <0 0x088eb800 0 0x218>,
3537 <0 0x088eb600 0 0x70>;
3538 #phy-cells = <0>;
3547 reg = <0 0x0a6f8800 0 0x400>;
3577 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
3578 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3583 reg = <0 0x0a600000 0 0xcd00>;
3585 iommus = <&apps_smmu 0x740 0>;
3595 reg = <0 0x0a8f8800 0 0x400>;
3625 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
3626 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
3631 reg = <0 0x0a800000 0 0xcd00>;
3633 iommus = <&apps_smmu 0x760 0>;
3643 reg = <0 0x0aa00000 0 0xff000>;
3661 iommus = <&apps_smmu 0x10a0 0x8>,
3662 <&apps_smmu 0x10b0 0x0>;
3710 reg = <0 0x0ab00000 0 0x10000>;
3721 #size-cells = <0>;
3723 reg = <0 0x0ac4a000 0 0x4000>;
3745 pinctrl-0 = <&cci0_default &cci1_default>;
3750 cci_i2c0: i2c-bus@0 {
3751 reg = <0>;
3754 #size-cells = <0>;
3761 #size-cells = <0>;
3767 reg = <0 0x0ad00000 0 0x10000>;
3804 reg = <0 0x0ae00000 0 0x1000>;
3821 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
3822 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
3825 iommus = <&apps_smmu 0x880 0x8>,
3826 <&apps_smmu 0xc80 0x8>;
3836 reg = <0 0x0ae01000 0 0x8f000>,
3837 <0 0x0aeb0000 0 0x2008>;
3854 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
3860 #size-cells = <0>;
3862 port@0 {
3863 reg = <0>;
3904 reg = <0 0x0ae94000 0 0x400>;
3932 #size-cells = <0>;
3934 port@0 {
3935 reg = <0>;
3951 reg = <0 0x0ae94400 0 0x200>,
3952 <0 0x0ae94600 0 0x280>,
3953 <0 0x0ae94a00 0 0x1e0>;
3959 #phy-cells = <0>;
3970 reg = <0 0x0ae96000 0 0x400>;
3998 #size-cells = <0>;
4000 port@0 {
4001 reg = <0>;
4017 reg = <0 0x0ae96400 0 0x200>,
4018 <0 0x0ae96600 0 0x280>,
4019 <0 0x0ae96a00 0 0x10e>;
4025 #phy-cells = <0>;
4039 reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
4049 iommus = <&adreno_smmu 0>;
4055 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
4107 reg = <0 0x5040000 0 0x10000>;
4130 reg = <0 0x506a000 0 0x30000>,
4131 <0 0xb280000 0 0x10000>,
4132 <0 0xb480000 0 0x10000>;
4170 reg = <0 0x0af00000 0 0x10000>;
4174 <&dsi0_phy 0>,
4176 <&dsi1_phy 0>,
4178 <0>,
4179 <0>;
4196 reg = <0 0x0b220000 0 0x30000>;
4197 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4205 reg = <0 0x0b2e0000 0 0x20000>;
4211 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4212 <0 0x0c222000 0 0x1ff>; /* SROT */
4222 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4223 <0 0x0c223000 0 0x1ff>; /* SROT */
4233 reg = <0 0x0c2a0000 0 0x31000>;
4239 reg = <0 0x0c300000 0 0x100000>;
4241 mboxes = <&apss_shared 0>;
4243 #clock-cells = <0>;
4257 reg = <0 0x0c440000 0 0x1100>,
4258 <0 0x0c600000 0 0x2000000>,
4259 <0 0x0e600000 0 0x100000>,
4260 <0 0x0e700000 0 0xa0000>,
4261 <0 0x0c40a000 0 0x26000>;
4265 qcom,ee = <0>;
4266 qcom,channel = <0>;
4268 #size-cells = <0>;
4271 cell-index = <0>;
4276 reg = <0 0x146bf000 0 0x1000>;
4281 ranges = <0 0 0x146bf000 0x1000>;
4285 reg = <0x94c 0xc8>;
4291 reg = <0 0x15000000 0 0x80000>;
4363 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
4371 reg = <0 0x17900000 0 0xd080>;
4378 reg = <0 0x17980000 0 0x1000>;
4384 reg = <0 0x17990000 0 0x1000>;
4391 reg = <0 0x179c0000 0 0x10000>,
4392 <0 0x179d0000 0 0x10000>,
4393 <0 0x179e0000 0 0x10000>;
4394 reg-names = "drv-0", "drv-1", "drv-2";
4398 qcom,tcs-offset = <0xd00>;
4474 reg = <0 0x17a00000 0 0x10000>, /* GICD */
4475 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
4482 reg = <0 0x17a40000 0 0x20000>;
4490 reg = <0 0x17184000 0 0x2a000>;
4496 iommus = <&apps_smmu 0x1806 0x0>;
4504 reg = <0 0x17c90000 0 0x1000>;
4507 frame-number = <0>;
4510 reg = <0 0x17ca0000 0 0x1000>,
4511 <0 0x17cb0000 0 0x1000>;
4517 reg = <0 0x17cc0000 0 0x1000>;
4524 reg = <0 0x17cd0000 0 0x1000>;
4531 reg = <0 0x17ce0000 0 0x1000>;
4538 reg = <0 0x17cf0000 0 0x1000>;
4545 reg = <0 0x17d00000 0 0x1000>;
4552 reg = <0 0x17d10000 0 0x1000>;
4559 reg = <0 0x17d41000 0 0x1400>;
4569 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
4581 reg = <0 0x18800000 0 0x800000>;
4599 iommus = <&apps_smmu 0x0040 0x1>;
4960 thermal-sensors = <&tsens0 0>;
5045 thermal-sensors = <&tsens1 0>;