Lines Matching +full:redistributor +full:- +full:stride
1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
11 interrupt-parent = <&intc>;
13 #address-cells = <2>;
14 #size-cells = <2>;
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
22 clock-frequency = <19200000>;
23 clock-output-names = "xo_board";
27 compatible = "fixed-clock";
28 #clock-cells = <0>;
29 clock-frequency = <32764>;
30 clock-output-names = "sleep_clk";
35 #address-cells = <2>;
36 #size-cells = <0>;
42 enable-method = "psci";
43 capacity-dmips-mhz = <1024>;
44 next-level-cache = <&L2_1>;
45 L2_1: l2-cache {
47 cache-level = <2>;
49 L1_I_100: l1-icache {
52 L1_D_100: l1-dcache {
61 enable-method = "psci";
62 capacity-dmips-mhz = <1024>;
63 next-level-cache = <&L2_1>;
64 L1_I_101: l1-icache {
67 L1_D_101: l1-dcache {
76 enable-method = "psci";
77 capacity-dmips-mhz = <1024>;
78 next-level-cache = <&L2_1>;
79 L1_I_102: l1-icache {
82 L1_D_102: l1-dcache {
91 enable-method = "psci";
92 capacity-dmips-mhz = <1024>;
93 next-level-cache = <&L2_1>;
94 L1_I_103: l1-icache {
97 L1_D_103: l1-dcache {
106 enable-method = "psci";
107 capacity-dmips-mhz = <640>;
108 next-level-cache = <&L2_0>;
109 L2_0: l2-cache {
111 cache-level = <2>;
113 L1_I_0: l1-icache {
116 L1_D_0: l1-dcache {
125 enable-method = "psci";
126 capacity-dmips-mhz = <640>;
127 next-level-cache = <&L2_0>;
128 L1_I_1: l1-icache {
131 L1_D_1: l1-dcache {
140 enable-method = "psci";
141 capacity-dmips-mhz = <640>;
142 next-level-cache = <&L2_0>;
143 L1_I_2: l1-icache {
146 L1_D_2: l1-dcache {
155 enable-method = "psci";
156 capacity-dmips-mhz = <640>;
157 next-level-cache = <&L2_0>;
158 L1_I_3: l1-icache {
161 L1_D_3: l1-dcache {
166 cpu-map {
218 compatible = "arm,psci-1.0";
223 compatible = "arm,armv8-timer";
231 #address-cells = <1>;
232 #size-cells = <1>;
234 compatible = "simple-bus";
236 gcc: clock-controller@100000 {
237 compatible = "qcom,gcc-sdm660";
238 #clock-cells = <1>;
239 #reset-cells = <1>;
240 #power-domain-cells = <1>;
245 compatible = "qcom,sdm660-pinctrl";
249 reg-names = "south", "center", "north";
251 gpio-controller;
252 gpio-ranges = <&tlmm 0 0 114>;
253 #gpio-cells = <2>;
254 interrupt-controller;
255 #interrupt-cells = <2>;
265 drive-strength = <2>;
266 bias-disable;
272 compatible = "qcom,spmi-pmic-arb";
278 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
279 interrupt-names = "periph_irq";
283 #address-cells = <2>;
284 #size-cells = <0>;
285 interrupt-controller;
286 #interrupt-cells = <4>;
287 cell-index = <0>;
291 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
296 clock-names = "core", "iface";
301 #address-cells = <1>;
302 #size-cells = <1>;
304 compatible = "arm,armv7-timer-mem";
308 frame-number = <0>;
316 frame-number = <1>;
323 frame-number = <2>;
330 frame-number = <3>;
337 frame-number = <4>;
344 frame-number = <5>;
351 frame-number = <6>;
358 intc: interrupt-controller@17a00000 {
359 compatible = "arm,gic-v3";
362 #interrupt-cells = <3>;
363 #address-cells = <1>;
364 #size-cells = <1>;
366 interrupt-controller;
367 #redistributor-regions = <1>;
368 redistributor-stride = <0x0 0x20000>;