Lines Matching +full:redistributor +full:- +full:stride
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&intc>;
14 #address-cells = <2>;
15 #size-cells = <2>;
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <19200000>;
24 clock-output-names = "xo_board";
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <32764>;
31 clock-output-names = "sleep_clk";
36 #address-cells = <2>;
37 #size-cells = <0>;
41 compatible = "arm,cortex-a53";
43 enable-method = "psci";
44 cpu-idle-states = <&PERF_CPU_SLEEP_0
49 capacity-dmips-mhz = <1126>;
50 #cooling-cells = <2>;
51 next-level-cache = <&L2_1>;
52 L2_1: l2-cache {
54 cache-level = <2>;
60 compatible = "arm,cortex-a53";
62 enable-method = "psci";
63 cpu-idle-states = <&PERF_CPU_SLEEP_0
68 capacity-dmips-mhz = <1126>;
69 #cooling-cells = <2>;
70 next-level-cache = <&L2_1>;
75 compatible = "arm,cortex-a53";
77 enable-method = "psci";
78 cpu-idle-states = <&PERF_CPU_SLEEP_0
83 capacity-dmips-mhz = <1126>;
84 #cooling-cells = <2>;
85 next-level-cache = <&L2_1>;
90 compatible = "arm,cortex-a53";
92 enable-method = "psci";
93 cpu-idle-states = <&PERF_CPU_SLEEP_0
98 capacity-dmips-mhz = <1126>;
99 #cooling-cells = <2>;
100 next-level-cache = <&L2_1>;
105 compatible = "arm,cortex-a53";
107 enable-method = "psci";
108 cpu-idle-states = <&PWR_CPU_SLEEP_0
113 capacity-dmips-mhz = <1024>;
114 #cooling-cells = <2>;
115 next-level-cache = <&L2_0>;
116 L2_0: l2-cache {
118 cache-level = <2>;
124 compatible = "arm,cortex-a53";
126 enable-method = "psci";
127 cpu-idle-states = <&PWR_CPU_SLEEP_0
132 capacity-dmips-mhz = <1024>;
133 #cooling-cells = <2>;
134 next-level-cache = <&L2_0>;
139 compatible = "arm,cortex-a53";
141 enable-method = "psci";
142 cpu-idle-states = <&PWR_CPU_SLEEP_0
147 capacity-dmips-mhz = <1024>;
148 #cooling-cells = <2>;
149 next-level-cache = <&L2_0>;
154 compatible = "arm,cortex-a53";
156 enable-method = "psci";
157 cpu-idle-states = <&PWR_CPU_SLEEP_0
162 capacity-dmips-mhz = <1024>;
163 #cooling-cells = <2>;
164 next-level-cache = <&L2_0>;
167 cpu-map {
205 idle-states {
206 entry-method = "psci";
208 PWR_CPU_SLEEP_0: cpu-sleep-0-0 {
209 compatible = "arm,idle-state";
210 idle-state-name = "pwr-retention";
211 arm,psci-suspend-param = <0x40000002>;
212 entry-latency-us = <338>;
213 exit-latency-us = <423>;
214 min-residency-us = <200>;
217 PWR_CPU_SLEEP_1: cpu-sleep-0-1 {
218 compatible = "arm,idle-state";
219 idle-state-name = "pwr-power-collapse";
220 arm,psci-suspend-param = <0x40000003>;
221 entry-latency-us = <515>;
222 exit-latency-us = <1821>;
223 min-residency-us = <1000>;
224 local-timer-stop;
227 PERF_CPU_SLEEP_0: cpu-sleep-1-0 {
228 compatible = "arm,idle-state";
229 idle-state-name = "perf-retention";
230 arm,psci-suspend-param = <0x40000002>;
231 entry-latency-us = <154>;
232 exit-latency-us = <87>;
233 min-residency-us = <200>;
236 PERF_CPU_SLEEP_1: cpu-sleep-1-1 {
237 compatible = "arm,idle-state";
238 idle-state-name = "perf-power-collapse";
239 arm,psci-suspend-param = <0x40000003>;
240 entry-latency-us = <262>;
241 exit-latency-us = <301>;
242 min-residency-us = <1000>;
243 local-timer-stop;
246 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 {
247 compatible = "arm,idle-state";
248 idle-state-name = "pwr-cluster-dynamic-retention";
249 arm,psci-suspend-param = <0x400000F2>;
250 entry-latency-us = <284>;
251 exit-latency-us = <384>;
252 min-residency-us = <9987>;
253 local-timer-stop;
256 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 {
257 compatible = "arm,idle-state";
258 idle-state-name = "pwr-cluster-retention";
259 arm,psci-suspend-param = <0x400000F3>;
260 entry-latency-us = <338>;
261 exit-latency-us = <423>;
262 min-residency-us = <9987>;
263 local-timer-stop;
266 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 {
267 compatible = "arm,idle-state";
268 idle-state-name = "pwr-cluster-retention";
269 arm,psci-suspend-param = <0x400000F4>;
270 entry-latency-us = <515>;
271 exit-latency-us = <1821>;
272 min-residency-us = <9987>;
273 local-timer-stop;
276 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 {
277 compatible = "arm,idle-state";
278 idle-state-name = "perf-cluster-dynamic-retention";
279 arm,psci-suspend-param = <0x400000F2>;
280 entry-latency-us = <272>;
281 exit-latency-us = <329>;
282 min-residency-us = <9987>;
283 local-timer-stop;
286 PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 {
287 compatible = "arm,idle-state";
288 idle-state-name = "perf-cluster-retention";
289 arm,psci-suspend-param = <0x400000F3>;
290 entry-latency-us = <332>;
291 exit-latency-us = <368>;
292 min-residency-us = <9987>;
293 local-timer-stop;
296 PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 {
297 compatible = "arm,idle-state";
298 idle-state-name = "perf-cluster-retention";
299 arm,psci-suspend-param = <0x400000F4>;
300 entry-latency-us = <545>;
301 exit-latency-us = <1609>;
302 min-residency-us = <9987>;
303 local-timer-stop;
310 compatible = "qcom,scm-msm8998", "qcom,scm";
321 compatible = "arm,armv8-pmuv3";
326 compatible = "arm,psci-1.0";
330 reserved-memory {
331 #address-cells = <2>;
332 #size-cells = <2>;
335 wlan_msa_guard: wlan-msa-guard@85600000 {
337 no-map;
340 wlan_msa_mem: wlan-msa-mem@85700000 {
342 no-map;
345 qhee_code: qhee-code@85800000 {
347 no-map;
350 smem_region: smem-mem@86000000 {
352 no-map;
357 no-map;
360 modem_fw_mem: modem-fw-region@8ac00000 {
362 no-map;
365 adsp_fw_mem: adsp-fw-region@92a00000 {
367 no-map;
370 pil_mba_mem: pil-mba-region@94800000 {
372 no-map;
375 buffer_mem: buffer-region@94a00000 {
377 no-map;
380 venus_fw_mem: venus-fw-region@9f800000 {
382 no-map;
385 secure_region2: secure-region2@f7c00000 {
387 no-map;
390 adsp_mem: adsp-region@f6000000 {
392 no-map;
395 qseecom_ta_mem: qseecom-ta-region@fec00000 {
397 no-map;
400 qseecom_mem: qseecom-region@f6800000 {
402 no-map;
405 secure_display_memory: secure-region@f5c00000 {
407 no-map;
410 cont_splash_mem: cont-splash-region@9d400000 {
412 no-map;
416 rpm-glink {
417 compatible = "qcom,glink-rpm";
420 qcom,rpm-msg-ram = <&rpm_msg_ram>;
423 rpm_requests: rpm-requests {
424 compatible = "qcom,rpm-sdm660";
425 qcom,glink-channels = "rpm_requests";
427 rpmcc: clock-controller {
428 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc";
429 #clock-cells = <1>;
436 memory-region = <&smem_region>;
441 #address-cells = <1>;
442 #size-cells = <1>;
444 compatible = "simple-bus";
446 gcc: clock-controller@100000 {
447 compatible = "qcom,gcc-sdm630";
448 #clock-cells = <1>;
449 #reset-cells = <1>;
450 #power-domain-cells = <1>;
453 clock-names = "xo", "sleep_clk";
459 compatible = "qcom,rpm-msg-ram";
466 #address-cells = <1>;
467 #size-cells = <1>;
471 compatible = "qcom,prng-ee";
474 clock-names = "core";
483 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
485 #iommu-cells = <1>;
487 #global-interrupts = <2>;
531 compatible = "qcom,sdm630-pinctrl";
534 gpio-controller;
535 #gpio-cells = <0x2>;
536 interrupt-controller;
537 #interrupt-cells = <0x2>;
539 blsp1_uart1_default: blsp1-uart1-default {
541 drive-strength = <2>;
542 bias-disable;
545 blsp1_uart1_sleep: blsp1-uart1-sleep {
547 drive-strength = <2>;
548 bias-disable;
551 blsp1_uart2_default: blsp1-uart2-default {
553 drive-strength = <2>;
554 bias-disable;
557 blsp2_uart1_tx_active: blsp2-uart1-tx-active {
559 drive-strength = <2>;
560 bias-disable;
563 blsp2_uart1_tx_sleep: blsp2-uart1-tx-sleep {
565 drive-strength = <2>;
566 bias-pull-up;
569 blsp2_uart1_rxcts_active: blsp2-uart1-rxcts-active {
571 drive-strength = <2>;
572 bias-disable;
575 blsp2_uart1_rxcts_sleep: blsp2-uart1-rxcts-sleep {
577 drive-strength = <2>;
578 bias-no-pull;
581 blsp2_uart1_rfr_active: blsp2-uart1-rfr-active {
583 drive-strength = <2>;
584 bias-disable;
587 blsp2_uart1_rfr_sleep: blsp2-uart1-rfr-sleep {
589 drive-strength = <2>;
590 bias-no-pull;
593 i2c1_default: i2c1-default {
595 drive-strength = <2>;
596 bias-disable;
599 i2c1_sleep: i2c1-sleep {
601 drive-strength = <2>;
602 bias-pull-up;
605 i2c2_default: i2c2-default {
607 drive-strength = <2>;
608 bias-disable;
611 i2c2_sleep: i2c2-sleep {
613 drive-strength = <2>;
614 bias-pull-up;
617 i2c3_default: i2c3-default {
619 drive-strength = <2>;
620 bias-disable;
623 i2c3_sleep: i2c3-sleep {
625 drive-strength = <2>;
626 bias-pull-up;
629 i2c4_default: i2c4-default {
631 drive-strength = <2>;
632 bias-disable;
635 i2c4_sleep: i2c4-sleep {
637 drive-strength = <2>;
638 bias-pull-up;
641 i2c5_default: i2c5-default {
643 drive-strength = <2>;
644 bias-disable;
647 i2c5_sleep: i2c5-sleep {
649 drive-strength = <2>;
650 bias-pull-up;
653 i2c6_default: i2c6-default {
655 drive-strength = <2>;
656 bias-disable;
659 i2c6_sleep: i2c6-sleep {
661 drive-strength = <2>;
662 bias-pull-up;
665 i2c7_default: i2c7-default {
667 drive-strength = <2>;
668 bias-disable;
671 i2c7_sleep: i2c7-sleep {
673 drive-strength = <2>;
674 bias-pull-up;
677 i2c8_default: i2c8-default {
679 drive-strength = <2>;
680 bias-disable;
683 i2c8_sleep: i2c8-sleep {
685 drive-strength = <2>;
686 bias-pull-up;
689 sdc1_clk_on: sdc1-clk-on {
691 bias-disable;
692 drive-strength = <16>;
695 sdc1_clk_off: sdc1-clk-off {
697 bias-disable;
698 drive-strength = <2>;
701 sdc1_cmd_on: sdc1-cmd-on {
703 bias-pull-up;
704 drive-strength = <10>;
707 sdc1_cmd_off: sdc1-cmd-off {
709 bias-pull-up;
710 drive-strength = <2>;
713 sdc1_data_on: sdc1-data-on {
715 bias-pull-up;
716 drive-strength = <8>;
719 sdc1_data_off: sdc1-data-off {
721 bias-pull-up;
722 drive-strength = <2>;
725 sdc1_rclk_on: sdc1-rclk-on {
727 bias-pull-down;
730 sdc1_rclk_off: sdc1-rclk-off {
732 bias-pull-down;
737 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
739 #iommu-cells = <1>;
741 #global-interrupts = <2>;
759 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
761 #iommu-cells = <1>;
763 #global-interrupts = <2>;
790 compatible = "qcom,spmi-pmic-arb";
796 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
797 interrupt-names = "periph_irq";
801 #address-cells = <2>;
802 #size-cells = <0>;
803 interrupt-controller;
804 #interrupt-cells = <4>;
805 cell-index = <0>;
809 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
812 reg-names = "hc", "cqhci";
816 interrupt-names = "hc_irq", "pwr_irq";
821 clock-names = "core", "iface", "xo";
823 pinctrl-names = "default", "sleep";
824 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
825 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
827 bus-width = <8>;
828 non-removable;
834 compatible = "qcom,bam-v1.7.0";
838 clock-names = "bam_clk";
839 #dma-cells = <1>;
841 qcom,controlled-remotely;
842 num-channels = <18>;
843 qcom,num-ees = <4>;
847 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
852 clock-names = "core", "iface";
854 dma-names = "tx", "rx";
855 pinctrl-names = "default", "sleep";
856 pinctrl-0 = <&blsp1_uart1_default>;
857 pinctrl-1 = <&blsp1_uart1_sleep>;
862 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
867 clock-names = "core", "iface";
869 dma-names = "tx", "rx";
870 pinctrl-names = "default";
871 pinctrl-0 = <&blsp1_uart2_default>;
876 compatible = "qcom,i2c-qup-v2.2.1";
882 clock-names = "core", "iface";
883 clock-frequency = <400000>;
885 pinctrl-names = "default", "sleep";
886 pinctrl-0 = <&i2c1_default>;
887 pinctrl-1 = <&i2c1_sleep>;
888 #address-cells = <1>;
889 #size-cells = <0>;
894 compatible = "qcom,i2c-qup-v2.2.1";
900 clock-names = "core", "iface";
901 clock-frequency = <400000>;
903 pinctrl-names = "default", "sleep";
904 pinctrl-0 = <&i2c2_default>;
905 pinctrl-1 = <&i2c2_sleep>;
906 #address-cells = <1>;
907 #size-cells = <0>;
912 compatible = "qcom,i2c-qup-v2.2.1";
918 clock-names = "core", "iface";
919 clock-frequency = <400000>;
921 pinctrl-names = "default", "sleep";
922 pinctrl-0 = <&i2c3_default>;
923 pinctrl-1 = <&i2c3_sleep>;
924 #address-cells = <1>;
925 #size-cells = <0>;
930 compatible = "qcom,i2c-qup-v2.2.1";
936 clock-names = "core", "iface";
937 clock-frequency = <400000>;
939 pinctrl-names = "default", "sleep";
940 pinctrl-0 = <&i2c4_default>;
941 pinctrl-1 = <&i2c4_sleep>;
942 #address-cells = <1>;
943 #size-cells = <0>;
948 compatible = "qcom,bam-v1.7.0";
952 clock-names = "bam_clk";
953 #dma-cells = <1>;
955 qcom,controlled-remotely;
956 num-channels = <18>;
957 qcom,num-ees = <4>;
961 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
966 clock-names = "core", "iface";
968 dma-names = "tx", "rx";
969 pinctrl-names = "default", "sleep";
970 pinctrl-0 = <&blsp2_uart1_tx_active &blsp2_uart1_rxcts_active
972 pinctrl-1 = <&blsp2_uart1_tx_sleep &blsp2_uart1_rxcts_sleep
978 compatible = "qcom,i2c-qup-v2.2.1";
984 clock-names = "core", "iface";
985 clock-frequency = <400000>;
987 pinctrl-names = "default", "sleep";
988 pinctrl-0 = <&i2c5_default>;
989 pinctrl-1 = <&i2c5_sleep>;
990 #address-cells = <1>;
991 #size-cells = <0>;
996 compatible = "qcom,i2c-qup-v2.2.1";
1002 clock-names = "core", "iface";
1003 clock-frequency = <400000>;
1005 pinctrl-names = "default", "sleep";
1006 pinctrl-0 = <&i2c6_default>;
1007 pinctrl-1 = <&i2c6_sleep>;
1008 #address-cells = <1>;
1009 #size-cells = <0>;
1014 compatible = "qcom,i2c-qup-v2.2.1";
1020 clock-names = "core", "iface";
1021 clock-frequency = <400000>;
1023 pinctrl-names = "default", "sleep";
1024 pinctrl-0 = <&i2c7_default>;
1025 pinctrl-1 = <&i2c7_sleep>;
1026 #address-cells = <1>;
1027 #size-cells = <0>;
1032 compatible = "qcom,i2c-qup-v2.2.1";
1038 clock-names = "core", "iface";
1039 clock-frequency = <400000>;
1041 pinctrl-names = "default", "sleep";
1042 pinctrl-0 = <&i2c8_default>;
1043 pinctrl-1 = <&i2c8_sleep>;
1044 #address-cells = <1>;
1045 #size-cells = <0>;
1050 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
1052 #iommu-cells = <1>;
1054 #global-interrupts = <2>;
1088 compatible = "qcom,sdm660-apcs-hmss-global";
1091 #mbox-cells = <1>;
1095 #address-cells = <1>;
1096 #size-cells = <1>;
1098 compatible = "arm,armv7-timer-mem";
1100 clock-frequency = <19200000>;
1103 frame-number = <0>;
1111 frame-number = <1>;
1118 frame-number = <2>;
1125 frame-number = <3>;
1132 frame-number = <4>;
1139 frame-number = <5>;
1146 frame-number = <6>;
1153 intc: interrupt-controller@17a00000 {
1154 compatible = "arm,gic-v3";
1157 #interrupt-cells = <3>;
1158 #address-cells = <1>;
1159 #size-cells = <1>;
1161 interrupt-controller;
1162 #redistributor-regions = <1>;
1163 redistributor-stride = <0x0 0x20000>;
1169 compatible = "qcom,tcsr-mutex";
1171 #hwlock-cells = <1>;
1175 compatible = "arm,armv8-timer";