Lines Matching +full:sc7180 +full:- +full:lpasshm
1 // SPDX-License-Identifier: BSD-3-Clause
3 * SC7180 SoC device tree source
8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
15 #include <dt-bindings/interconnect/qcom,sc7180.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/phy/phy-qcom-qusb2.h>
18 #include <dt-bindings/power/qcom-aoss-qmp.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
21 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
23 #include <dt-bindings/thermal/thermal.h>
26 interrupt-parent = <&intc>;
28 #address-cells = <2>;
29 #size-cells = <2>;
57 xo_board: xo-board {
58 compatible = "fixed-clock";
59 clock-frequency = <38400000>;
60 #clock-cells = <0>;
63 sleep_clk: sleep-clk {
64 compatible = "fixed-clock";
65 clock-frequency = <32764>;
66 #clock-cells = <0>;
70 reserved_memory: reserved-memory {
71 #address-cells = <2>;
72 #size-cells = <2>;
77 no-map;
82 no-map;
87 no-map;
92 compatible = "qcom,cmd-db";
93 no-map;
98 no-map;
103 no-map;
108 no-map;
112 compatible = "qcom,rmtfs-mem";
114 no-map;
116 qcom,client-id = <1>;
122 #address-cells = <2>;
123 #size-cells = <0>;
129 enable-method = "psci";
130 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
133 capacity-dmips-mhz = <1024>;
134 dynamic-power-coefficient = <100>;
135 operating-points-v2 = <&cpu0_opp_table>;
138 next-level-cache = <&L2_0>;
139 #cooling-cells = <2>;
140 qcom,freq-domain = <&cpufreq_hw 0>;
141 L2_0: l2-cache {
143 next-level-cache = <&L3_0>;
144 L3_0: l3-cache {
154 enable-method = "psci";
155 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
158 capacity-dmips-mhz = <1024>;
159 dynamic-power-coefficient = <100>;
160 next-level-cache = <&L2_100>;
161 operating-points-v2 = <&cpu0_opp_table>;
164 #cooling-cells = <2>;
165 qcom,freq-domain = <&cpufreq_hw 0>;
166 L2_100: l2-cache {
168 next-level-cache = <&L3_0>;
176 enable-method = "psci";
177 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
180 capacity-dmips-mhz = <1024>;
181 dynamic-power-coefficient = <100>;
182 next-level-cache = <&L2_200>;
183 operating-points-v2 = <&cpu0_opp_table>;
186 #cooling-cells = <2>;
187 qcom,freq-domain = <&cpufreq_hw 0>;
188 L2_200: l2-cache {
190 next-level-cache = <&L3_0>;
198 enable-method = "psci";
199 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
202 capacity-dmips-mhz = <1024>;
203 dynamic-power-coefficient = <100>;
204 next-level-cache = <&L2_300>;
205 operating-points-v2 = <&cpu0_opp_table>;
208 #cooling-cells = <2>;
209 qcom,freq-domain = <&cpufreq_hw 0>;
210 L2_300: l2-cache {
212 next-level-cache = <&L3_0>;
220 enable-method = "psci";
221 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
224 capacity-dmips-mhz = <1024>;
225 dynamic-power-coefficient = <100>;
226 next-level-cache = <&L2_400>;
227 operating-points-v2 = <&cpu0_opp_table>;
230 #cooling-cells = <2>;
231 qcom,freq-domain = <&cpufreq_hw 0>;
232 L2_400: l2-cache {
234 next-level-cache = <&L3_0>;
242 enable-method = "psci";
243 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
246 capacity-dmips-mhz = <1024>;
247 dynamic-power-coefficient = <100>;
248 next-level-cache = <&L2_500>;
249 operating-points-v2 = <&cpu0_opp_table>;
252 #cooling-cells = <2>;
253 qcom,freq-domain = <&cpufreq_hw 0>;
254 L2_500: l2-cache {
256 next-level-cache = <&L3_0>;
264 enable-method = "psci";
265 cpu-idle-states = <&BIG_CPU_SLEEP_0
268 capacity-dmips-mhz = <1740>;
269 dynamic-power-coefficient = <405>;
270 next-level-cache = <&L2_600>;
271 operating-points-v2 = <&cpu6_opp_table>;
274 #cooling-cells = <2>;
275 qcom,freq-domain = <&cpufreq_hw 1>;
276 L2_600: l2-cache {
278 next-level-cache = <&L3_0>;
286 enable-method = "psci";
287 cpu-idle-states = <&BIG_CPU_SLEEP_0
290 capacity-dmips-mhz = <1740>;
291 dynamic-power-coefficient = <405>;
292 next-level-cache = <&L2_700>;
293 operating-points-v2 = <&cpu6_opp_table>;
296 #cooling-cells = <2>;
297 qcom,freq-domain = <&cpufreq_hw 1>;
298 L2_700: l2-cache {
300 next-level-cache = <&L3_0>;
304 cpu-map {
340 idle-states {
341 entry-method = "psci";
343 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
344 compatible = "arm,idle-state";
345 idle-state-name = "little-power-down";
346 arm,psci-suspend-param = <0x40000003>;
347 entry-latency-us = <549>;
348 exit-latency-us = <901>;
349 min-residency-us = <1774>;
350 local-timer-stop;
353 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
354 compatible = "arm,idle-state";
355 idle-state-name = "little-rail-power-down";
356 arm,psci-suspend-param = <0x40000004>;
357 entry-latency-us = <702>;
358 exit-latency-us = <915>;
359 min-residency-us = <4001>;
360 local-timer-stop;
363 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
364 compatible = "arm,idle-state";
365 idle-state-name = "big-power-down";
366 arm,psci-suspend-param = <0x40000003>;
367 entry-latency-us = <523>;
368 exit-latency-us = <1244>;
369 min-residency-us = <2207>;
370 local-timer-stop;
373 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
374 compatible = "arm,idle-state";
375 idle-state-name = "big-rail-power-down";
376 arm,psci-suspend-param = <0x40000004>;
377 entry-latency-us = <526>;
378 exit-latency-us = <1854>;
379 min-residency-us = <5555>;
380 local-timer-stop;
383 CLUSTER_SLEEP_0: cluster-sleep-0 {
384 compatible = "arm,idle-state";
385 idle-state-name = "cluster-power-down";
386 arm,psci-suspend-param = <0x40003444>;
387 entry-latency-us = <3263>;
388 exit-latency-us = <6562>;
389 min-residency-us = <9926>;
390 local-timer-stop;
396 compatible = "operating-points-v2";
397 opp-shared;
399 cpu0_opp1: opp-300000000 {
400 opp-hz = /bits/ 64 <300000000>;
401 opp-peak-kBps = <1200000 4800000>;
404 cpu0_opp2: opp-576000000 {
405 opp-hz = /bits/ 64 <576000000>;
406 opp-peak-kBps = <1200000 4800000>;
409 cpu0_opp3: opp-768000000 {
410 opp-hz = /bits/ 64 <768000000>;
411 opp-peak-kBps = <1200000 4800000>;
414 cpu0_opp4: opp-1017600000 {
415 opp-hz = /bits/ 64 <1017600000>;
416 opp-peak-kBps = <1804000 8908800>;
419 cpu0_opp5: opp-1248000000 {
420 opp-hz = /bits/ 64 <1248000000>;
421 opp-peak-kBps = <2188000 12902400>;
424 cpu0_opp6: opp-1324800000 {
425 opp-hz = /bits/ 64 <1324800000>;
426 opp-peak-kBps = <2188000 12902400>;
429 cpu0_opp7: opp-1516800000 {
430 opp-hz = /bits/ 64 <1516800000>;
431 opp-peak-kBps = <3072000 15052800>;
434 cpu0_opp8: opp-1612800000 {
435 opp-hz = /bits/ 64 <1612800000>;
436 opp-peak-kBps = <3072000 15052800>;
439 cpu0_opp9: opp-1708800000 {
440 opp-hz = /bits/ 64 <1708800000>;
441 opp-peak-kBps = <3072000 15052800>;
444 cpu0_opp10: opp-1804800000 {
445 opp-hz = /bits/ 64 <1804800000>;
446 opp-peak-kBps = <4068000 22425600>;
451 compatible = "operating-points-v2";
452 opp-shared;
454 cpu6_opp1: opp-300000000 {
455 opp-hz = /bits/ 64 <300000000>;
456 opp-peak-kBps = <2188000 8908800>;
459 cpu6_opp2: opp-652800000 {
460 opp-hz = /bits/ 64 <652800000>;
461 opp-peak-kBps = <2188000 8908800>;
464 cpu6_opp3: opp-825600000 {
465 opp-hz = /bits/ 64 <825600000>;
466 opp-peak-kBps = <2188000 8908800>;
469 cpu6_opp4: opp-979200000 {
470 opp-hz = /bits/ 64 <979200000>;
471 opp-peak-kBps = <2188000 8908800>;
474 cpu6_opp5: opp-1113600000 {
475 opp-hz = /bits/ 64 <1113600000>;
476 opp-peak-kBps = <2188000 8908800>;
479 cpu6_opp6: opp-1267200000 {
480 opp-hz = /bits/ 64 <1267200000>;
481 opp-peak-kBps = <4068000 12902400>;
484 cpu6_opp7: opp-1555200000 {
485 opp-hz = /bits/ 64 <1555200000>;
486 opp-peak-kBps = <4068000 15052800>;
489 cpu6_opp8: opp-1708800000 {
490 opp-hz = /bits/ 64 <1708800000>;
491 opp-peak-kBps = <6220000 19353600>;
494 cpu6_opp9: opp-1843200000 {
495 opp-hz = /bits/ 64 <1843200000>;
496 opp-peak-kBps = <6220000 19353600>;
499 cpu6_opp10: opp-1900800000 {
500 opp-hz = /bits/ 64 <1900800000>;
501 opp-peak-kBps = <6220000 22425600>;
504 cpu6_opp11: opp-1996800000 {
505 opp-hz = /bits/ 64 <1996800000>;
506 opp-peak-kBps = <6220000 22425600>;
509 cpu6_opp12: opp-2112000000 {
510 opp-hz = /bits/ 64 <2112000000>;
511 opp-peak-kBps = <6220000 22425600>;
514 cpu6_opp13: opp-2208000000 {
515 opp-hz = /bits/ 64 <2208000000>;
516 opp-peak-kBps = <7216000 22425600>;
519 cpu6_opp14: opp-2323200000 {
520 opp-hz = /bits/ 64 <2323200000>;
521 opp-peak-kBps = <7216000 22425600>;
524 cpu6_opp15: opp-2400000000 {
525 opp-hz = /bits/ 64 <2400000000>;
526 opp-peak-kBps = <8532000 23347200>;
537 compatible = "arm,armv8-pmuv3";
543 compatible = "qcom,scm-sc7180", "qcom,scm";
548 compatible = "qcom,tcsr-mutex";
550 #hwlock-cells = <1>;
555 memory-region = <&smem_mem>;
559 smp2p-cdsp {
567 qcom,local-pid = <0>;
568 qcom,remote-pid = <5>;
570 cdsp_smp2p_out: master-kernel {
571 qcom,entry-name = "master-kernel";
572 #qcom,smem-state-cells = <1>;
575 cdsp_smp2p_in: slave-kernel {
576 qcom,entry-name = "slave-kernel";
578 interrupt-controller;
579 #interrupt-cells = <2>;
583 smp2p-lpass {
591 qcom,local-pid = <0>;
592 qcom,remote-pid = <2>;
594 adsp_smp2p_out: master-kernel {
595 qcom,entry-name = "master-kernel";
596 #qcom,smem-state-cells = <1>;
599 adsp_smp2p_in: slave-kernel {
600 qcom,entry-name = "slave-kernel";
602 interrupt-controller;
603 #interrupt-cells = <2>;
607 smp2p-mpss {
612 qcom,local-pid = <0>;
613 qcom,remote-pid = <1>;
615 modem_smp2p_out: master-kernel {
616 qcom,entry-name = "master-kernel";
617 #qcom,smem-state-cells = <1>;
620 modem_smp2p_in: slave-kernel {
621 qcom,entry-name = "slave-kernel";
622 interrupt-controller;
623 #interrupt-cells = <2>;
626 ipa_smp2p_out: ipa-ap-to-modem {
627 qcom,entry-name = "ipa";
628 #qcom,smem-state-cells = <1>;
631 ipa_smp2p_in: ipa-modem-to-ap {
632 qcom,entry-name = "ipa";
633 interrupt-controller;
634 #interrupt-cells = <2>;
639 compatible = "arm,psci-1.0";
644 #address-cells = <2>;
645 #size-cells = <2>;
647 dma-ranges = <0 0 0 0 0x10 0>;
648 compatible = "simple-bus";
650 gcc: clock-controller@100000 {
651 compatible = "qcom,gcc-sc7180";
656 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
657 #clock-cells = <1>;
658 #reset-cells = <1>;
659 #power-domain-cells = <1>;
670 clock-names = "core";
671 #address-cells = <1>;
672 #size-cells = <1>;
674 qusb2p_hstx_trim: hstx-trim-primary@25b {
681 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
684 reg-names = "hc", "cqhci";
689 interrupt-names = "hc_irq", "pwr_irq";
693 clock-names = "core", "iface";
696 interconnect-names = "sdhc-ddr","cpu-sdhc";
697 power-domains = <&rpmhpd SC7180_CX>;
698 operating-points-v2 = <&sdhc1_opp_table>;
700 bus-width = <8>;
701 non-removable;
702 supports-cqe;
704 mmc-ddr-1_8v;
705 mmc-hs200-1_8v;
706 mmc-hs400-1_8v;
707 mmc-hs400-enhanced-strobe;
711 sdhc1_opp_table: sdhc1-opp-table {
712 compatible = "operating-points-v2";
714 opp-100000000 {
715 opp-hz = /bits/ 64 <100000000>;
716 required-opps = <&rpmhpd_opp_low_svs>;
717 opp-peak-kBps = <100000 100000>;
718 opp-avg-kBps = <100000 50000>;
721 opp-384000000 {
722 opp-hz = /bits/ 64 <384000000>;
723 required-opps = <&rpmhpd_opp_svs_l1>;
724 opp-peak-kBps = <600000 900000>;
725 opp-avg-kBps = <261438 300000>;
730 qup_opp_table: qup-opp-table {
731 compatible = "operating-points-v2";
733 opp-75000000 {
734 opp-hz = /bits/ 64 <75000000>;
735 required-opps = <&rpmhpd_opp_low_svs>;
738 opp-100000000 {
739 opp-hz = /bits/ 64 <100000000>;
740 required-opps = <&rpmhpd_opp_svs>;
743 opp-128000000 {
744 opp-hz = /bits/ 64 <128000000>;
745 required-opps = <&rpmhpd_opp_nom>;
750 compatible = "qcom,geni-se-qup";
752 clock-names = "m-ahb", "s-ahb";
755 #address-cells = <2>;
756 #size-cells = <2>;
760 interconnect-names = "qup-core";
764 compatible = "qcom,geni-i2c";
766 clock-names = "se";
768 pinctrl-names = "default";
769 pinctrl-0 = <&qup_i2c0_default>;
771 #address-cells = <1>;
772 #size-cells = <0>;
776 interconnect-names = "qup-core", "qup-config",
777 "qup-memory";
782 compatible = "qcom,geni-spi";
784 clock-names = "se";
786 pinctrl-names = "default";
787 pinctrl-0 = <&qup_spi0_default>;
789 #address-cells = <1>;
790 #size-cells = <0>;
791 power-domains = <&rpmhpd SC7180_CX>;
792 operating-points-v2 = <&qup_opp_table>;
795 interconnect-names = "qup-core", "qup-config";
800 compatible = "qcom,geni-uart";
802 clock-names = "se";
804 pinctrl-names = "default";
805 pinctrl-0 = <&qup_uart0_default>;
807 power-domains = <&rpmhpd SC7180_CX>;
808 operating-points-v2 = <&qup_opp_table>;
811 interconnect-names = "qup-core", "qup-config";
816 compatible = "qcom,geni-i2c";
818 clock-names = "se";
820 pinctrl-names = "default";
821 pinctrl-0 = <&qup_i2c1_default>;
823 #address-cells = <1>;
824 #size-cells = <0>;
828 interconnect-names = "qup-core", "qup-config",
829 "qup-memory";
834 compatible = "qcom,geni-spi";
836 clock-names = "se";
838 pinctrl-names = "default";
839 pinctrl-0 = <&qup_spi1_default>;
841 #address-cells = <1>;
842 #size-cells = <0>;
843 power-domains = <&rpmhpd SC7180_CX>;
844 operating-points-v2 = <&qup_opp_table>;
847 interconnect-names = "qup-core", "qup-config";
852 compatible = "qcom,geni-uart";
854 clock-names = "se";
856 pinctrl-names = "default";
857 pinctrl-0 = <&qup_uart1_default>;
859 power-domains = <&rpmhpd SC7180_CX>;
860 operating-points-v2 = <&qup_opp_table>;
863 interconnect-names = "qup-core", "qup-config";
868 compatible = "qcom,geni-i2c";
870 clock-names = "se";
872 pinctrl-names = "default";
873 pinctrl-0 = <&qup_i2c2_default>;
875 #address-cells = <1>;
876 #size-cells = <0>;
880 interconnect-names = "qup-core", "qup-config",
881 "qup-memory";
886 compatible = "qcom,geni-uart";
888 clock-names = "se";
890 pinctrl-names = "default";
891 pinctrl-0 = <&qup_uart2_default>;
893 power-domains = <&rpmhpd SC7180_CX>;
894 operating-points-v2 = <&qup_opp_table>;
897 interconnect-names = "qup-core", "qup-config";
902 compatible = "qcom,geni-i2c";
904 clock-names = "se";
906 pinctrl-names = "default";
907 pinctrl-0 = <&qup_i2c3_default>;
909 #address-cells = <1>;
910 #size-cells = <0>;
914 interconnect-names = "qup-core", "qup-config",
915 "qup-memory";
920 compatible = "qcom,geni-spi";
922 clock-names = "se";
924 pinctrl-names = "default";
925 pinctrl-0 = <&qup_spi3_default>;
927 #address-cells = <1>;
928 #size-cells = <0>;
929 power-domains = <&rpmhpd SC7180_CX>;
930 operating-points-v2 = <&qup_opp_table>;
933 interconnect-names = "qup-core", "qup-config";
938 compatible = "qcom,geni-uart";
940 clock-names = "se";
942 pinctrl-names = "default";
943 pinctrl-0 = <&qup_uart3_default>;
945 power-domains = <&rpmhpd SC7180_CX>;
946 operating-points-v2 = <&qup_opp_table>;
949 interconnect-names = "qup-core", "qup-config";
954 compatible = "qcom,geni-i2c";
956 clock-names = "se";
958 pinctrl-names = "default";
959 pinctrl-0 = <&qup_i2c4_default>;
961 #address-cells = <1>;
962 #size-cells = <0>;
966 interconnect-names = "qup-core", "qup-config",
967 "qup-memory";
972 compatible = "qcom,geni-uart";
974 clock-names = "se";
976 pinctrl-names = "default";
977 pinctrl-0 = <&qup_uart4_default>;
979 power-domains = <&rpmhpd SC7180_CX>;
980 operating-points-v2 = <&qup_opp_table>;
983 interconnect-names = "qup-core", "qup-config";
988 compatible = "qcom,geni-i2c";
990 clock-names = "se";
992 pinctrl-names = "default";
993 pinctrl-0 = <&qup_i2c5_default>;
995 #address-cells = <1>;
996 #size-cells = <0>;
1000 interconnect-names = "qup-core", "qup-config",
1001 "qup-memory";
1006 compatible = "qcom,geni-spi";
1008 clock-names = "se";
1010 pinctrl-names = "default";
1011 pinctrl-0 = <&qup_spi5_default>;
1013 #address-cells = <1>;
1014 #size-cells = <0>;
1015 power-domains = <&rpmhpd SC7180_CX>;
1016 operating-points-v2 = <&qup_opp_table>;
1019 interconnect-names = "qup-core", "qup-config";
1024 compatible = "qcom,geni-uart";
1026 clock-names = "se";
1028 pinctrl-names = "default";
1029 pinctrl-0 = <&qup_uart5_default>;
1031 power-domains = <&rpmhpd SC7180_CX>;
1032 operating-points-v2 = <&qup_opp_table>;
1035 interconnect-names = "qup-core", "qup-config";
1041 compatible = "qcom,geni-se-qup";
1043 clock-names = "m-ahb", "s-ahb";
1046 #address-cells = <2>;
1047 #size-cells = <2>;
1051 interconnect-names = "qup-core";
1055 compatible = "qcom,geni-i2c";
1057 clock-names = "se";
1059 pinctrl-names = "default";
1060 pinctrl-0 = <&qup_i2c6_default>;
1062 #address-cells = <1>;
1063 #size-cells = <0>;
1067 interconnect-names = "qup-core", "qup-config",
1068 "qup-memory";
1073 compatible = "qcom,geni-spi";
1075 clock-names = "se";
1077 pinctrl-names = "default";
1078 pinctrl-0 = <&qup_spi6_default>;
1080 #address-cells = <1>;
1081 #size-cells = <0>;
1082 power-domains = <&rpmhpd SC7180_CX>;
1083 operating-points-v2 = <&qup_opp_table>;
1086 interconnect-names = "qup-core", "qup-config";
1091 compatible = "qcom,geni-uart";
1093 clock-names = "se";
1095 pinctrl-names = "default";
1096 pinctrl-0 = <&qup_uart6_default>;
1098 power-domains = <&rpmhpd SC7180_CX>;
1099 operating-points-v2 = <&qup_opp_table>;
1102 interconnect-names = "qup-core", "qup-config";
1107 compatible = "qcom,geni-i2c";
1109 clock-names = "se";
1111 pinctrl-names = "default";
1112 pinctrl-0 = <&qup_i2c7_default>;
1114 #address-cells = <1>;
1115 #size-cells = <0>;
1119 interconnect-names = "qup-core", "qup-config",
1120 "qup-memory";
1125 compatible = "qcom,geni-uart";
1127 clock-names = "se";
1129 pinctrl-names = "default";
1130 pinctrl-0 = <&qup_uart7_default>;
1132 power-domains = <&rpmhpd SC7180_CX>;
1133 operating-points-v2 = <&qup_opp_table>;
1136 interconnect-names = "qup-core", "qup-config";
1141 compatible = "qcom,geni-i2c";
1143 clock-names = "se";
1145 pinctrl-names = "default";
1146 pinctrl-0 = <&qup_i2c8_default>;
1148 #address-cells = <1>;
1149 #size-cells = <0>;
1153 interconnect-names = "qup-core", "qup-config",
1154 "qup-memory";
1159 compatible = "qcom,geni-spi";
1161 clock-names = "se";
1163 pinctrl-names = "default";
1164 pinctrl-0 = <&qup_spi8_default>;
1166 #address-cells = <1>;
1167 #size-cells = <0>;
1168 power-domains = <&rpmhpd SC7180_CX>;
1169 operating-points-v2 = <&qup_opp_table>;
1172 interconnect-names = "qup-core", "qup-config";
1177 compatible = "qcom,geni-debug-uart";
1179 clock-names = "se";
1181 pinctrl-names = "default";
1182 pinctrl-0 = <&qup_uart8_default>;
1184 power-domains = <&rpmhpd SC7180_CX>;
1185 operating-points-v2 = <&qup_opp_table>;
1188 interconnect-names = "qup-core", "qup-config";
1193 compatible = "qcom,geni-i2c";
1195 clock-names = "se";
1197 pinctrl-names = "default";
1198 pinctrl-0 = <&qup_i2c9_default>;
1200 #address-cells = <1>;
1201 #size-cells = <0>;
1205 interconnect-names = "qup-core", "qup-config",
1206 "qup-memory";
1211 compatible = "qcom,geni-uart";
1213 clock-names = "se";
1215 pinctrl-names = "default";
1216 pinctrl-0 = <&qup_uart9_default>;
1218 power-domains = <&rpmhpd SC7180_CX>;
1219 operating-points-v2 = <&qup_opp_table>;
1222 interconnect-names = "qup-core", "qup-config";
1227 compatible = "qcom,geni-i2c";
1229 clock-names = "se";
1231 pinctrl-names = "default";
1232 pinctrl-0 = <&qup_i2c10_default>;
1234 #address-cells = <1>;
1235 #size-cells = <0>;
1239 interconnect-names = "qup-core", "qup-config",
1240 "qup-memory";
1245 compatible = "qcom,geni-spi";
1247 clock-names = "se";
1249 pinctrl-names = "default";
1250 pinctrl-0 = <&qup_spi10_default>;
1252 #address-cells = <1>;
1253 #size-cells = <0>;
1254 power-domains = <&rpmhpd SC7180_CX>;
1255 operating-points-v2 = <&qup_opp_table>;
1258 interconnect-names = "qup-core", "qup-config";
1263 compatible = "qcom,geni-uart";
1265 clock-names = "se";
1267 pinctrl-names = "default";
1268 pinctrl-0 = <&qup_uart10_default>;
1270 power-domains = <&rpmhpd SC7180_CX>;
1271 operating-points-v2 = <&qup_opp_table>;
1274 interconnect-names = "qup-core", "qup-config";
1279 compatible = "qcom,geni-i2c";
1281 clock-names = "se";
1283 pinctrl-names = "default";
1284 pinctrl-0 = <&qup_i2c11_default>;
1286 #address-cells = <1>;
1287 #size-cells = <0>;
1291 interconnect-names = "qup-core", "qup-config",
1292 "qup-memory";
1297 compatible = "qcom,geni-spi";
1299 clock-names = "se";
1301 pinctrl-names = "default";
1302 pinctrl-0 = <&qup_spi11_default>;
1304 #address-cells = <1>;
1305 #size-cells = <0>;
1306 power-domains = <&rpmhpd SC7180_CX>;
1307 operating-points-v2 = <&qup_opp_table>;
1310 interconnect-names = "qup-core", "qup-config";
1315 compatible = "qcom,geni-uart";
1317 clock-names = "se";
1319 pinctrl-names = "default";
1320 pinctrl-0 = <&qup_uart11_default>;
1322 power-domains = <&rpmhpd SC7180_CX>;
1323 operating-points-v2 = <&qup_opp_table>;
1326 interconnect-names = "qup-core", "qup-config";
1332 compatible = "qcom,sc7180-config-noc";
1334 #interconnect-cells = <2>;
1335 qcom,bcm-voters = <&apps_bcm_voter>;
1339 compatible = "qcom,sc7180-system-noc";
1341 #interconnect-cells = <2>;
1342 qcom,bcm-voters = <&apps_bcm_voter>;
1346 compatible = "qcom,sc7180-mc-virt";
1348 #interconnect-cells = <2>;
1349 qcom,bcm-voters = <&apps_bcm_voter>;
1353 compatible = "qcom,sc7180-qup-virt";
1355 #interconnect-cells = <2>;
1356 qcom,bcm-voters = <&apps_bcm_voter>;
1360 compatible = "qcom,sc7180-aggre1-noc";
1362 #interconnect-cells = <2>;
1363 qcom,bcm-voters = <&apps_bcm_voter>;
1367 compatible = "qcom,sc7180-aggre2-noc";
1369 #interconnect-cells = <2>;
1370 qcom,bcm-voters = <&apps_bcm_voter>;
1374 compatible = "qcom,sc7180-compute-noc";
1376 #interconnect-cells = <2>;
1377 qcom,bcm-voters = <&apps_bcm_voter>;
1381 compatible = "qcom,sc7180-mmss-noc";
1383 #interconnect-cells = <2>;
1384 qcom,bcm-voters = <&apps_bcm_voter>;
1388 compatible = "qcom,sc7180-ipa-virt";
1390 #interconnect-cells = <2>;
1391 qcom,bcm-voters = <&apps_bcm_voter>;
1395 compatible = "qcom,sc7180-ipa";
1401 reg-names = "ipa-reg",
1402 "ipa-shared",
1405 interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>,
1409 interrupt-names = "ipa",
1411 "ipa-clock-query",
1412 "ipa-setup-ready";
1415 clock-names = "core";
1420 interconnect-names = "memory",
1424 qcom,smem-states = <&ipa_smp2p_out 0>,
1426 qcom,smem-state-names = "ipa-clock-enabled-valid",
1427 "ipa-clock-enabled";
1429 modem-remoteproc = <&remoteproc_mpss>;
1445 compatible = "qcom,sc7180-pinctrl";
1449 reg-names = "west", "north", "south";
1451 gpio-controller;
1452 #gpio-cells = <2>;
1453 interrupt-controller;
1454 #interrupt-cells = <2>;
1455 gpio-ranges = <&tlmm 0 0 120>;
1456 wakeup-parent = <&pdc>;
1458 dp_hot_plug_det: dp-hot-plug-det {
1466 bias-disable;
1467 input-enable;
1471 qspi_clk: qspi-clk {
1478 qspi_cs0: qspi-cs0 {
1485 qspi_cs1: qspi-cs1 {
1492 qspi_data01: qspi-data01 {
1493 pinmux-data {
1499 qspi_data12: qspi-data12 {
1500 pinmux-data {
1506 qup_i2c0_default: qup-i2c0-default {
1513 qup_i2c1_default: qup-i2c1-default {
1520 qup_i2c2_default: qup-i2c2-default {
1527 qup_i2c3_default: qup-i2c3-default {
1534 qup_i2c4_default: qup-i2c4-default {
1541 qup_i2c5_default: qup-i2c5-default {
1548 qup_i2c6_default: qup-i2c6-default {
1555 qup_i2c7_default: qup-i2c7-default {
1562 qup_i2c8_default: qup-i2c8-default {
1569 qup_i2c9_default: qup-i2c9-default {
1576 qup_i2c10_default: qup-i2c10-default {
1583 qup_i2c11_default: qup-i2c11-default {
1590 qup_spi0_default: qup-spi0-default {
1598 qup_spi1_default: qup-spi1-default {
1606 qup_spi3_default: qup-spi3-default {
1614 qup_spi5_default: qup-spi5-default {
1622 qup_spi6_default: qup-spi6-default {
1630 qup_spi8_default: qup-spi8-default {
1638 qup_spi10_default: qup-spi10-default {
1646 qup_spi11_default: qup-spi11-default {
1654 qup_uart0_default: qup-uart0-default {
1662 qup_uart1_default: qup-uart1-default {
1670 qup_uart2_default: qup-uart2-default {
1677 qup_uart3_default: qup-uart3-default {
1685 qup_uart4_default: qup-uart4-default {
1692 qup_uart5_default: qup-uart5-default {
1700 qup_uart6_default: qup-uart6-default {
1708 qup_uart7_default: qup-uart7-default {
1715 qup_uart8_default: qup-uart8-default {
1722 qup_uart9_default: qup-uart9-default {
1729 qup_uart10_default: qup-uart10-default {
1737 qup_uart11_default: qup-uart11-default {
1745 sdc1_on: sdc1-on {
1746 pinconf-clk {
1748 bias-disable;
1749 drive-strength = <16>;
1752 pinconf-cmd {
1754 bias-pull-up;
1755 drive-strength = <10>;
1758 pinconf-data {
1760 bias-pull-up;
1761 drive-strength = <10>;
1764 pinconf-rclk {
1766 bias-pull-down;
1770 sdc1_off: sdc1-off {
1771 pinconf-clk {
1773 bias-disable;
1774 drive-strength = <2>;
1777 pinconf-cmd {
1779 bias-pull-up;
1780 drive-strength = <2>;
1783 pinconf-data {
1785 bias-pull-up;
1786 drive-strength = <2>;
1789 pinconf-rclk {
1791 bias-pull-down;
1795 sdc2_on: sdc2-on {
1796 pinconf-clk {
1798 bias-disable;
1799 drive-strength = <16>;
1802 pinconf-cmd {
1804 bias-pull-up;
1805 drive-strength = <10>;
1808 pinconf-data {
1810 bias-pull-up;
1811 drive-strength = <10>;
1814 pinconf-sd-cd {
1816 bias-pull-up;
1817 drive-strength = <2>;
1821 sdc2_off: sdc2-off {
1822 pinconf-clk {
1824 bias-disable;
1825 drive-strength = <2>;
1828 pinconf-cmd {
1830 bias-pull-up;
1831 drive-strength = <2>;
1834 pinconf-data {
1836 bias-pull-up;
1837 drive-strength = <2>;
1840 pinconf-sd-cd {
1842 bias-disable;
1843 drive-strength = <2>;
1849 compatible = "qcom,sc7180-mpss-pas";
1851 reg-names = "qdsp6", "rmb";
1853 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
1859 interrupt-names = "wdog", "fatal", "ready", "handover",
1860 "stop-ack", "shutdown-ack";
1868 clock-names = "iface", "bus", "nav", "snoc_axi",
1871 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
1875 power-domain-names = "load_state", "cx", "mx", "mss";
1877 memory-region = <&mpss_mem>;
1879 qcom,smem-states = <&modem_smp2p_out 0>;
1880 qcom,smem-state-names = "stop";
1884 reset-names = "mss_restart", "pdc_reset";
1886 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
1887 qcom,spare-regs = <&tcsr_regs 0xb3e4>;
1891 glink-edge {
1894 qcom,remote-pid = <1>;
1900 compatible = "qcom,adreno-618.0", "qcom,adreno";
1901 #stream-id-cells = <16>;
1904 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
1907 operating-points-v2 = <&gpu_opp_table>;
1911 interconnect-names = "gfx-mem";
1913 gpu_opp_table: opp-table {
1914 compatible = "operating-points-v2";
1916 opp-800000000 {
1917 opp-hz = /bits/ 64 <800000000>;
1918 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1919 opp-peak-kBps = <8532000>;
1922 opp-650000000 {
1923 opp-hz = /bits/ 64 <650000000>;
1924 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1925 opp-peak-kBps = <7216000>;
1928 opp-565000000 {
1929 opp-hz = /bits/ 64 <565000000>;
1930 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1931 opp-peak-kBps = <5412000>;
1934 opp-430000000 {
1935 opp-hz = /bits/ 64 <430000000>;
1936 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1937 opp-peak-kBps = <5412000>;
1940 opp-355000000 {
1941 opp-hz = /bits/ 64 <355000000>;
1942 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1943 opp-peak-kBps = <3072000>;
1946 opp-267000000 {
1947 opp-hz = /bits/ 64 <267000000>;
1948 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1949 opp-peak-kBps = <3072000>;
1952 opp-180000000 {
1953 opp-hz = /bits/ 64 <180000000>;
1954 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1955 opp-peak-kBps = <1804000>;
1961 compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2";
1963 #iommu-cells = <1>;
1964 #global-interrupts = <2>;
1978 clock-names = "bus", "iface";
1980 power-domains = <&gpucc CX_GDSC>;
1984 compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
1987 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
1990 interrupt-names = "hfi", "gmu";
1995 clock-names = "gmu", "cxo", "axi", "memnoc";
1996 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
1997 power-domain-names = "cx", "gx";
1999 operating-points-v2 = <&gmu_opp_table>;
2001 gmu_opp_table: opp-table {
2002 compatible = "operating-points-v2";
2004 opp-200000000 {
2005 opp-hz = /bits/ 64 <200000000>;
2006 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2011 gpucc: clock-controller@5090000 {
2012 compatible = "qcom,sc7180-gpucc";
2017 clock-names = "bi_tcxo",
2020 #clock-cells = <1>;
2021 #reset-cells = <1>;
2022 #power-domain-cells = <1>;
2026 compatible = "arm,coresight-stm", "arm,primecell";
2029 reg-names = "stm-base", "stm-stimulus-base";
2032 clock-names = "apb_pclk";
2034 out-ports {
2037 remote-endpoint = <&funnel0_in7>;
2044 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2048 clock-names = "apb_pclk";
2050 out-ports {
2053 remote-endpoint = <&merge_funnel_in0>;
2058 in-ports {
2059 #address-cells = <1>;
2060 #size-cells = <0>;
2065 remote-endpoint = <&stm_out>;
2072 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2076 clock-names = "apb_pclk";
2078 out-ports {
2081 remote-endpoint = <&merge_funnel_in1>;
2086 in-ports {
2087 #address-cells = <1>;
2088 #size-cells = <0>;
2093 remote-endpoint = <&apss_merge_funnel_out>;
2100 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2104 clock-names = "apb_pclk";
2106 out-ports {
2109 remote-endpoint = <&swao_funnel_in>;
2114 in-ports {
2115 #address-cells = <1>;
2116 #size-cells = <0>;
2121 remote-endpoint = <&funnel0_out>;
2128 remote-endpoint = <&funnel1_out>;
2135 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2139 clock-names = "apb_pclk";
2141 out-ports {
2144 remote-endpoint = <&etr_in>;
2149 in-ports {
2152 remote-endpoint = <&swao_replicator_out>;
2159 compatible = "arm,coresight-tmc", "arm,primecell";
2164 clock-names = "apb_pclk";
2165 arm,scatter-gather;
2167 in-ports {
2170 remote-endpoint = <&replicator_out>;
2177 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2181 clock-names = "apb_pclk";
2183 out-ports {
2186 remote-endpoint = <&etf_in>;
2191 in-ports {
2192 #address-cells = <1>;
2193 #size-cells = <0>;
2198 remote-endpoint = <&merge_funnel_out>;
2205 compatible = "arm,coresight-tmc", "arm,primecell";
2209 clock-names = "apb_pclk";
2211 out-ports {
2214 remote-endpoint = <&swao_replicator_in>;
2219 in-ports {
2222 remote-endpoint = <&swao_funnel_out>;
2229 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2233 clock-names = "apb_pclk";
2234 qcom,replicator-loses-context;
2236 out-ports {
2239 remote-endpoint = <&replicator_in>;
2244 in-ports {
2247 remote-endpoint = <&etf_out>;
2254 compatible = "arm,coresight-etm4x", "arm,primecell";
2260 clock-names = "apb_pclk";
2261 arm,coresight-loses-context-with-cpu;
2262 qcom,skip-power-up;
2264 out-ports {
2267 remote-endpoint = <&apss_funnel_in0>;
2274 compatible = "arm,coresight-etm4x", "arm,primecell";
2280 clock-names = "apb_pclk";
2281 arm,coresight-loses-context-with-cpu;
2282 qcom,skip-power-up;
2284 out-ports {
2287 remote-endpoint = <&apss_funnel_in1>;
2294 compatible = "arm,coresight-etm4x", "arm,primecell";
2300 clock-names = "apb_pclk";
2301 arm,coresight-loses-context-with-cpu;
2302 qcom,skip-power-up;
2304 out-ports {
2307 remote-endpoint = <&apss_funnel_in2>;
2314 compatible = "arm,coresight-etm4x", "arm,primecell";
2320 clock-names = "apb_pclk";
2321 arm,coresight-loses-context-with-cpu;
2322 qcom,skip-power-up;
2324 out-ports {
2327 remote-endpoint = <&apss_funnel_in3>;
2334 compatible = "arm,coresight-etm4x", "arm,primecell";
2340 clock-names = "apb_pclk";
2341 arm,coresight-loses-context-with-cpu;
2342 qcom,skip-power-up;
2344 out-ports {
2347 remote-endpoint = <&apss_funnel_in4>;
2354 compatible = "arm,coresight-etm4x", "arm,primecell";
2360 clock-names = "apb_pclk";
2361 arm,coresight-loses-context-with-cpu;
2362 qcom,skip-power-up;
2364 out-ports {
2367 remote-endpoint = <&apss_funnel_in5>;
2374 compatible = "arm,coresight-etm4x", "arm,primecell";
2380 clock-names = "apb_pclk";
2381 arm,coresight-loses-context-with-cpu;
2382 qcom,skip-power-up;
2384 out-ports {
2387 remote-endpoint = <&apss_funnel_in6>;
2394 compatible = "arm,coresight-etm4x", "arm,primecell";
2400 clock-names = "apb_pclk";
2401 arm,coresight-loses-context-with-cpu;
2402 qcom,skip-power-up;
2404 out-ports {
2407 remote-endpoint = <&apss_funnel_in7>;
2414 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2418 clock-names = "apb_pclk";
2420 out-ports {
2423 remote-endpoint = <&apss_merge_funnel_in>;
2428 in-ports {
2429 #address-cells = <1>;
2430 #size-cells = <0>;
2435 remote-endpoint = <&etm0_out>;
2442 remote-endpoint = <&etm1_out>;
2449 remote-endpoint = <&etm2_out>;
2456 remote-endpoint = <&etm3_out>;
2463 remote-endpoint = <&etm4_out>;
2470 remote-endpoint = <&etm5_out>;
2477 remote-endpoint = <&etm6_out>;
2484 remote-endpoint = <&etm7_out>;
2491 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2495 clock-names = "apb_pclk";
2497 out-ports {
2500 remote-endpoint = <&funnel1_in4>;
2505 in-ports {
2508 remote-endpoint = <&apss_funnel_out>;
2515 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2521 interrupt-names = "hc_irq", "pwr_irq";
2525 clock-names = "core", "iface";
2529 interconnect-names = "sdhc-ddr","cpu-sdhc";
2530 power-domains = <&rpmhpd SC7180_CX>;
2531 operating-points-v2 = <&sdhc2_opp_table>;
2533 bus-width = <4>;
2537 sdhc2_opp_table: sdhc2-opp-table {
2538 compatible = "operating-points-v2";
2540 opp-100000000 {
2541 opp-hz = /bits/ 64 <100000000>;
2542 required-opps = <&rpmhpd_opp_low_svs>;
2543 opp-peak-kBps = <160000 100000>;
2544 opp-avg-kBps = <80000 50000>;
2547 opp-202000000 {
2548 opp-hz = /bits/ 64 <202000000>;
2549 required-opps = <&rpmhpd_opp_svs_l1>;
2550 opp-peak-kBps = <200000 120000>;
2551 opp-avg-kBps = <100000 60000>;
2556 qspi_opp_table: qspi-opp-table {
2557 compatible = "operating-points-v2";
2559 opp-75000000 {
2560 opp-hz = /bits/ 64 <75000000>;
2561 required-opps = <&rpmhpd_opp_low_svs>;
2564 opp-150000000 {
2565 opp-hz = /bits/ 64 <150000000>;
2566 required-opps = <&rpmhpd_opp_svs>;
2569 opp-300000000 {
2570 opp-hz = /bits/ 64 <300000000>;
2571 required-opps = <&rpmhpd_opp_nom>;
2576 compatible = "qcom,qspi-v1";
2578 #address-cells = <1>;
2579 #size-cells = <0>;
2583 clock-names = "iface", "core";
2586 interconnect-names = "qspi-config";
2587 power-domains = <&rpmhpd SC7180_CX>;
2588 operating-points-v2 = <&qspi_opp_table>;
2593 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2596 #phy-cells = <0>;
2599 clock-names = "cfg_ahb", "ref";
2602 nvmem-cells = <&qusb2p_hstx_trim>;
2605 usb_1_qmpphy: phy-wrapper@88e9000 {
2606 compatible = "qcom,sc7180-qmp-usb3-phy";
2609 reg-names = "reg-base", "dp_com";
2611 #clock-cells = <1>;
2612 #address-cells = <2>;
2613 #size-cells = <2>;
2620 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2624 reset-names = "phy", "common";
2633 #clock-cells = <0>;
2634 #phy-cells = <0>;
2636 clock-names = "pipe0";
2637 clock-output-names = "usb3_phy_pipe_clk_src";
2642 compatible = "qcom,sc7180-dc-noc";
2644 #interconnect-cells = <2>;
2645 qcom,bcm-voters = <&apps_bcm_voter>;
2648 system-cache-controller@9200000 {
2649 compatible = "qcom,sc7180-llcc";
2651 reg-names = "llcc_base", "llcc_broadcast_base";
2656 compatible = "qcom,sc7180-gem-noc";
2658 #interconnect-cells = <2>;
2659 qcom,bcm-voters = <&apps_bcm_voter>;
2663 compatible = "qcom,sc7180-npu-noc";
2665 #interconnect-cells = <2>;
2666 qcom,bcm-voters = <&apps_bcm_voter>;
2670 compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
2673 #address-cells = <2>;
2674 #size-cells = <2>;
2676 dma-ranges;
2683 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2686 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2688 assigned-clock-rates = <19200000>, <150000000>;
2694 interrupt-names = "hs_phy_irq", "ss_phy_irq",
2697 power-domains = <&gcc USB30_PRIM_GDSC>;
2703 interconnect-names = "usb-ddr", "apps-usb";
2713 phy-names = "usb2-phy", "usb3-phy";
2714 maximum-speed = "super-speed";
2718 venus: video-codec@aa00000 {
2719 compatible = "qcom,sc7180-venus";
2722 power-domains = <&videocc VENUS_GDSC>,
2725 power-domain-names = "venus", "vcodec0", "cx";
2726 operating-points-v2 = <&venus_opp_table>;
2732 clock-names = "core", "iface", "bus",
2735 memory-region = <&venus_mem>;
2738 interconnect-names = "video-mem", "cpu-cfg";
2740 video-decoder {
2741 compatible = "venus-decoder";
2744 video-encoder {
2745 compatible = "venus-encoder";
2748 venus_opp_table: venus-opp-table {
2749 compatible = "operating-points-v2";
2751 opp-150000000 {
2752 opp-hz = /bits/ 64 <150000000>;
2753 required-opps = <&rpmhpd_opp_low_svs>;
2756 opp-270000000 {
2757 opp-hz = /bits/ 64 <270000000>;
2758 required-opps = <&rpmhpd_opp_svs>;
2761 opp-340000000 {
2762 opp-hz = /bits/ 64 <340000000>;
2763 required-opps = <&rpmhpd_opp_svs_l1>;
2766 opp-434000000 {
2767 opp-hz = /bits/ 64 <434000000>;
2768 required-opps = <&rpmhpd_opp_nom>;
2771 opp-500000097 {
2772 opp-hz = /bits/ 64 <500000097>;
2773 required-opps = <&rpmhpd_opp_turbo>;
2778 videocc: clock-controller@ab00000 {
2779 compatible = "qcom,sc7180-videocc";
2782 clock-names = "bi_tcxo";
2783 #clock-cells = <1>;
2784 #reset-cells = <1>;
2785 #power-domain-cells = <1>;
2789 compatible = "qcom,sc7180-camnoc-virt";
2791 #interconnect-cells = <2>;
2792 qcom,bcm-voters = <&apps_bcm_voter>;
2796 compatible = "qcom,sc7180-mdss";
2798 reg-names = "mdss";
2800 power-domains = <&dispcc MDSS_GDSC>;
2805 clock-names = "iface", "ahb", "core";
2807 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
2808 assigned-clock-rates = <300000000>;
2811 interrupt-controller;
2812 #interrupt-cells = <1>;
2815 interconnect-names = "mdp0-mem";
2819 #address-cells = <2>;
2820 #size-cells = <2>;
2826 compatible = "qcom,sc7180-dpu";
2829 reg-names = "mdp", "vbif";
2837 clock-names = "bus", "iface", "rot", "lut", "core",
2839 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
2843 assigned-clock-rates = <300000000>,
2847 operating-points-v2 = <&mdp_opp_table>;
2848 power-domains = <&rpmhpd SC7180_CX>;
2850 interrupt-parent = <&mdss>;
2856 #address-cells = <1>;
2857 #size-cells = <0>;
2862 remote-endpoint = <&dsi0_in>;
2867 mdp_opp_table: mdp-opp-table {
2868 compatible = "operating-points-v2";
2870 opp-200000000 {
2871 opp-hz = /bits/ 64 <200000000>;
2872 required-opps = <&rpmhpd_opp_low_svs>;
2875 opp-300000000 {
2876 opp-hz = /bits/ 64 <300000000>;
2877 required-opps = <&rpmhpd_opp_svs>;
2880 opp-345000000 {
2881 opp-hz = /bits/ 64 <345000000>;
2882 required-opps = <&rpmhpd_opp_svs_l1>;
2885 opp-460000000 {
2886 opp-hz = /bits/ 64 <460000000>;
2887 required-opps = <&rpmhpd_opp_nom>;
2894 compatible = "qcom,mdss-dsi-ctrl";
2896 reg-names = "dsi_ctrl";
2898 interrupt-parent = <&mdss>;
2907 clock-names = "byte",
2914 operating-points-v2 = <&dsi_opp_table>;
2915 power-domains = <&rpmhpd SC7180_CX>;
2918 phy-names = "dsi";
2920 #address-cells = <1>;
2921 #size-cells = <0>;
2926 #address-cells = <1>;
2927 #size-cells = <0>;
2932 remote-endpoint = <&dpu_intf1_out>;
2943 dsi_opp_table: dsi-opp-table {
2944 compatible = "operating-points-v2";
2946 opp-187500000 {
2947 opp-hz = /bits/ 64 <187500000>;
2948 required-opps = <&rpmhpd_opp_low_svs>;
2951 opp-300000000 {
2952 opp-hz = /bits/ 64 <300000000>;
2953 required-opps = <&rpmhpd_opp_svs>;
2956 opp-358000000 {
2957 opp-hz = /bits/ 64 <358000000>;
2958 required-opps = <&rpmhpd_opp_svs_l1>;
2963 dsi_phy: dsi-phy@ae94400 {
2964 compatible = "qcom,dsi-phy-10nm";
2968 reg-names = "dsi_phy",
2972 #clock-cells = <1>;
2973 #phy-cells = <0>;
2977 clock-names = "iface", "ref";
2983 dispcc: clock-controller@af00000 {
2984 compatible = "qcom,sc7180-dispcc";
2992 clock-names = "bi_tcxo",
2998 #clock-cells = <1>;
2999 #reset-cells = <1>;
3000 #power-domain-cells = <1>;
3003 pdc: interrupt-controller@b220000 {
3004 compatible = "qcom,sc7180-pdc", "qcom,pdc";
3006 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3007 #interrupt-cells = <2>;
3008 interrupt-parent = <&intc>;
3009 interrupt-controller;
3012 pdc_reset: reset-controller@b2e0000 {
3013 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3015 #reset-cells = <1>;
3018 tsens0: thermal-sensor@c263000 {
3019 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3025 interrupt-names = "uplow","critical";
3026 #thermal-sensor-cells = <1>;
3029 tsens1: thermal-sensor@c265000 {
3030 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3036 interrupt-names = "uplow","critical";
3037 #thermal-sensor-cells = <1>;
3040 aoss_reset: reset-controller@c2a0000 {
3041 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3043 #reset-cells = <1>;
3047 compatible = "qcom,sc7180-aoss-qmp";
3052 #clock-cells = <0>;
3053 #power-domain-cells = <1>;
3057 compatible = "qcom,spmi-pmic-arb";
3063 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3064 interrupt-names = "periph_irq";
3065 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3068 #address-cells = <1>;
3069 #size-cells = <1>;
3070 interrupt-controller;
3071 #interrupt-cells = <4>;
3072 cell-index = <0>;
3076 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3078 #iommu-cells = <2>;
3079 #global-interrupts = <1>;
3163 intc: interrupt-controller@17a00000 {
3164 compatible = "arm,gic-v3";
3165 #address-cells = <2>;
3166 #size-cells = <2>;
3168 #interrupt-cells = <3>;
3169 interrupt-controller;
3174 msi-controller@17a40000 {
3175 compatible = "arm,gic-v3-its";
3176 msi-controller;
3177 #msi-cells = <1>;
3184 compatible = "qcom,sc7180-apss-shared";
3186 #mbox-cells = <1>;
3190 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3196 #address-cells = <2>;
3197 #size-cells = <2>;
3199 compatible = "arm,armv7-timer-mem";
3203 frame-number = <0>;
3211 frame-number = <1>;
3218 frame-number = <2>;
3225 frame-number = <3>;
3232 frame-number = <4>;
3239 frame-number = <5>;
3246 frame-number = <6>;
3254 compatible = "qcom,rpmh-rsc";
3258 reg-names = "drv-0", "drv-1", "drv-2";
3262 qcom,tcs-offset = <0xd00>;
3263 qcom,drv-id = <2>;
3264 qcom,tcs-config = <ACTIVE_TCS 2>,
3269 rpmhcc: clock-controller {
3270 compatible = "qcom,sc7180-rpmh-clk";
3272 clock-names = "xo";
3273 #clock-cells = <1>;
3276 rpmhpd: power-controller {
3277 compatible = "qcom,sc7180-rpmhpd";
3278 #power-domain-cells = <1>;
3279 operating-points-v2 = <&rpmhpd_opp_table>;
3281 rpmhpd_opp_table: opp-table {
3282 compatible = "operating-points-v2";
3285 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3289 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3293 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3297 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3301 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3305 opp-level = <224>;
3309 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3313 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3317 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3321 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3325 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3331 compatible = "qcom,bcm-voter";
3336 compatible = "qcom,sc7180-osm-l3";
3340 clock-names = "xo", "alternate";
3342 #interconnect-cells = <1>;
3346 compatible = "qcom,cpufreq-hw";
3348 reg-names = "freq-domain0", "freq-domain1";
3351 clock-names = "xo", "alternate";
3353 #freq-domain-cells = <1>;
3357 compatible = "qcom,wcn3990-wifi";
3359 reg-names = "membase";
3374 memory-region = <&wlan_mem>;
3375 qcom,msa-fixed-perm;
3379 lpasscc: clock-controller@62d00000 {
3380 compatible = "qcom,sc7180-lpasscorecc";
3383 reg-names = "lpass_core_cc", "lpass_audio_cc";
3386 clock-names = "iface", "bi_tcxo";
3387 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3388 #clock-cells = <1>;
3389 #power-domain-cells = <1>;
3392 lpass_hm: clock-controller@63000000 {
3393 compatible = "qcom,sc7180-lpasshm";
3397 clock-names = "iface", "bi_tcxo";
3398 #clock-cells = <1>;
3399 #power-domain-cells = <1>;
3403 thermal-zones {
3404 cpu0-thermal {
3405 polling-delay-passive = <0>;
3406 polling-delay = <0>;
3408 thermal-sensors = <&tsens0 1>;
3409 sustainable-power = <768>;
3412 cpu0_alert0: trip-point0 {
3418 cpu0_alert1: trip-point1 {
3431 cooling-maps {
3434 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3443 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3453 cpu1-thermal {
3454 polling-delay-passive = <0>;
3455 polling-delay = <0>;
3457 thermal-sensors = <&tsens0 2>;
3458 sustainable-power = <768>;
3461 cpu1_alert0: trip-point0 {
3467 cpu1_alert1: trip-point1 {
3480 cooling-maps {
3483 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3492 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3502 cpu2-thermal {
3503 polling-delay-passive = <0>;
3504 polling-delay = <0>;
3506 thermal-sensors = <&tsens0 3>;
3507 sustainable-power = <768>;
3510 cpu2_alert0: trip-point0 {
3516 cpu2_alert1: trip-point1 {
3529 cooling-maps {
3532 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3541 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3551 cpu3-thermal {
3552 polling-delay-passive = <0>;
3553 polling-delay = <0>;
3555 thermal-sensors = <&tsens0 4>;
3556 sustainable-power = <768>;
3559 cpu3_alert0: trip-point0 {
3565 cpu3_alert1: trip-point1 {
3578 cooling-maps {
3581 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3590 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3600 cpu4-thermal {
3601 polling-delay-passive = <0>;
3602 polling-delay = <0>;
3604 thermal-sensors = <&tsens0 5>;
3605 sustainable-power = <768>;
3608 cpu4_alert0: trip-point0 {
3614 cpu4_alert1: trip-point1 {
3627 cooling-maps {
3630 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3639 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3649 cpu5-thermal {
3650 polling-delay-passive = <0>;
3651 polling-delay = <0>;
3653 thermal-sensors = <&tsens0 6>;
3654 sustainable-power = <768>;
3657 cpu5_alert0: trip-point0 {
3663 cpu5_alert1: trip-point1 {
3676 cooling-maps {
3679 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3688 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3698 cpu6-thermal {
3699 polling-delay-passive = <0>;
3700 polling-delay = <0>;
3702 thermal-sensors = <&tsens0 9>;
3703 sustainable-power = <1202>;
3706 cpu6_alert0: trip-point0 {
3712 cpu6_alert1: trip-point1 {
3725 cooling-maps {
3728 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3733 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3739 cpu7-thermal {
3740 polling-delay-passive = <0>;
3741 polling-delay = <0>;
3743 thermal-sensors = <&tsens0 10>;
3744 sustainable-power = <1202>;
3747 cpu7_alert0: trip-point0 {
3753 cpu7_alert1: trip-point1 {
3766 cooling-maps {
3769 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3774 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3780 cpu8-thermal {
3781 polling-delay-passive = <0>;
3782 polling-delay = <0>;
3784 thermal-sensors = <&tsens0 11>;
3785 sustainable-power = <1202>;
3788 cpu8_alert0: trip-point0 {
3794 cpu8_alert1: trip-point1 {
3807 cooling-maps {
3810 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3815 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3821 cpu9-thermal {
3822 polling-delay-passive = <0>;
3823 polling-delay = <0>;
3825 thermal-sensors = <&tsens0 12>;
3826 sustainable-power = <1202>;
3829 cpu9_alert0: trip-point0 {
3835 cpu9_alert1: trip-point1 {
3848 cooling-maps {
3851 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3856 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3862 aoss0-thermal {
3863 polling-delay-passive = <0>;
3864 polling-delay = <0>;
3866 thermal-sensors = <&tsens0 0>;
3869 aoss0_alert0: trip-point0 {
3883 cpuss0-thermal {
3884 polling-delay-passive = <0>;
3885 polling-delay = <0>;
3887 thermal-sensors = <&tsens0 7>;
3890 cpuss0_alert0: trip-point0 {
3903 cpuss1-thermal {
3904 polling-delay-passive = <0>;
3905 polling-delay = <0>;
3907 thermal-sensors = <&tsens0 8>;
3910 cpuss1_alert0: trip-point0 {
3923 gpuss0-thermal {
3924 polling-delay-passive = <0>;
3925 polling-delay = <0>;
3927 thermal-sensors = <&tsens0 13>;
3930 gpuss0_alert0: trip-point0 {
3944 gpuss1-thermal {
3945 polling-delay-passive = <0>;
3946 polling-delay = <0>;
3948 thermal-sensors = <&tsens0 14>;
3951 gpuss1_alert0: trip-point0 {
3965 aoss1-thermal {
3966 polling-delay-passive = <0>;
3967 polling-delay = <0>;
3969 thermal-sensors = <&tsens1 0>;
3972 aoss1_alert0: trip-point0 {
3986 cwlan-thermal {
3987 polling-delay-passive = <0>;
3988 polling-delay = <0>;
3990 thermal-sensors = <&tsens1 1>;
3993 cwlan_alert0: trip-point0 {
4007 audio-thermal {
4008 polling-delay-passive = <0>;
4009 polling-delay = <0>;
4011 thermal-sensors = <&tsens1 2>;
4014 audio_alert0: trip-point0 {
4028 ddr-thermal {
4029 polling-delay-passive = <0>;
4030 polling-delay = <0>;
4032 thermal-sensors = <&tsens1 3>;
4035 ddr_alert0: trip-point0 {
4049 q6-hvx-thermal {
4050 polling-delay-passive = <0>;
4051 polling-delay = <0>;
4053 thermal-sensors = <&tsens1 4>;
4056 q6_hvx_alert0: trip-point0 {
4070 camera-thermal {
4071 polling-delay-passive = <0>;
4072 polling-delay = <0>;
4074 thermal-sensors = <&tsens1 5>;
4077 camera_alert0: trip-point0 {
4091 mdm-core-thermal {
4092 polling-delay-passive = <0>;
4093 polling-delay = <0>;
4095 thermal-sensors = <&tsens1 6>;
4098 mdm_alert0: trip-point0 {
4112 mdm-dsp-thermal {
4113 polling-delay-passive = <0>;
4114 polling-delay = <0>;
4116 thermal-sensors = <&tsens1 7>;
4119 mdm_dsp_alert0: trip-point0 {
4133 npu-thermal {
4134 polling-delay-passive = <0>;
4135 polling-delay = <0>;
4137 thermal-sensors = <&tsens1 8>;
4140 npu_alert0: trip-point0 {
4154 video-thermal {
4155 polling-delay-passive = <0>;
4156 polling-delay = <0>;
4158 thermal-sensors = <&tsens1 9>;
4161 video_alert0: trip-point0 {
4177 compatible = "arm,armv8-timer";