Lines Matching refs:gcc
5 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
313 clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;
331 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
332 <&gcc GCC_USB3_PHY_PIPE_CLK>;
334 resets = <&gcc GCC_USB3_PHY_BCR>,
335 <&gcc GCC_USB3PHY_PHY_BCR>;
345 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
346 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
348 resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,
349 <&gcc GCC_USB2A_PHY_BCR>;
359 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
360 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
362 resets = <&gcc GCC_QUSB2_PHY_BCR>,
363 <&gcc GCC_USB2_HS_PHY_ONLY_BCR>;
437 clocks = <&gcc GCC_PRNG_AHB_CLK>;
493 <&gcc GCC_CDSP_CFG_AHB_CLK>,
494 <&gcc GCC_CDSP_TBU_CLK>,
495 <&gcc GCC_BIMC_CDSP_CLK>,
509 resets = <&gcc GCC_CDSP_RESTART>;
537 clocks = <&gcc GCC_USB30_MASTER_CLK>,
538 <&gcc GCC_SYS_NOC_USB3_CLK>,
539 <&gcc GCC_USB30_SLEEP_CLK>,
540 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
542 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
543 <&gcc GCC_USB30_MASTER_CLK>;
566 clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>,
567 <&gcc GCC_PCNOC_USB2_CLK>,
568 <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>,
569 <&gcc GCC_USB20_MOCK_UTMI_CLK>;
571 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
572 <&gcc GCC_USB_HS_SYSTEM_CLK>;
702 gcc: clock-controller@1800000 { label
703 compatible = "qcom,gcc-qcs404";
708 assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
776 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
777 resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
778 <&gcc 21>;
796 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
797 <&gcc GCC_SDCC1_AHB_CLK>,
808 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
819 clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
832 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
845 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
860 clocks = <&gcc GCC_ETH_AXI_CLK>,
861 <&gcc GCC_ETH_SLAVE_AHB_CLK>,
862 <&gcc GCC_ETH_PTP_CLK>,
863 <&gcc GCC_ETH_RGMII_CLK>;
899 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
912 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
913 <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>;
926 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
927 <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>;
940 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
941 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
954 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
955 <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>;
968 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
969 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
982 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
983 <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>;
996 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
997 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
1010 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1011 <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>;
1024 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1025 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
1038 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1039 <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>;
1052 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1063 clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
1076 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
1077 <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>;
1090 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
1091 <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>;
1127 clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>;
1302 clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1303 <&gcc GCC_PCIE_0_AUX_CLK>,
1304 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1305 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1308 resets = <&gcc 18>,
1309 <&gcc 17>,
1310 <&gcc 15>,
1311 <&gcc 19>,
1312 <&gcc GCC_PCIE_0_BCR>,
1313 <&gcc 16>;