Lines Matching +full:kpss +full:- +full:acc +full:- +full:v2
1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
6 #include <dt-bindings/clock/qcom,turingcc-qcs404.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/power/qcom-rpmpd.h>
9 #include <dt-bindings/thermal/thermal.h>
12 interrupt-parent = <&intc>;
14 #address-cells = <2>;
15 #size-cells = <2>;
20 xo_board: xo-board {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <19200000>;
26 sleep_clk: sleep-clk {
27 compatible = "fixed-clock";
28 #clock-cells = <0>;
29 clock-frequency = <32768>;
34 #address-cells = <1>;
35 #size-cells = <0>;
39 compatible = "arm,cortex-a53";
41 enable-method = "psci";
42 cpu-idle-states = <&CPU_SLEEP_0>;
43 next-level-cache = <&L2_0>;
44 #cooling-cells = <2>;
46 operating-points-v2 = <&cpu_opp_table>;
47 power-domains = <&cpr>;
48 power-domain-names = "cpr";
53 compatible = "arm,cortex-a53";
55 enable-method = "psci";
56 cpu-idle-states = <&CPU_SLEEP_0>;
57 next-level-cache = <&L2_0>;
58 #cooling-cells = <2>;
60 operating-points-v2 = <&cpu_opp_table>;
61 power-domains = <&cpr>;
62 power-domain-names = "cpr";
67 compatible = "arm,cortex-a53";
69 enable-method = "psci";
70 cpu-idle-states = <&CPU_SLEEP_0>;
71 next-level-cache = <&L2_0>;
72 #cooling-cells = <2>;
74 operating-points-v2 = <&cpu_opp_table>;
75 power-domains = <&cpr>;
76 power-domain-names = "cpr";
81 compatible = "arm,cortex-a53";
83 enable-method = "psci";
84 cpu-idle-states = <&CPU_SLEEP_0>;
85 next-level-cache = <&L2_0>;
86 #cooling-cells = <2>;
88 operating-points-v2 = <&cpu_opp_table>;
89 power-domains = <&cpr>;
90 power-domain-names = "cpr";
93 L2_0: l2-cache {
95 cache-level = <2>;
98 idle-states {
99 entry-method = "psci";
101 CPU_SLEEP_0: cpu-sleep-0 {
102 compatible = "arm,idle-state";
103 idle-state-name = "standalone-power-collapse";
104 arm,psci-suspend-param = <0x40000003>;
105 entry-latency-us = <125>;
106 exit-latency-us = <180>;
107 min-residency-us = <595>;
108 local-timer-stop;
113 cpu_opp_table: cpu-opp-table {
114 compatible = "operating-points-v2-kryo-cpu";
115 opp-shared;
117 opp-1094400000 {
118 opp-hz = /bits/ 64 <1094400000>;
119 required-opps = <&cpr_opp1>;
121 opp-1248000000 {
122 opp-hz = /bits/ 64 <1248000000>;
123 required-opps = <&cpr_opp2>;
125 opp-1401600000 {
126 opp-hz = /bits/ 64 <1401600000>;
127 required-opps = <&cpr_opp3>;
131 cpr_opp_table: cpr-opp-table {
132 compatible = "operating-points-v2-qcom-level";
135 opp-level = <1>;
136 qcom,opp-fuse-level = <1>;
139 opp-level = <2>;
140 qcom,opp-fuse-level = <2>;
143 opp-level = <3>;
144 qcom,opp-fuse-level = <3>;
150 compatible = "qcom,scm-qcs404", "qcom,scm";
151 #reset-cells = <1>;
162 compatible = "arm,psci-1.0";
166 reserved-memory {
167 #address-cells = <2>;
168 #size-cells = <2>;
173 no-map;
178 no-map;
183 no-map;
188 no-map;
193 no-map;
198 no-map;
203 no-map;
208 no-map;
213 no-map;
217 rpm-glink {
218 compatible = "qcom,glink-rpm";
221 qcom,rpm-msg-ram = <&rpm_msg_ram>;
224 rpm_requests: glink-channel {
225 compatible = "qcom,rpm-qcs404";
226 qcom,glink-channels = "rpm_requests";
228 rpmcc: clock-controller {
229 compatible = "qcom,rpmcc-qcs404";
230 #clock-cells = <1>;
233 rpmpd: power-controller {
234 compatible = "qcom,qcs404-rpmpd";
235 #power-domain-cells = <1>;
236 operating-points-v2 = <&rpmpd_opp_table>;
238 rpmpd_opp_table: opp-table {
239 compatible = "operating-points-v2";
242 opp-level = <16>;
246 opp-level = <32>;
250 opp-level = <48>;
254 opp-level = <64>;
258 opp-level = <128>;
262 opp-level = <192>;
266 opp-level = <256>;
270 opp-level = <320>;
274 opp-level = <384>;
278 opp-level = <416>;
282 opp-level = <512>;
292 memory-region = <&smem_region>;
293 qcom,rpm-msg-ram = <&rpm_msg_ram>;
299 compatible = "qcom,tcsr-mutex";
301 #hwlock-cells = <1>;
305 #address-cells = <1>;
306 #size-cells = <1>;
308 compatible = "simple-bus";
310 turingcc: clock-controller@800000 {
311 compatible = "qcom,qcs404-turingcc";
315 #clock-cells = <1>;
316 #reset-cells = <1>;
322 compatible = "qcom,rpm-msg-ram";
327 compatible = "qcom,usb-ss-28nm-phy";
329 #phy-cells = <0>;
333 clock-names = "ref", "ahb", "pipe";
336 reset-names = "com", "phy";
341 compatible = "qcom,usb-hs-28nm-femtophy";
343 #phy-cells = <0>;
347 clock-names = "ref", "ahb", "sleep";
350 reset-names = "phy", "por";
355 compatible = "qcom,usb-hs-28nm-femtophy";
357 #phy-cells = <0>;
361 clock-names = "ref", "ahb", "sleep";
364 reset-names = "phy", "por";
371 #address-cells = <1>;
372 #size-cells = <1>;
435 compatible = "qcom,prng-ee";
438 clock-names = "core";
443 compatible = "qcom,qcs404-bimc";
444 #interconnect-cells = <1>;
445 clock-names = "bus", "bus_a";
450 tsens: thermal-sensor@4a9000 {
451 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
454 nvmem-cells = <&tsens_caldata>;
455 nvmem-cell-names = "calib";
458 interrupt-names = "uplow";
459 #thermal-sensor-cells = <1>;
464 compatible = "qcom,qcs404-pcnoc";
465 #interconnect-cells = <1>;
466 clock-names = "bus", "bus_a";
473 compatible = "qcom,qcs404-snoc";
474 #interconnect-cells = <1>;
475 clock-names = "bus", "bus_a";
481 compatible = "qcom,qcs404-cdsp-pas";
484 interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
489 interrupt-names = "wdog", "fatal", "ready",
490 "handover", "stop-ack";
500 clock-names = "xo",
510 reset-names = "restart";
512 qcom,halt-regs = <&tcsr 0x19004>;
514 memory-region = <&cdsp_fw_mem>;
516 qcom,smem-states = <&cdsp_smp2p_out 0>;
517 qcom,smem-state-names = "stop";
521 glink-edge {
524 qcom,remote-pid = <5>;
534 #address-cells = <1>;
535 #size-cells = <1>;
541 clock-names = "core", "iface", "sleep", "mock_utmi";
542 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
544 assigned-clock-rates = <19200000>, <200000000>;
552 phy-names = "usb2-phy", "usb3-phy";
553 snps,has-lpm-erratum;
554 snps,hird-threshold = /bits/ 8 <0x10>;
563 #address-cells = <1>;
564 #size-cells = <1>;
570 clock-names = "core", "iface", "sleep", "mock_utmi";
571 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
573 assigned-clock-rates = <19200000>, <133333333>;
581 phy-names = "usb2-phy";
582 snps,has-lpm-erratum;
583 snps,hird-threshold = /bits/ 8 <0x10>;
590 compatible = "qcom,qcs404-pinctrl";
594 reg-names = "south", "north", "east";
596 gpio-ranges = <&tlmm 0 0 120>;
597 gpio-controller;
598 #gpio-cells = <2>;
599 interrupt-controller;
600 #interrupt-cells = <2>;
602 blsp1_i2c0_default: blsp1-i2c0-default {
607 blsp1_i2c1_default: blsp1-i2c1-default {
612 blsp1_i2c2_default: blsp1-i2c2-default {
624 blsp1_i2c3_default: blsp1-i2c3-default {
629 blsp1_i2c4_default: blsp1-i2c4-default {
634 blsp1_uart0_default: blsp1-uart0-default {
639 blsp1_uart1_default: blsp1-uart1-default {
644 blsp1_uart2_default: blsp1-uart2-default {
656 blsp1_uart3_default: blsp1-uart3-default {
661 blsp2_i2c0_default: blsp2-i2c0-default {
666 blsp1_spi0_default: blsp1-spi0-default {
671 blsp1_spi1_default: blsp1-spi1-default {
676 blsp1_spi2_default: blsp1-spi2-default {
681 blsp1_spi3_default: blsp1-spi3-default {
686 blsp1_spi4_default: blsp1-spi4-default {
691 blsp2_spi0_default: blsp2-spi0-default {
696 blsp2_uart0_default: blsp2-uart0-default {
702 gcc: clock-controller@1800000 {
703 compatible = "qcom,gcc-qcs404";
705 #clock-cells = <1>;
706 #reset-cells = <1>;
708 assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
709 assigned-clock-rates = <19200000>;
723 compatible = "qcom,spmi-pmic-arb";
729 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
730 interrupt-names = "periph_irq";
734 #address-cells = <2>;
735 #size-cells = <0>;
736 interrupt-controller;
737 #interrupt-cells = <4>;
741 compatible = "qcom,qcs404-wcss-pas";
744 interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
749 interrupt-names = "wdog", "fatal", "ready",
750 "handover", "stop-ack";
753 clock-names = "xo";
755 memory-region = <&wlan_fw_mem>;
757 qcom,smem-states = <&wcss_smp2p_out 0>;
758 qcom,smem-state-names = "stop";
762 glink-edge {
765 qcom,remote-pid = <1>;
773 compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
779 reset-names = "phy", "pipe";
781 clock-output-names = "pcie_0_pipe_clk";
782 #phy-cells = <0>;
788 compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5";
790 reg-names = "hc", "cqhci";
794 interrupt-names = "hc_irq", "pwr_irq";
799 clock-names = "core", "iface", "xo";
805 compatible = "qcom,bam-v1.7.0";
809 clock-names = "bam_clk";
810 #dma-cells = <1>;
816 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
820 clock-names = "core", "iface";
822 dma-names = "rx", "tx";
823 pinctrl-names = "default";
824 pinctrl-0 = <&blsp1_uart0_default>;
829 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
833 clock-names = "core", "iface";
835 dma-names = "rx", "tx";
836 pinctrl-names = "default";
837 pinctrl-0 = <&blsp1_uart1_default>;
842 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
846 clock-names = "core", "iface";
848 dma-names = "rx", "tx";
849 pinctrl-names = "default";
850 pinctrl-0 = <&blsp1_uart2_default>;
855 compatible = "qcom,qcs404-ethqos";
858 reg-names = "stmmaceth", "rgmii";
859 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
866 interrupt-names = "macirq", "eth_lpi";
869 rx-fifo-depth = <4096>;
870 tx-fifo-depth = <4096>;
876 compatible = "qcom,wcn3990-wifi";
878 reg-names = "membase";
879 memory-region = <&wlan_msa_mem>;
896 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
900 clock-names = "core", "iface";
902 dma-names = "rx", "tx";
903 pinctrl-names = "default";
904 pinctrl-0 = <&blsp1_uart3_default>;
909 compatible = "qcom,i2c-qup-v2.2.1";
914 clock-names = "iface", "core";
915 pinctrl-names = "default";
916 pinctrl-0 = <&blsp1_i2c0_default>;
917 #address-cells = <1>;
918 #size-cells = <0>;
923 compatible = "qcom,spi-qup-v2.2.1";
928 clock-names = "iface", "core";
929 pinctrl-names = "default";
930 pinctrl-0 = <&blsp1_spi0_default>;
931 #address-cells = <1>;
932 #size-cells = <0>;
937 compatible = "qcom,i2c-qup-v2.2.1";
942 clock-names = "iface", "core";
943 pinctrl-names = "default";
944 pinctrl-0 = <&blsp1_i2c1_default>;
945 #address-cells = <1>;
946 #size-cells = <0>;
951 compatible = "qcom,spi-qup-v2.2.1";
956 clock-names = "iface", "core";
957 pinctrl-names = "default";
958 pinctrl-0 = <&blsp1_spi1_default>;
959 #address-cells = <1>;
960 #size-cells = <0>;
965 compatible = "qcom,i2c-qup-v2.2.1";
970 clock-names = "iface", "core";
971 pinctrl-names = "default";
972 pinctrl-0 = <&blsp1_i2c2_default>;
973 #address-cells = <1>;
974 #size-cells = <0>;
979 compatible = "qcom,spi-qup-v2.2.1";
984 clock-names = "iface", "core";
985 pinctrl-names = "default";
986 pinctrl-0 = <&blsp1_spi2_default>;
987 #address-cells = <1>;
988 #size-cells = <0>;
993 compatible = "qcom,i2c-qup-v2.2.1";
998 clock-names = "iface", "core";
999 pinctrl-names = "default";
1000 pinctrl-0 = <&blsp1_i2c3_default>;
1001 #address-cells = <1>;
1002 #size-cells = <0>;
1007 compatible = "qcom,spi-qup-v2.2.1";
1012 clock-names = "iface", "core";
1013 pinctrl-names = "default";
1014 pinctrl-0 = <&blsp1_spi3_default>;
1015 #address-cells = <1>;
1016 #size-cells = <0>;
1021 compatible = "qcom,i2c-qup-v2.2.1";
1026 clock-names = "iface", "core";
1027 pinctrl-names = "default";
1028 pinctrl-0 = <&blsp1_i2c4_default>;
1029 #address-cells = <1>;
1030 #size-cells = <0>;
1035 compatible = "qcom,spi-qup-v2.2.1";
1040 clock-names = "iface", "core";
1041 pinctrl-names = "default";
1042 pinctrl-0 = <&blsp1_spi4_default>;
1043 #address-cells = <1>;
1044 #size-cells = <0>;
1049 compatible = "qcom,bam-v1.7.0";
1053 clock-names = "bam_clk";
1054 #dma-cells = <1>;
1060 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1064 clock-names = "core", "iface";
1066 dma-names = "rx", "tx";
1067 pinctrl-names = "default";
1068 pinctrl-0 = <&blsp2_uart0_default>;
1073 compatible = "qcom,i2c-qup-v2.2.1";
1078 clock-names = "iface", "core";
1079 pinctrl-names = "default";
1080 pinctrl-0 = <&blsp2_i2c0_default>;
1081 #address-cells = <1>;
1082 #size-cells = <0>;
1087 compatible = "qcom,spi-qup-v2.2.1";
1092 clock-names = "iface", "core";
1093 pinctrl-names = "default";
1094 pinctrl-0 = <&blsp2_spi0_default>;
1095 #address-cells = <1>;
1096 #size-cells = <0>;
1101 compatible = "simple-mfd";
1104 #address-cells = <1>;
1105 #size-cells = <1>;
1109 pil-reloc@94c {
1110 compatible = "qcom,pil-reloc-info";
1115 intc: interrupt-controller@b000000 {
1116 compatible = "qcom,msm-qgic2";
1117 interrupt-controller;
1118 #interrupt-cells = <3>;
1124 compatible = "qcom,qcs404-apcs-apps-global", "syscon";
1126 #mbox-cells = <1>;
1128 clock-names = "pll", "aux";
1129 #clock-cells = <0>;
1132 apcs_hfpll: clock-controller@b016000 {
1135 #clock-cells = <0>;
1136 clock-output-names = "apcs_hfpll";
1138 clock-names = "xo";
1142 compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt";
1147 cpr: power-controller@b018000 {
1148 compatible = "qcom,qcs404-cpr", "qcom,cpr";
1152 clock-names = "ref";
1153 vdd-apc-supply = <&pms405_s3>;
1154 #power-domain-cells = <0>;
1155 operating-points-v2 = <&cpr_opp_table>;
1156 acc-syscon = <&tcsr>;
1158 nvmem-cells = <&cpr_efuse_quot_offset1>,
1171 nvmem-cell-names = "cpr_quotient_offset1",
1187 #address-cells = <1>;
1188 #size-cells = <1>;
1190 compatible = "arm,armv7-timer-mem";
1192 clock-frequency = <19200000>;
1195 frame-number = <0>;
1203 frame-number = <1>;
1210 frame-number = <2>;
1217 frame-number = <3>;
1224 frame-number = <4>;
1231 frame-number = <5>;
1238 frame-number = <6>;
1246 compatible = "qcom,qcs404-adsp-pas";
1249 interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
1254 interrupt-names = "wdog", "fatal", "ready",
1255 "handover", "stop-ack";
1258 clock-names = "xo";
1260 memory-region = <&adsp_fw_mem>;
1262 qcom,smem-states = <&adsp_smp2p_out 0>;
1263 qcom,smem-state-names = "stop";
1267 glink-edge {
1270 qcom,remote-pid = <2>;
1278 compatible = "qcom,pcie-qcs404", "snps,dw-pcie";
1283 reg-names = "dbi", "elbi", "parf", "config";
1285 linux,pci-domain = <0>;
1286 bus-range = <0x00 0xff>;
1287 num-lanes = <1>;
1288 #address-cells = <3>;
1289 #size-cells = <2>;
1295 interrupt-names = "msi";
1296 #interrupt-cells = <1>;
1297 interrupt-map-mask = <0 0 0 0x7>;
1298 interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1306 clock-names = "iface", "aux", "master_bus", "slave_bus";
1314 reset-names = "axi_m",
1322 phy-names = "pciephy";
1329 compatible = "arm,armv8-timer";
1336 smp2p-adsp {
1341 qcom,local-pid = <0>;
1342 qcom,remote-pid = <2>;
1344 adsp_smp2p_out: master-kernel {
1345 qcom,entry-name = "master-kernel";
1346 #qcom,smem-state-cells = <1>;
1349 adsp_smp2p_in: slave-kernel {
1350 qcom,entry-name = "slave-kernel";
1351 interrupt-controller;
1352 #interrupt-cells = <2>;
1356 smp2p-cdsp {
1361 qcom,local-pid = <0>;
1362 qcom,remote-pid = <5>;
1364 cdsp_smp2p_out: master-kernel {
1365 qcom,entry-name = "master-kernel";
1366 #qcom,smem-state-cells = <1>;
1369 cdsp_smp2p_in: slave-kernel {
1370 qcom,entry-name = "slave-kernel";
1371 interrupt-controller;
1372 #interrupt-cells = <2>;
1376 smp2p-wcss {
1381 qcom,local-pid = <0>;
1382 qcom,remote-pid = <1>;
1384 wcss_smp2p_out: master-kernel {
1385 qcom,entry-name = "master-kernel";
1386 #qcom,smem-state-cells = <1>;
1389 wcss_smp2p_in: slave-kernel {
1390 qcom,entry-name = "slave-kernel";
1391 interrupt-controller;
1392 #interrupt-cells = <2>;
1396 thermal-zones {
1397 aoss-thermal {
1398 polling-delay-passive = <250>;
1399 polling-delay = <1000>;
1401 thermal-sensors = <&tsens 0>;
1404 aoss_alert0: trip-point0 {
1412 q6-hvx-thermal {
1413 polling-delay-passive = <250>;
1414 polling-delay = <1000>;
1416 thermal-sensors = <&tsens 1>;
1419 q6_hvx_alert0: trip-point0 {
1427 lpass-thermal {
1428 polling-delay-passive = <250>;
1429 polling-delay = <1000>;
1431 thermal-sensors = <&tsens 2>;
1434 lpass_alert0: trip-point0 {
1442 wlan-thermal {
1443 polling-delay-passive = <250>;
1444 polling-delay = <1000>;
1446 thermal-sensors = <&tsens 3>;
1449 wlan_alert0: trip-point0 {
1457 cluster-thermal {
1458 polling-delay-passive = <250>;
1459 polling-delay = <1000>;
1461 thermal-sensors = <&tsens 4>;
1464 cluster_alert0: trip-point0 {
1469 cluster_alert1: trip-point1 {
1480 cooling-maps {
1483 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1491 cpu0-thermal {
1492 polling-delay-passive = <250>;
1493 polling-delay = <1000>;
1495 thermal-sensors = <&tsens 5>;
1498 cpu0_alert0: trip-point0 {
1503 cpu0_alert1: trip-point1 {
1514 cooling-maps {
1517 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1525 cpu1-thermal {
1526 polling-delay-passive = <250>;
1527 polling-delay = <1000>;
1529 thermal-sensors = <&tsens 6>;
1532 cpu1_alert0: trip-point0 {
1537 cpu1_alert1: trip-point1 {
1548 cooling-maps {
1551 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1559 cpu2-thermal {
1560 polling-delay-passive = <250>;
1561 polling-delay = <1000>;
1563 thermal-sensors = <&tsens 7>;
1566 cpu2_alert0: trip-point0 {
1571 cpu2_alert1: trip-point1 {
1582 cooling-maps {
1585 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1593 cpu3-thermal {
1594 polling-delay-passive = <250>;
1595 polling-delay = <1000>;
1597 thermal-sensors = <&tsens 8>;
1600 cpu3_alert0: trip-point0 {
1605 cpu3_alert1: trip-point1 {
1616 cooling-maps {
1619 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1627 gpu-thermal {
1628 polling-delay-passive = <250>;
1629 polling-delay = <1000>;
1631 thermal-sensors = <&tsens 9>;
1634 gpu_alert0: trip-point0 {