Lines Matching +full:redistributor +full:- +full:stride
1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/power/qcom-rpmpd.h>
9 #include <dt-bindings/gpio/gpio.h>
12 interrupt-parent = <&intc>;
14 qcom,msm-id = <292 0x0>;
16 #address-cells = <2>;
17 #size-cells = <2>;
27 reserved-memory {
28 #address-cells = <2>;
29 #size-cells = <2>;
34 no-map;
39 no-map;
42 smem_mem: smem-mem@86000000 {
44 no-map;
49 no-map;
53 compatible = "qcom,rmtfs-mem";
55 no-map;
57 qcom,client-id = <1>;
63 no-map;
68 no-map;
73 no-map;
78 no-map;
83 no-map;
88 no-map;
93 no-map;
98 no-map;
103 no-map;
108 no-map;
113 xo: xo-board {
114 compatible = "fixed-clock";
115 #clock-cells = <0>;
116 clock-frequency = <19200000>;
117 clock-output-names = "xo_board";
121 compatible = "fixed-clock";
122 #clock-cells = <0>;
123 clock-frequency = <32764>;
128 #address-cells = <2>;
129 #size-cells = <0>;
135 enable-method = "psci";
136 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
137 next-level-cache = <&L2_0>;
138 L2_0: l2-cache {
139 compatible = "arm,arch-cache";
140 cache-level = <2>;
142 L1_I_0: l1-icache {
143 compatible = "arm,arch-cache";
145 L1_D_0: l1-dcache {
146 compatible = "arm,arch-cache";
154 enable-method = "psci";
155 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
156 next-level-cache = <&L2_0>;
157 L1_I_1: l1-icache {
158 compatible = "arm,arch-cache";
160 L1_D_1: l1-dcache {
161 compatible = "arm,arch-cache";
169 enable-method = "psci";
170 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
171 next-level-cache = <&L2_0>;
172 L1_I_2: l1-icache {
173 compatible = "arm,arch-cache";
175 L1_D_2: l1-dcache {
176 compatible = "arm,arch-cache";
184 enable-method = "psci";
185 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
186 next-level-cache = <&L2_0>;
187 L1_I_3: l1-icache {
188 compatible = "arm,arch-cache";
190 L1_D_3: l1-dcache {
191 compatible = "arm,arch-cache";
199 enable-method = "psci";
200 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
201 next-level-cache = <&L2_1>;
202 L2_1: l2-cache {
203 compatible = "arm,arch-cache";
204 cache-level = <2>;
206 L1_I_100: l1-icache {
207 compatible = "arm,arch-cache";
209 L1_D_100: l1-dcache {
210 compatible = "arm,arch-cache";
218 enable-method = "psci";
219 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
220 next-level-cache = <&L2_1>;
221 L1_I_101: l1-icache {
222 compatible = "arm,arch-cache";
224 L1_D_101: l1-dcache {
225 compatible = "arm,arch-cache";
233 enable-method = "psci";
234 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
235 next-level-cache = <&L2_1>;
236 L1_I_102: l1-icache {
237 compatible = "arm,arch-cache";
239 L1_D_102: l1-dcache {
240 compatible = "arm,arch-cache";
248 enable-method = "psci";
249 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
250 next-level-cache = <&L2_1>;
251 L1_I_103: l1-icache {
252 compatible = "arm,arch-cache";
254 L1_D_103: l1-dcache {
255 compatible = "arm,arch-cache";
259 cpu-map {
297 idle-states {
298 entry-method = "psci";
300 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
301 compatible = "arm,idle-state";
302 idle-state-name = "little-retention";
303 arm,psci-suspend-param = <0x00000002>;
304 entry-latency-us = <81>;
305 exit-latency-us = <86>;
306 min-residency-us = <200>;
309 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
310 compatible = "arm,idle-state";
311 idle-state-name = "little-power-collapse";
312 arm,psci-suspend-param = <0x40000003>;
313 entry-latency-us = <273>;
314 exit-latency-us = <612>;
315 min-residency-us = <1000>;
316 local-timer-stop;
319 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
320 compatible = "arm,idle-state";
321 idle-state-name = "big-retention";
322 arm,psci-suspend-param = <0x00000002>;
323 entry-latency-us = <79>;
324 exit-latency-us = <82>;
325 min-residency-us = <200>;
328 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
329 compatible = "arm,idle-state";
330 idle-state-name = "big-power-collapse";
331 arm,psci-suspend-param = <0x40000003>;
332 entry-latency-us = <336>;
333 exit-latency-us = <525>;
334 min-residency-us = <1000>;
335 local-timer-stop;
342 compatible = "qcom,scm-msm8998", "qcom,scm";
347 compatible = "qcom,tcsr-mutex";
349 #hwlock-cells = <1>;
353 compatible = "arm,psci-1.0";
357 rpm-glink {
358 compatible = "qcom,glink-rpm";
361 qcom,rpm-msg-ram = <&rpm_msg_ram>;
364 rpm_requests: rpm-requests {
365 compatible = "qcom,rpm-msm8998";
366 qcom,glink-channels = "rpm_requests";
368 rpmcc: clock-controller {
369 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
370 #clock-cells = <1>;
373 rpmpd: power-controller {
374 compatible = "qcom,msm8998-rpmpd";
375 #power-domain-cells = <1>;
376 operating-points-v2 = <&rpmpd_opp_table>;
378 rpmpd_opp_table: opp-table {
379 compatible = "operating-points-v2";
382 opp-level = <16>;
386 opp-level = <32>;
390 opp-level = <48>;
394 opp-level = <64>;
398 opp-level = <128>;
402 opp-level = <192>;
406 opp-level = <256>;
410 opp-level = <320>;
414 opp-level = <384>;
418 opp-level = <512>;
427 memory-region = <&smem_mem>;
431 smp2p-lpass {
439 qcom,local-pid = <0>;
440 qcom,remote-pid = <2>;
442 adsp_smp2p_out: master-kernel {
443 qcom,entry-name = "master-kernel";
444 #qcom,smem-state-cells = <1>;
447 adsp_smp2p_in: slave-kernel {
448 qcom,entry-name = "slave-kernel";
450 interrupt-controller;
451 #interrupt-cells = <2>;
455 smp2p-mpss {
460 qcom,local-pid = <0>;
461 qcom,remote-pid = <1>;
463 modem_smp2p_out: master-kernel {
464 qcom,entry-name = "master-kernel";
465 #qcom,smem-state-cells = <1>;
468 modem_smp2p_in: slave-kernel {
469 qcom,entry-name = "slave-kernel";
470 interrupt-controller;
471 #interrupt-cells = <2>;
475 smp2p-slpi {
480 qcom,local-pid = <0>;
481 qcom,remote-pid = <3>;
483 slpi_smp2p_out: master-kernel {
484 qcom,entry-name = "master-kernel";
485 #qcom,smem-state-cells = <1>;
488 slpi_smp2p_in: slave-kernel {
489 qcom,entry-name = "slave-kernel";
490 interrupt-controller;
491 #interrupt-cells = <2>;
495 thermal-zones {
496 cpu0-thermal {
497 polling-delay-passive = <250>;
498 polling-delay = <1000>;
500 thermal-sensors = <&tsens0 1>;
503 cpu0_alert0: trip-point0 {
517 cpu1-thermal {
518 polling-delay-passive = <250>;
519 polling-delay = <1000>;
521 thermal-sensors = <&tsens0 2>;
524 cpu1_alert0: trip-point0 {
538 cpu2-thermal {
539 polling-delay-passive = <250>;
540 polling-delay = <1000>;
542 thermal-sensors = <&tsens0 3>;
545 cpu2_alert0: trip-point0 {
559 cpu3-thermal {
560 polling-delay-passive = <250>;
561 polling-delay = <1000>;
563 thermal-sensors = <&tsens0 4>;
566 cpu3_alert0: trip-point0 {
580 cpu4-thermal {
581 polling-delay-passive = <250>;
582 polling-delay = <1000>;
584 thermal-sensors = <&tsens0 7>;
587 cpu4_alert0: trip-point0 {
601 cpu5-thermal {
602 polling-delay-passive = <250>;
603 polling-delay = <1000>;
605 thermal-sensors = <&tsens0 8>;
608 cpu5_alert0: trip-point0 {
622 cpu6-thermal {
623 polling-delay-passive = <250>;
624 polling-delay = <1000>;
626 thermal-sensors = <&tsens0 9>;
629 cpu6_alert0: trip-point0 {
643 cpu7-thermal {
644 polling-delay-passive = <250>;
645 polling-delay = <1000>;
647 thermal-sensors = <&tsens0 10>;
650 cpu7_alert0: trip-point0 {
664 gpu-thermal-bottom {
665 polling-delay-passive = <250>;
666 polling-delay = <1000>;
668 thermal-sensors = <&tsens0 12>;
671 gpu1_alert0: trip-point0 {
679 gpu-thermal-top {
680 polling-delay-passive = <250>;
681 polling-delay = <1000>;
683 thermal-sensors = <&tsens0 13>;
686 gpu2_alert0: trip-point0 {
694 clust0-mhm-thermal {
695 polling-delay-passive = <250>;
696 polling-delay = <1000>;
698 thermal-sensors = <&tsens0 5>;
701 cluster0_mhm_alert0: trip-point0 {
709 clust1-mhm-thermal {
710 polling-delay-passive = <250>;
711 polling-delay = <1000>;
713 thermal-sensors = <&tsens0 6>;
716 cluster1_mhm_alert0: trip-point0 {
724 cluster1-l2-thermal {
725 polling-delay-passive = <250>;
726 polling-delay = <1000>;
728 thermal-sensors = <&tsens0 11>;
731 cluster1_l2_alert0: trip-point0 {
739 modem-thermal {
740 polling-delay-passive = <250>;
741 polling-delay = <1000>;
743 thermal-sensors = <&tsens1 1>;
746 modem_alert0: trip-point0 {
754 mem-thermal {
755 polling-delay-passive = <250>;
756 polling-delay = <1000>;
758 thermal-sensors = <&tsens1 2>;
761 mem_alert0: trip-point0 {
769 wlan-thermal {
770 polling-delay-passive = <250>;
771 polling-delay = <1000>;
773 thermal-sensors = <&tsens1 3>;
776 wlan_alert0: trip-point0 {
784 q6-dsp-thermal {
785 polling-delay-passive = <250>;
786 polling-delay = <1000>;
788 thermal-sensors = <&tsens1 4>;
791 q6_dsp_alert0: trip-point0 {
799 camera-thermal {
800 polling-delay-passive = <250>;
801 polling-delay = <1000>;
803 thermal-sensors = <&tsens1 5>;
806 camera_alert0: trip-point0 {
814 multimedia-thermal {
815 polling-delay-passive = <250>;
816 polling-delay = <1000>;
818 thermal-sensors = <&tsens1 6>;
821 multimedia_alert0: trip-point0 {
831 compatible = "arm,armv8-timer";
839 #address-cells = <1>;
840 #size-cells = <1>;
842 compatible = "simple-bus";
844 gcc: clock-controller@100000 {
845 compatible = "qcom,gcc-msm8998";
846 #clock-cells = <1>;
847 #reset-cells = <1>;
848 #power-domain-cells = <1>;
853 compatible = "qcom,rpm-msg-ram";
860 #address-cells = <1>;
861 #size-cells = <1>;
863 qusb2_hstx_trim: hstx-trim@423a {
870 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
876 interrupt-names = "uplow", "critical";
877 #thermal-sensor-cells = <1>;
881 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
887 interrupt-names = "uplow", "critical";
888 #thermal-sensor-cells = <1>;
892 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
894 #iommu-cells = <1>;
896 #global-interrupts = <0>;
907 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
909 #iommu-cells = <1>;
911 #global-interrupts = <0>;
926 compatible = "qcom,pcie-msm8996";
931 reg-names = "parf", "dbi", "elbi", "config";
933 linux,pci-domain = <0>;
934 bus-range = <0x00 0xff>;
935 #address-cells = <3>;
936 #size-cells = <2>;
937 num-lanes = <1>;
939 phy-names = "pciephy";
944 #interrupt-cells = <1>;
946 interrupt-names = "msi";
947 interrupt-map-mask = <0 0 0 0x7>;
948 interrupt-map = <0 0 0 1 &intc 0 135 IRQ_TYPE_LEVEL_HIGH>,
958 clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux";
960 power-domains = <&gcc PCIE_0_GDSC>;
961 iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
962 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
966 compatible = "qcom,msm8998-qmp-pcie-phy";
968 #address-cells = <1>;
969 #size-cells = <1>;
975 clock-names = "aux", "cfg_ahb", "ref";
978 reset-names = "phy", "common";
980 vdda-phy-supply = <&vreg_l1a_0p875>;
981 vdda-pll-supply = <&vreg_l2a_1p2>;
985 #phy-cells = <0>;
988 clock-names = "pipe0";
989 clock-output-names = "pcie_0_pipe_clk_src";
990 #clock-cells = <0>;
995 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
999 phy-names = "ufsphy";
1000 lanes-per-direction = <2>;
1001 power-domains = <&gcc UFS_GDSC>;
1002 #reset-cells = <1>;
1004 clock-names =
1022 freq-table-hz =
1033 reset-names = "rst";
1037 compatible = "qcom,msm8998-qmp-ufs-phy";
1039 #address-cells = <1>;
1040 #size-cells = <1>;
1043 clock-names =
1050 reset-names = "ufsphy";
1059 #phy-cells = <0>;
1069 compatible = "qcom,msm8998-pinctrl";
1072 gpio-controller;
1073 #gpio-cells = <0x2>;
1074 interrupt-controller;
1075 #interrupt-cells = <0x2>;
1079 compatible = "qcom,msm8998-mss-pil";
1081 reg-names = "qdsp6", "rmb";
1083 interrupts-extended =
1090 interrupt-names = "wdog", "fatal", "ready",
1091 "handover", "stop-ack",
1092 "shutdown-ack";
1102 clock-names = "iface", "bus", "mem", "gpll0_mss",
1105 qcom,smem-states = <&modem_smp2p_out 0>;
1106 qcom,smem-state-names = "stop";
1109 reset-names = "mss_restart";
1111 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
1113 power-domains = <&rpmpd MSM8998_VDDCX>,
1115 power-domain-names = "cx", "mx";
1118 memory-region = <&mba_mem>;
1122 memory-region = <&mpss_mem>;
1125 glink-edge {
1128 qcom,remote-pid = <1>;
1133 gpucc: clock-controller@5065000 {
1134 compatible = "qcom,msm8998-gpucc";
1135 #clock-cells = <1>;
1136 #reset-cells = <1>;
1137 #power-domain-cells = <1>;
1142 clock-names = "xo",
1147 compatible = "qcom,msm8998-slpi-pas";
1150 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
1155 interrupt-names = "wdog", "fatal", "ready",
1156 "handover", "stop-ack";
1158 px-supply = <&vreg_lvs2a_1p8>;
1162 clock-names = "xo", "aggre2";
1164 memory-region = <&slpi_mem>;
1166 qcom,smem-states = <&slpi_smp2p_out 0>;
1167 qcom,smem-state-names = "stop";
1169 power-domains = <&rpmpd MSM8998_SSCCX>;
1170 power-domain-names = "ssc_cx";
1174 glink-edge {
1177 qcom,remote-pid = <3>;
1183 compatible = "arm,coresight-stm", "arm,primecell";
1186 reg-names = "stm-base", "stm-data-base";
1190 clock-names = "apb_pclk", "atclk";
1192 out-ports {
1195 remote-endpoint = <&funnel0_in7>;
1202 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1207 clock-names = "apb_pclk", "atclk";
1209 out-ports {
1212 remote-endpoint =
1218 in-ports {
1219 #address-cells = <1>;
1220 #size-cells = <0>;
1225 remote-endpoint = <&stm_out>;
1232 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1237 clock-names = "apb_pclk", "atclk";
1239 out-ports {
1242 remote-endpoint =
1248 in-ports {
1249 #address-cells = <1>;
1250 #size-cells = <0>;
1255 remote-endpoint =
1263 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1268 clock-names = "apb_pclk", "atclk";
1270 out-ports {
1273 remote-endpoint =
1279 in-ports {
1280 #address-cells = <1>;
1281 #size-cells = <0>;
1286 remote-endpoint =
1294 remote-endpoint =
1302 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1307 clock-names = "apb_pclk", "atclk";
1309 out-ports {
1312 remote-endpoint = <&etr_in>;
1317 in-ports {
1320 remote-endpoint = <&etf_out>;
1327 compatible = "arm,coresight-tmc", "arm,primecell";
1332 clock-names = "apb_pclk", "atclk";
1334 out-ports {
1337 remote-endpoint =
1343 in-ports {
1346 remote-endpoint =
1354 compatible = "arm,coresight-tmc", "arm,primecell";
1359 clock-names = "apb_pclk", "atclk";
1360 arm,scatter-gather;
1362 in-ports {
1365 remote-endpoint =
1373 compatible = "arm,coresight-etm4x", "arm,primecell";
1378 clock-names = "apb_pclk", "atclk";
1382 out-ports {
1385 remote-endpoint =
1393 compatible = "arm,coresight-etm4x", "arm,primecell";
1398 clock-names = "apb_pclk", "atclk";
1402 out-ports {
1405 remote-endpoint =
1413 compatible = "arm,coresight-etm4x", "arm,primecell";
1418 clock-names = "apb_pclk", "atclk";
1422 out-ports {
1425 remote-endpoint =
1433 compatible = "arm,coresight-etm4x", "arm,primecell";
1438 clock-names = "apb_pclk", "atclk";
1442 out-ports {
1445 remote-endpoint =
1453 compatible = "arm,coresight-etm4x", "arm,primecell";
1458 clock-names = "apb_pclk", "atclk";
1460 out-ports {
1463 remote-endpoint =
1469 in-ports {
1470 #address-cells = <1>;
1471 #size-cells = <0>;
1476 remote-endpoint =
1484 remote-endpoint =
1492 remote-endpoint =
1500 remote-endpoint =
1508 remote-endpoint =
1516 remote-endpoint =
1524 remote-endpoint =
1532 remote-endpoint =
1540 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1545 clock-names = "apb_pclk", "atclk";
1547 out-ports {
1550 remote-endpoint =
1556 in-ports {
1559 remote-endpoint =
1567 compatible = "arm,coresight-etm4x", "arm,primecell";
1572 clock-names = "apb_pclk", "atclk";
1578 remote-endpoint = <&apss_funnel_in4>;
1584 compatible = "arm,coresight-etm4x", "arm,primecell";
1589 clock-names = "apb_pclk", "atclk";
1595 remote-endpoint = <&apss_funnel_in5>;
1601 compatible = "arm,coresight-etm4x", "arm,primecell";
1606 clock-names = "apb_pclk", "atclk";
1612 remote-endpoint = <&apss_funnel_in6>;
1618 compatible = "arm,coresight-etm4x", "arm,primecell";
1623 clock-names = "apb_pclk", "atclk";
1629 remote-endpoint = <&apss_funnel_in7>;
1635 compatible = "qcom,spmi-pmic-arb";
1641 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1642 interrupt-names = "periph_irq";
1646 #address-cells = <2>;
1647 #size-cells = <0>;
1648 interrupt-controller;
1649 #interrupt-cells = <4>;
1650 cell-index = <0>;
1654 compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
1657 #address-cells = <1>;
1658 #size-cells = <1>;
1666 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1669 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1671 assigned-clock-rates = <19200000>, <120000000>;
1675 interrupt-names = "hs_phy_irq", "ss_phy_irq";
1677 power-domains = <&gcc USB_30_GDSC>;
1688 phy-names = "usb2-phy", "usb3-phy";
1689 snps,has-lpm-erratum;
1690 snps,hird-threshold = /bits/ 8 <0x10>;
1695 compatible = "qcom,msm8998-qmp-usb3-phy";
1698 #clock-cells = <1>;
1699 #address-cells = <1>;
1700 #size-cells = <1>;
1706 clock-names = "aux", "cfg_ahb", "ref";
1710 reset-names = "phy", "common";
1718 #phy-cells = <0>;
1720 clock-names = "pipe0";
1721 clock-output-names = "usb3_phy_pipe_clk_src";
1726 compatible = "qcom,msm8998-qusb2-phy";
1729 #phy-cells = <0>;
1733 clock-names = "cfg_ahb", "ref";
1737 nvmem-cells = <&qusb2_hstx_trim>;
1741 compatible = "qcom,sdhci-msm-v4";
1743 reg-names = "hc_mem", "core_mem";
1747 interrupt-names = "hc_irq", "pwr_irq";
1749 clock-names = "iface", "core", "xo";
1753 bus-width = <4>;
1758 compatible = "qcom,bam-v1.7.0";
1762 clock-names = "bam_clk";
1763 #dma-cells = <1>;
1765 qcom,controlled-remotely;
1766 num-channels = <18>;
1767 qcom,num-ees = <4>;
1771 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1776 clock-names = "core", "iface";
1778 dma-names = "tx", "rx";
1779 pinctrl-names = "default";
1780 pinctrl-0 = <&blsp1_uart3_on>;
1785 compatible = "qcom,i2c-qup-v2.2.1";
1791 clock-names = "core", "iface";
1792 clock-frequency = <400000>;
1795 #address-cells = <1>;
1796 #size-cells = <0>;
1800 compatible = "qcom,i2c-qup-v2.2.1";
1806 clock-names = "core", "iface";
1807 clock-frequency = <400000>;
1810 #address-cells = <1>;
1811 #size-cells = <0>;
1815 compatible = "qcom,i2c-qup-v2.2.1";
1821 clock-names = "core", "iface";
1822 clock-frequency = <400000>;
1825 #address-cells = <1>;
1826 #size-cells = <0>;
1830 compatible = "qcom,i2c-qup-v2.2.1";
1836 clock-names = "core", "iface";
1837 clock-frequency = <400000>;
1840 #address-cells = <1>;
1841 #size-cells = <0>;
1845 compatible = "qcom,i2c-qup-v2.2.1";
1851 clock-names = "core", "iface";
1852 clock-frequency = <400000>;
1855 #address-cells = <1>;
1856 #size-cells = <0>;
1860 compatible = "qcom,i2c-qup-v2.2.1";
1866 clock-names = "core", "iface";
1867 clock-frequency = <400000>;
1870 #address-cells = <1>;
1871 #size-cells = <0>;
1875 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1880 clock-names = "core", "iface";
1885 compatible = "qcom,i2c-qup-v2.2.1";
1891 clock-names = "core", "iface";
1892 clock-frequency = <400000>;
1895 #address-cells = <1>;
1896 #size-cells = <0>;
1900 compatible = "qcom,i2c-qup-v2.2.1";
1906 clock-names = "core", "iface";
1907 clock-frequency = <400000>;
1910 #address-cells = <1>;
1911 #size-cells = <0>;
1915 compatible = "qcom,i2c-qup-v2.2.1";
1921 clock-names = "core", "iface";
1922 clock-frequency = <400000>;
1925 #address-cells = <1>;
1926 #size-cells = <0>;
1930 compatible = "qcom,i2c-qup-v2.2.1";
1936 clock-names = "core", "iface";
1937 clock-frequency = <400000>;
1940 #address-cells = <1>;
1941 #size-cells = <0>;
1945 compatible = "qcom,i2c-qup-v2.2.1";
1951 clock-names = "core", "iface";
1952 clock-frequency = <400000>;
1955 #address-cells = <1>;
1956 #size-cells = <0>;
1960 compatible = "qcom,i2c-qup-v2.2.1";
1966 clock-names = "core", "iface";
1967 clock-frequency = <400000>;
1970 #address-cells = <1>;
1971 #size-cells = <0>;
1975 compatible = "qcom,msm8998-adsp-pas";
1978 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
1983 interrupt-names = "wdog", "fatal", "ready",
1984 "handover", "stop-ack";
1987 clock-names = "xo";
1989 memory-region = <&adsp_mem>;
1991 qcom,smem-states = <&adsp_smp2p_out 0>;
1992 qcom,smem-state-names = "stop";
1994 power-domains = <&rpmpd MSM8998_VDDCX>;
1995 power-domain-names = "cx";
1999 glink-edge {
2002 qcom,remote-pid = <2>;
2008 compatible = "qcom,msm8998-apcs-hmss-global";
2011 #mbox-cells = <1>;
2015 #address-cells = <1>;
2016 #size-cells = <1>;
2018 compatible = "arm,armv7-timer-mem";
2022 frame-number = <0>;
2030 frame-number = <1>;
2037 frame-number = <2>;
2044 frame-number = <3>;
2051 frame-number = <4>;
2058 frame-number = <5>;
2065 frame-number = <6>;
2072 intc: interrupt-controller@17a00000 {
2073 compatible = "arm,gic-v3";
2076 #interrupt-cells = <3>;
2077 #address-cells = <1>;
2078 #size-cells = <1>;
2080 interrupt-controller;
2081 #redistributor-regions = <1>;
2082 redistributor-stride = <0x0 0x20000>;
2087 compatible = "qcom,wcn3990-wifi";
2090 reg-names = "membase";
2091 memory-region = <&wlan_msa_mem>;
2093 clock-names = "cxo_ref_clk_pin";
2109 qcom,snoc-host-cap-8bit-quirk;
2114 #include "msm8998-pins.dtsi"