Lines Matching refs:gcc
7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
93 clocks = <&gcc GCC_USB1_AUX_CLK>,
94 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
98 resets = <&gcc GCC_USB1_PHY_BCR>,
99 <&gcc GCC_USB3PHY_1_PHY_BCR>;
109 clocks = <&gcc GCC_USB1_PIPE_CLK>;
120 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
124 resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
136 clocks = <&gcc GCC_USB0_AUX_CLK>,
137 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
141 resets = <&gcc GCC_USB0_PHY_BCR>,
142 <&gcc GCC_USB3PHY_0_PHY_BCR>;
152 clocks = <&gcc GCC_USB0_PIPE_CLK>;
163 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
167 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
174 clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
178 resets = <&gcc GCC_PCIE0_PHY_BCR>,
179 <&gcc GCC_PCIE0PHY_PHY_BCR>;
189 clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
193 resets = <&gcc GCC_PCIE1_PHY_BCR>,
194 <&gcc GCC_PCIE1PHY_PHY_BCR>;
250 gcc: gcc@1800000 { label
251 compatible = "qcom,gcc-ipq8074";
267 <&gcc GCC_SDCC1_AHB_CLK>,
268 <&gcc GCC_SDCC1_APPS_CLK>;
283 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
293 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
294 <&gcc GCC_BLSP1_AHB_CLK>;
303 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
304 <&gcc GCC_BLSP1_AHB_CLK>;
318 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
319 <&gcc GCC_BLSP1_AHB_CLK>;
333 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
334 <&gcc GCC_BLSP1_AHB_CLK>;
349 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
350 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
366 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
367 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
379 clocks = <&gcc GCC_QPIC_AHB_CLK>;
391 clocks = <&gcc GCC_QPIC_CLK>,
392 <&gcc GCC_QPIC_AHB_CLK>;
411 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
412 <&gcc GCC_USB0_MASTER_CLK>,
413 <&gcc GCC_USB0_SLEEP_CLK>,
414 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
420 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
421 <&gcc GCC_USB0_MASTER_CLK>,
422 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
427 resets = <&gcc GCC_USB0_BCR>;
452 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
453 <&gcc GCC_USB1_MASTER_CLK>,
454 <&gcc GCC_USB1_SLEEP_CLK>,
455 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
461 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
462 <&gcc GCC_USB1_MASTER_CLK>,
463 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
468 resets = <&gcc GCC_USB1_BCR>;
603 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
604 <&gcc GCC_PCIE1_AXI_M_CLK>,
605 <&gcc GCC_PCIE1_AXI_S_CLK>,
606 <&gcc GCC_PCIE1_AHB_CLK>,
607 <&gcc GCC_PCIE1_AUX_CLK>;
613 resets = <&gcc GCC_PCIE1_PIPE_ARES>,
614 <&gcc GCC_PCIE1_SLEEP_ARES>,
615 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
616 <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
617 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
618 <&gcc GCC_PCIE1_AHB_ARES>,
619 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
665 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
666 <&gcc GCC_PCIE0_AXI_M_CLK>,
667 <&gcc GCC_PCIE0_AXI_S_CLK>,
668 <&gcc GCC_PCIE0_AHB_CLK>,
669 <&gcc GCC_PCIE0_AUX_CLK>;
676 resets = <&gcc GCC_PCIE0_PIPE_ARES>,
677 <&gcc GCC_PCIE0_SLEEP_ARES>,
678 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
679 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
680 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
681 <&gcc GCC_PCIE0_AHB_ARES>,
682 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;