Lines Matching +full:ipq8074 +full:- +full:wcss +full:- +full:pil
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
11 #include <dt-bindings/clock/qcom,apss-ipq.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&intc>;
19 sleep_clk: sleep-clk {
20 compatible = "fixed-clock";
21 clock-frequency = <32000>;
22 #clock-cells = <0>;
26 compatible = "fixed-clock";
27 clock-frequency = <24000000>;
28 #clock-cells = <0>;
33 #address-cells = <1>;
34 #size-cells = <0>;
38 compatible = "arm,cortex-a53";
40 enable-method = "psci";
41 next-level-cache = <&L2_0>;
43 clock-names = "cpu";
44 operating-points-v2 = <&cpu_opp_table>;
45 cpu-supply = <&ipq6018_s2>;
50 compatible = "arm,cortex-a53";
51 enable-method = "psci";
53 next-level-cache = <&L2_0>;
55 clock-names = "cpu";
56 operating-points-v2 = <&cpu_opp_table>;
57 cpu-supply = <&ipq6018_s2>;
62 compatible = "arm,cortex-a53";
63 enable-method = "psci";
65 next-level-cache = <&L2_0>;
67 clock-names = "cpu";
68 operating-points-v2 = <&cpu_opp_table>;
69 cpu-supply = <&ipq6018_s2>;
74 compatible = "arm,cortex-a53";
75 enable-method = "psci";
77 next-level-cache = <&L2_0>;
79 clock-names = "cpu";
80 operating-points-v2 = <&cpu_opp_table>;
81 cpu-supply = <&ipq6018_s2>;
84 L2_0: l2-cache {
86 cache-level = <0x2>;
91 compatible = "operating-points-v2";
92 opp-shared;
94 opp-864000000 {
95 opp-hz = /bits/ 64 <864000000>;
96 opp-microvolt = <725000>;
97 clock-latency-ns = <200000>;
99 opp-1056000000 {
100 opp-hz = /bits/ 64 <1056000000>;
101 opp-microvolt = <787500>;
102 clock-latency-ns = <200000>;
104 opp-1320000000 {
105 opp-hz = /bits/ 64 <1320000000>;
106 opp-microvolt = <862500>;
107 clock-latency-ns = <200000>;
109 opp-1440000000 {
110 opp-hz = /bits/ 64 <1440000000>;
111 opp-microvolt = <925000>;
112 clock-latency-ns = <200000>;
114 opp-1608000000 {
115 opp-hz = /bits/ 64 <1608000000>;
116 opp-microvolt = <987500>;
117 clock-latency-ns = <200000>;
119 opp-1800000000 {
120 opp-hz = /bits/ 64 <1800000000>;
121 opp-microvolt = <1062500>;
122 clock-latency-ns = <200000>;
133 compatible = "qcom,tcsr-mutex";
135 #hwlock-cells = <1>;
139 compatible = "arm,cortex-a53-pmu";
145 compatible = "arm,psci-1.0";
149 reserved-memory {
150 #address-cells = <2>;
151 #size-cells = <2>;
156 no-map;
161 no-map;
166 no-map;
171 no-map;
177 memory-region = <&smem_region>;
182 #address-cells = <2>;
183 #size-cells = <2>;
185 dma-ranges;
186 compatible = "simple-bus";
189 compatible = "qcom,prng-ee";
192 clock-names = "core";
196 compatible = "qcom,bam-v1.7.0";
200 clock-names = "bam_clk";
201 #dma-cells = <1>;
203 qcom,controlled-remotely = <1>;
204 qcom,config-pipe-trust-reg = <0>;
208 compatible = "qcom,crypto-v5.1";
213 clock-names = "iface", "bus", "core";
215 dma-names = "rx", "tx";
219 compatible = "qcom,ipq6018-pinctrl";
222 gpio-controller;
223 #gpio-cells = <2>;
224 gpio-ranges = <&tlmm 0 80>;
225 interrupt-controller;
226 #interrupt-cells = <2>;
228 serial_3_pins: serial3-pinmux {
231 drive-strength = <8>;
232 bias-pull-down;
237 compatible = "qcom,gcc-ipq6018";
240 clock-names = "xo", "sleep_clk";
241 #clock-cells = <1>;
242 #reset-cells = <1>;
256 compatible = "qcom,bam-v1.7.0";
260 clock-names = "bam_clk";
261 #dma-cells = <1>;
266 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
271 clock-names = "core", "iface";
276 compatible = "qcom,spi-qup-v2.2.1";
277 #address-cells = <1>;
278 #size-cells = <0>;
281 spi-max-frequency = <50000000>;
284 clock-names = "core", "iface";
286 dma-names = "tx", "rx";
291 compatible = "qcom,spi-qup-v2.2.1";
292 #address-cells = <1>;
293 #size-cells = <0>;
296 spi-max-frequency = <50000000>;
299 clock-names = "core", "iface";
301 dma-names = "tx", "rx";
306 compatible = "qcom,i2c-qup-v2.2.1";
307 #address-cells = <1>;
308 #size-cells = <0>;
313 clock-names = "iface", "core";
314 clock-frequency = <400000>;
316 dma-names = "rx", "tx";
321 compatible = "qcom,i2c-qup-v2.2.1";
322 #address-cells = <1>;
323 #size-cells = <0>;
328 clock-names = "iface", "core";
329 clock-frequency = <400000>;
331 dma-names = "rx", "tx";
335 intc: interrupt-controller@b000000 {
336 compatible = "qcom,msm-qgic2";
337 interrupt-controller;
338 #interrupt-cells = <0x3>;
347 compatible = "qcom,kpss-wdt";
351 timeout-sec = <10>;
355 compatible = "qcom,ipq6018-apcs-apps-global";
357 #clock-cells = <1>;
359 clock-names = "pll", "xo";
360 #mbox-cells = <1>;
364 compatible = "qcom,ipq6018-a53pll";
366 #clock-cells = <0>;
368 clock-names = "xo";
372 compatible = "arm,armv8-timer";
380 #address-cells = <2>;
381 #size-cells = <2>;
383 compatible = "arm,armv7-timer-mem";
385 clock-frequency = <19200000>;
388 frame-number = <0>;
396 frame-number = <1>;
403 frame-number = <2>;
410 frame-number = <3>;
417 frame-number = <4>;
424 frame-number = <5>;
431 frame-number = <6>;
439 compatible = "qcom,ipq8074-wcss-pil";
442 reg-names = "qdsp6",
444 interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
449 interrupt-names = "wdog",
453 "stop-ack";
459 reset-names = "wcss_aon_reset",
464 clock-names = "prng";
466 qcom,halt-regs = <&tcsr_q6 0xa000 0xd000 0x0>;
468 qcom,smem-states = <&wcss_smp2p_out 0>,
470 qcom,smem-state-names = "shutdown",
473 memory-region = <&q6_region>;
475 glink-edge {
477 qcom,remote-pid = <1>;
481 qcom,glink-channels = "IPCRTR";
488 wcss: wcss-smp2p { label
492 interrupt-parent = <&intc>;
497 qcom,local-pid = <0>;
498 qcom,remote-pid = <1>;
500 wcss_smp2p_out: master-kernel {
501 qcom,entry-name = "master-kernel";
502 #qcom,smem-state-cells = <1>;
505 wcss_smp2p_in: slave-kernel {
506 qcom,entry-name = "slave-kernel";
507 interrupt-controller;
508 #interrupt-cells = <2>;
512 rpm-glink {
513 compatible = "qcom,glink-rpm";
515 qcom,rpm-msg-ram = <&rpm_msg_ram>;
518 rpm_requests: glink-channel {
519 compatible = "qcom,rpm-ipq6018";
520 qcom,glink-channels = "rpm_requests";
523 compatible = "qcom,rpm-mp5496-regulators";
526 regulator-min-microvolt = <725000>;
527 regulator-max-microvolt = <1062500>;
528 regulator-always-on;