Lines Matching +full:0 +full:x34000000
19 bus@0 {
23 ranges = <0x0 0x0 0x0 0x40000000>;
27 reg = <0x00100000 0xf000>,
28 <0x0010f000 0x1000>;
34 reg = <0x2200000 0x10000>,
35 <0x2210000 0x10000>;
52 reg = <0x02490000 0x10000>;
69 snps,burst-map = <0x7>;
83 ranges = <0x02900000 0x02900000 0x200000>;
89 reg = <0x02930000 0x20000>;
91 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
134 reg = <0x02a41000 0x1000>,
135 <0x02a42000 0x2000>;
147 reg = <0x02900800 0x800>;
154 ranges = <0x02900800 0x02900800 0x11800>;
160 reg = <0x0290f000 0x1000>;
207 reg = <0x2901000 0x100>;
221 reg = <0x2901100 0x100>;
235 reg = <0x2901200 0x100>;
249 reg = <0x2901300 0x100>;
263 reg = <0x2901400 0x100>;
277 reg = <0x2901500 0x100>;
291 reg = <0x2904000 0x100>;
304 reg = <0x2904100 0x100>;
317 reg = <0x2904200 0x100>;
330 reg = <0x2904300 0x100>;
343 reg = <0x2905000 0x100>;
356 reg = <0x2905100 0x100>;
370 reg = <0x2430000 0x17000>,
371 <0xc300000 0x4000>;
402 reg = <0x02c00000 0x100000>,
403 <0x02b80000 0x040000>,
404 <0x01700000 0x100000>;
412 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>,
413 <0x02b80000 0x0 0x02b80000 0x0 0x040000>,
414 <0x02c00000 0x0 0x02c00000 0x0 0x100000>;
429 * Limit the DMA range for memory clients to [38:0].
431 dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
435 reg = <0x0 0x02c60000 0x0 0x90000>,
436 <0x0 0x01780000 0x0 0x80000>;
440 #interconnect-cells = <0>;
448 reg = <0x03100000 0x40>;
460 reg = <0x03110000 0x40>;
472 reg = <0x03130000 0x40>;
484 reg = <0x03140000 0x40>;
496 reg = <0x03150000 0x40>;
508 reg = <0x03160000 0x10000>;
511 #size-cells = <0>;
521 reg = <0x03170000 0x40>;
533 reg = <0x03180000 0x10000>;
536 #size-cells = <0>;
547 reg = <0x03190000 0x10000>;
550 #size-cells = <0>;
555 pinctrl-0 = <&state_dpaux1_i2c>;
564 reg = <0x031b0000 0x10000>;
567 #size-cells = <0>;
572 pinctrl-0 = <&state_dpaux0_i2c>;
581 reg = <0x031c0000 0x10000>;
584 #size-cells = <0>;
589 pinctrl-0 = <&state_dpaux2_i2c>;
598 reg = <0x031e0000 0x10000>;
601 #size-cells = <0>;
606 pinctrl-0 = <&state_dpaux3_i2c>;
615 reg = <0x3280000 0x10000>;
627 reg = <0x3290000 0x10000>;
639 reg = <0x32a0000 0x10000>;
651 reg = <0x32c0000 0x10000>;
663 reg = <0x32d0000 0x10000>;
675 reg = <0x32e0000 0x10000>;
687 reg = <0x32f0000 0x10000>;
698 reg = <0x03400000 0x10000>;
709 <0x07>;
711 <0x07>;
712 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
714 <0x07>;
715 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
716 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
717 nvidia,default-tap = <0x9>;
718 nvidia,default-trim = <0x5>;
724 reg = <0x03440000 0x10000>;
734 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
735 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
736 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
738 <0x07>;
739 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
741 <0x07>;
742 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
743 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
744 nvidia,default-tap = <0x9>;
745 nvidia,default-trim = <0x5>;
751 reg = <0x03460000 0x10000>;
765 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
766 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
767 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
769 <0x0a>;
770 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
772 <0x0a>;
773 nvidia,default-tap = <0x8>;
774 nvidia,default-trim = <0x14>;
782 reg = <0x3510000 0x10000>;
801 reg = <0x03520000 0x1000>,
802 <0x03540000 0x1000>;
816 usb2-0 {
819 #phy-cells = <0>;
825 #phy-cells = <0>;
831 #phy-cells = <0>;
837 #phy-cells = <0>;
844 usb3-0 {
847 #phy-cells = <0>;
853 #phy-cells = <0>;
859 #phy-cells = <0>;
865 #phy-cells = <0>;
872 usb2-0 {
888 usb3-0 {
908 reg = <0x03550000 0x8000>,
909 <0x03558000 0x1000>;
926 reg = <0x03610000 0x40000>,
927 <0x03600000 0x10000>;
957 reg = <0x03820000 0x10000>;
966 reg = <0x03881000 0x1000>,
967 <0x03882000 0x2000>,
968 <0x03884000 0x2000>,
969 <0x03886000 0x2000>;
977 reg = <0x03960000 0x10000>;
986 reg = <0x03c00000 0xa0000>;
1004 reg = <0x03e10000 0x10000>;
1007 #phy-cells = <0>;
1012 reg = <0x03e20000 0x10000>;
1015 #phy-cells = <0>;
1020 reg = <0x03e30000 0x10000>;
1023 #phy-cells = <0>;
1028 reg = <0x03e40000 0x10000>;
1031 #phy-cells = <0>;
1036 reg = <0x03e50000 0x10000>;
1039 #phy-cells = <0>;
1044 reg = <0x03e60000 0x10000>;
1047 #phy-cells = <0>;
1052 reg = <0x03e70000 0x10000>;
1055 #phy-cells = <0>;
1060 reg = <0x03e80000 0x10000>;
1063 #phy-cells = <0>;
1068 reg = <0x03e90000 0x10000>;
1071 #phy-cells = <0>;
1076 reg = <0x03ea0000 0x10000>;
1079 #phy-cells = <0>;
1084 reg = <0x03eb0000 0x10000>;
1087 #phy-cells = <0>;
1092 reg = <0x03ec0000 0x10000>;
1095 #phy-cells = <0>;
1100 reg = <0x03ed0000 0x10000>;
1103 #phy-cells = <0>;
1108 reg = <0x03ee0000 0x10000>;
1111 #phy-cells = <0>;
1116 reg = <0x03ef0000 0x10000>;
1119 #phy-cells = <0>;
1124 reg = <0x03f00000 0x10000>;
1127 #phy-cells = <0>;
1132 reg = <0x03f10000 0x10000>;
1135 #phy-cells = <0>;
1140 reg = <0x03f20000 0x10000>;
1143 #phy-cells = <0>;
1148 reg = <0x03f30000 0x10000>;
1151 #phy-cells = <0>;
1156 reg = <0x03f40000 0x10000>;
1159 #phy-cells = <0>;
1164 reg = <0x0c150000 0x90000>;
1170 * Shared interrupt 0 is routed only to AON/SPE, so
1179 reg = <0x0c240000 0x10000>;
1182 #size-cells = <0>;
1192 reg = <0x0c250000 0x10000>;
1195 #size-cells = <0>;
1205 reg = <0x0c280000 0x40>;
1217 reg = <0x0c290000 0x40>;
1229 reg = <0x0c2a0000 0x10000>;
1240 reg = <0xc2f0000 0x1000>,
1241 <0xc2f1000 0x1000>;
1252 reg = <0xc340000 0x10000>;
1263 reg = <0x0c360000 0x10000>,
1264 <0x0c370000 0x10000>,
1265 <0x0c380000 0x10000>,
1266 <0x0c390000 0x10000>,
1267 <0x0c3a0000 0x10000>;
1276 reg = <0x13e00000 0x10000>,
1277 <0x13e10000 0x10000>;
1290 ranges = <0x15000000 0x15000000 0x01000000>;
1296 reg = <0x15200000 0x00040000>;
1316 ranges = <0x15200000 0x15200000 0x40000>;
1320 reg = <0x15200000 0x10000>;
1333 nvidia,head = <0>;
1338 reg = <0x15210000 0x10000>;
1356 reg = <0x15220000 0x10000>;
1374 reg = <0x15230000 0x10000>;
1393 reg = <0x15340000 0x00040000>;
1408 reg = <0x155c0000 0x10000>;
1436 #size-cells = <0>;
1442 reg = <0x155d0000 0x10000>;
1470 #size-cells = <0>;
1476 reg = <0x155e0000 0x10000>;
1504 #size-cells = <0>;
1510 reg = <0x155f0000 0x10000>;
1538 #size-cells = <0>;
1544 reg = <0x15b00000 0x40000>;
1556 pinctrl-0 = <&state_dpaux0_aux>;
1563 nvidia,interface = <0>;
1568 reg = <0x15b40000 0x40000>;
1580 pinctrl-0 = <&state_dpaux1_aux>;
1592 reg = <0x15b80000 0x40000>;
1604 pinctrl-0 = <&state_dpaux2_aux>;
1616 reg = <0x15bc0000 0x40000>;
1628 pinctrl-0 = <&state_dpaux3_aux>;
1641 reg = <0x17000000 0x1000000>,
1642 <0x18000000 0x1000000>;
1667 interconnect-names = "dma-mem", "read-0-hp", "write-0",
1677 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */
1678 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
1679 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
1680 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */
1704 interrupt-map-mask = <0 0 0 0>;
1705 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1713 bus-range = <0x0 0xff>;
1715 …ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 …
1716 …<0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB -…
1717 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
1727 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */
1728 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
1729 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
1730 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */
1754 interrupt-map-mask = <0 0 0 0>;
1755 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1763 bus-range = <0x0 0xff>;
1765 …ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 …
1766 …<0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB -…
1767 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
1777 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */
1778 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
1779 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
1780 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */
1804 interrupt-map-mask = <0 0 0 0>;
1805 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1813 bus-range = <0x0 0xff>;
1815 …ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 …
1816 …<0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB +…
1817 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
1827 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
1828 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
1829 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
1830 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
1854 interrupt-map-mask = <0 0 0 0>;
1855 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1863 bus-range = <0x0 0xff>;
1865 …ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 G…
1866 …<0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 6…
1867 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
1877 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
1878 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
1879 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
1880 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
1890 linux,pci-domain = <0>;
1904 interrupt-map-mask = <0 0 0 0>;
1905 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1907 nvidia,bpmp = <&bpmp 0>;
1913 bus-range = <0x0 0xff>;
1915 …ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 G…
1916 …<0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 6…
1917 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
1927 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
1928 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
1929 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
1930 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */
1943 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
1960 interrupt-map-mask = <0 0 0 0>;
1961 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1967 bus-range = <0x0 0xff>;
1969 …ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 G…
1970 …<0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 6…
1971 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
1981 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
1982 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
1983 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */
1984 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
2013 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
2014 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2015 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */
2016 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
2035 nvidia,bpmp = <&bpmp 0>;
2045 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
2046 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2047 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
2048 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
2058 pinctrl-0 = <&clkreq_c5_bi_dir_state>;
2079 reg = <0x0 0x40000000 0x0 0x50000>;
2082 ranges = <0x0 0x0 0x40000000 0x50000>;
2085 reg = <0x4e000 0x1000>;
2091 reg = <0x4f000 0x1000>;
2115 #size-cells = <0>;
2128 #size-cells = <0>;
2130 cpu0_0: cpu@0 {
2133 reg = <0x000>;
2147 reg = <0x001>;
2161 reg = <0x100>;
2175 reg = <0x101>;
2189 reg = <0x200>;
2203 reg = <0x201>;
2217 reg = <0x300>;
2231 reg = <0x301>;
2327 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,