Lines Matching +full:gic +full:- +full:v3
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "nvidia,tegra186-misc";
25 compatible = "nvidia,tegra186-gpio";
26 reg-names = "security", "gpio";
35 #interrupt-cells = <2>;
36 interrupt-controller;
37 #gpio-cells = <2>;
38 gpio-controller;
42 compatible = "nvidia,tegra186-eqos",
43 "snps,dwc-qos-ethernet-4.10";
60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
62 reset-names = "eqos";
65 interconnect-names = "dma-mem", "write";
69 snps,write-requests = <1>;
70 snps,read-requests = <3>;
71 snps,burst-map = <0x7>;
77 compatible = "nvidia,tegra186-aconnect",
78 "nvidia,tegra210-aconnect";
81 clock-names = "ape", "apb2ape";
82 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
83 #address-cells = <1>;
84 #size-cells = <1>;
88 adma: dma-controller@2930000 {
89 compatible = "nvidia,tegra186-adma";
91 interrupt-parent = <&agic>;
124 #dma-cells = <1>;
126 clock-names = "d_audio";
130 agic: interrupt-controller@2a40000 {
131 compatible = "nvidia,tegra186-agic",
132 "nvidia,tegra210-agic";
133 #interrupt-cells = <3>;
134 interrupt-controller;
140 clock-names = "clk";
145 compatible = "nvidia,tegra186-ahub";
148 clock-names = "ahub";
149 assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
150 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
151 #address-cells = <1>;
152 #size-cells = <1>;
157 compatible = "nvidia,tegra186-admaif";
179 dma-names = "rx1", "tx1",
203 compatible = "nvidia,tegra186-i2s",
204 "nvidia,tegra210-i2s";
208 clock-names = "i2s", "sync_input";
209 assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>;
210 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
211 assigned-clock-rates = <1536000>;
212 sound-name-prefix = "I2S1";
217 compatible = "nvidia,tegra186-i2s",
218 "nvidia,tegra210-i2s";
222 clock-names = "i2s", "sync_input";
223 assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>;
224 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
225 assigned-clock-rates = <1536000>;
226 sound-name-prefix = "I2S2";
231 compatible = "nvidia,tegra186-i2s",
232 "nvidia,tegra210-i2s";
236 clock-names = "i2s", "sync_input";
237 assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>;
238 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
239 assigned-clock-rates = <1536000>;
240 sound-name-prefix = "I2S3";
245 compatible = "nvidia,tegra186-i2s",
246 "nvidia,tegra210-i2s";
250 clock-names = "i2s", "sync_input";
251 assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>;
252 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
253 assigned-clock-rates = <1536000>;
254 sound-name-prefix = "I2S4";
259 compatible = "nvidia,tegra186-i2s",
260 "nvidia,tegra210-i2s";
264 clock-names = "i2s", "sync_input";
265 assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>;
266 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
267 assigned-clock-rates = <1536000>;
268 sound-name-prefix = "I2S5";
273 compatible = "nvidia,tegra186-i2s",
274 "nvidia,tegra210-i2s";
278 clock-names = "i2s", "sync_input";
279 assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>;
280 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
281 assigned-clock-rates = <1536000>;
282 sound-name-prefix = "I2S6";
287 compatible = "nvidia,tegra210-dmic";
290 clock-names = "dmic";
291 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>;
292 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
293 assigned-clock-rates = <3072000>;
294 sound-name-prefix = "DMIC1";
299 compatible = "nvidia,tegra210-dmic";
302 clock-names = "dmic";
303 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>;
304 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
305 assigned-clock-rates = <3072000>;
306 sound-name-prefix = "DMIC2";
311 compatible = "nvidia,tegra210-dmic";
314 clock-names = "dmic";
315 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>;
316 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
317 assigned-clock-rates = <3072000>;
318 sound-name-prefix = "DMIC3";
323 compatible = "nvidia,tegra210-dmic";
326 clock-names = "dmic";
327 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>;
328 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
329 assigned-clock-rates = <3072000>;
330 sound-name-prefix = "DMIC4";
335 compatible = "nvidia,tegra186-dspk";
338 clock-names = "dspk";
339 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>;
340 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
341 assigned-clock-rates = <12288000>;
342 sound-name-prefix = "DSPK1";
347 compatible = "nvidia,tegra186-dspk";
350 clock-names = "dspk";
351 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>;
352 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
353 assigned-clock-rates = <12288000>;
354 sound-name-prefix = "DSPK2";
360 mc: memory-controller@2c00000 {
361 compatible = "nvidia,tegra186-mc";
366 #interconnect-cells = <1>;
367 #address-cells = <2>;
368 #size-cells = <2>;
376 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
378 emc: external-memory-controller@2c60000 {
379 compatible = "nvidia,tegra186-emc";
383 clock-names = "emc";
385 #interconnect-cells = <0>;
392 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
394 reg-shift = <2>;
397 clock-names = "serial";
399 reset-names = "serial";
404 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
406 reg-shift = <2>;
409 clock-names = "serial";
411 reset-names = "serial";
416 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
418 reg-shift = <2>;
421 clock-names = "serial";
423 reset-names = "serial";
428 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
430 reg-shift = <2>;
433 clock-names = "serial";
435 reset-names = "serial";
440 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
442 reg-shift = <2>;
445 clock-names = "serial";
447 reset-names = "serial";
452 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
455 #address-cells = <1>;
456 #size-cells = <0>;
458 clock-names = "div-clk";
460 reset-names = "i2c";
465 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
468 #address-cells = <1>;
469 #size-cells = <0>;
471 clock-names = "div-clk";
473 reset-names = "i2c";
479 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
482 #address-cells = <1>;
483 #size-cells = <0>;
485 clock-names = "div-clk";
487 reset-names = "i2c";
488 pinctrl-names = "default", "idle";
489 pinctrl-0 = <&state_dpaux1_i2c>;
490 pinctrl-1 = <&state_dpaux1_off>;
496 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
499 #address-cells = <1>;
500 #size-cells = <0>;
502 clock-names = "div-clk";
504 reset-names = "i2c";
510 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
513 #address-cells = <1>;
514 #size-cells = <0>;
516 clock-names = "div-clk";
518 reset-names = "i2c";
519 pinctrl-names = "default", "idle";
520 pinctrl-0 = <&state_dpaux_i2c>;
521 pinctrl-1 = <&state_dpaux_off>;
526 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
529 #address-cells = <1>;
530 #size-cells = <0>;
532 clock-names = "div-clk";
534 reset-names = "i2c";
539 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
542 #address-cells = <1>;
543 #size-cells = <0>;
545 clock-names = "div-clk";
547 reset-names = "i2c";
552 compatible = "nvidia,tegra186-sdhci";
557 clock-names = "sdhci", "tmclk";
559 reset-names = "sdhci";
562 interconnect-names = "dma-mem", "write";
564 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
565 pinctrl-0 = <&sdmmc1_3v3>;
566 pinctrl-1 = <&sdmmc1_1v8>;
567 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
568 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
569 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
570 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
571 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
572 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
573 nvidia,default-tap = <0x5>;
574 nvidia,default-trim = <0xb>;
575 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
577 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
582 compatible = "nvidia,tegra186-sdhci";
587 clock-names = "sdhci", "tmclk";
589 reset-names = "sdhci";
592 interconnect-names = "dma-mem", "write";
594 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
595 pinctrl-0 = <&sdmmc2_3v3>;
596 pinctrl-1 = <&sdmmc2_1v8>;
597 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
598 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
599 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
600 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
601 nvidia,default-tap = <0x5>;
602 nvidia,default-trim = <0xb>;
607 compatible = "nvidia,tegra186-sdhci";
612 clock-names = "sdhci", "tmclk";
614 reset-names = "sdhci";
617 interconnect-names = "dma-mem", "write";
619 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
620 pinctrl-0 = <&sdmmc3_3v3>;
621 pinctrl-1 = <&sdmmc3_1v8>;
622 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
623 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
624 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
625 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
626 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
627 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
628 nvidia,default-tap = <0x5>;
629 nvidia,default-trim = <0xb>;
634 compatible = "nvidia,tegra186-sdhci";
639 clock-names = "sdhci", "tmclk";
640 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
642 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
644 reset-names = "sdhci";
647 interconnect-names = "dma-mem", "write";
649 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
650 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
651 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
652 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
653 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
654 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
655 nvidia,default-tap = <0x9>;
656 nvidia,default-trim = <0x5>;
657 nvidia,dqs-trim = <63>;
658 mmc-hs400-1_8v;
659 supports-cqe;
664 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda";
670 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
674 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
675 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
678 interconnect-names = "dma-mem", "write";
684 compatible = "nvidia,tegra186-xusb-padctl";
687 reg-names = "padctl", "ao";
690 reset-names = "padctl";
697 clock-names = "trk";
701 usb2-0 {
703 #phy-cells = <0>;
706 usb2-1 {
708 #phy-cells = <0>;
711 usb2-2 {
713 #phy-cells = <0>;
720 clock-names = "trk";
724 hsic-0 {
726 #phy-cells = <0>;
735 usb3-0 {
737 #phy-cells = <0>;
740 usb3-1 {
742 #phy-cells = <0>;
745 usb3-2 {
747 #phy-cells = <0>;
754 usb2-0 {
758 usb2-1 {
762 usb2-2 {
766 hsic-0 {
770 usb3-0 {
774 usb3-1 {
778 usb3-2 {
785 compatible = "nvidia,tegra186-xusb";
788 reg-names = "hcd", "fpci";
800 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss",
803 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
805 power-domain-names = "xusb_host", "xusb_ss";
808 interconnect-names = "dma-mem", "write";
810 #address-cells = <1>;
811 #size-cells = <0>;
814 nvidia,xusb-padctl = <&padctl>;
818 compatible = "nvidia,tegra186-xudc";
821 reg-names = "base", "fpci";
827 clock-names = "dev", "ss", "ss_src", "fs_src";
829 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>,
831 power-domain-names = "dev", "ss";
832 nvidia,xusb-padctl = <&padctl>;
837 compatible = "nvidia,tegra186-efuse";
840 clock-names = "fuse";
843 gic: interrupt-controller@3881000 { label
844 compatible = "arm,gic-400";
845 #interrupt-cells = <3>;
846 interrupt-controller;
851 interrupt-parent = <&gic>;
855 compatible = "nvidia,tegra186-cec";
859 clock-names = "cec";
864 compatible = "nvidia,tegra186-hsp";
867 interrupt-names = "doorbell";
868 #mbox-cells = <2>;
873 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
876 #address-cells = <1>;
877 #size-cells = <0>;
879 clock-names = "div-clk";
881 reset-names = "i2c";
886 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
889 #address-cells = <1>;
890 #size-cells = <0>;
892 clock-names = "div-clk";
894 reset-names = "i2c";
899 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
901 reg-shift = <2>;
904 clock-names = "serial";
906 reset-names = "serial";
911 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
913 reg-shift = <2>;
916 clock-names = "serial";
918 reset-names = "serial";
923 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc";
925 interrupt-parent = <&pmc>;
928 clock-names = "rtc";
933 compatible = "nvidia,tegra186-gpio-aon";
934 reg-names = "security", "gpio";
938 gpio-controller;
939 #gpio-cells = <2>;
940 interrupt-controller;
941 #interrupt-cells = <2>;
945 compatible = "nvidia,tegra186-pmc";
950 reg-names = "pmc", "wake", "aotag", "scratch";
952 #interrupt-cells = <2>;
953 interrupt-controller;
955 sdmmc1_3v3: sdmmc1-3v3 {
956 pins = "sdmmc1-hv";
957 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
960 sdmmc1_1v8: sdmmc1-1v8 {
961 pins = "sdmmc1-hv";
962 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
965 sdmmc2_3v3: sdmmc2-3v3 {
966 pins = "sdmmc2-hv";
967 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
970 sdmmc2_1v8: sdmmc2-1v8 {
971 pins = "sdmmc2-hv";
972 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
975 sdmmc3_3v3: sdmmc3-3v3 {
976 pins = "sdmmc3-hv";
977 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
980 sdmmc3_1v8: sdmmc3-1v8 {
981 pins = "sdmmc3-hv";
982 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
987 compatible = "nvidia,tegra186-ccplex-cluster";
994 compatible = "nvidia,tegra186-pcie";
995 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
1000 reg-names = "pads", "afi", "cs";
1004 interrupt-names = "intr", "msi";
1006 #interrupt-cells = <1>;
1007 interrupt-map-mask = <0 0 0 0>;
1008 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1010 bus-range = <0x00 0xff>;
1011 #address-cells = <3>;
1012 #size-cells = <2>;
1018 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */
1024 clock-names = "pex", "afi", "pll_e";
1029 reset-names = "pex", "afi", "pcie_x";
1033 interconnect-names = "dma-mem", "write";
1036 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>;
1037 iommu-map-mask = <0x0>;
1043 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
1047 #address-cells = <3>;
1048 #size-cells = <2>;
1051 nvidia,num-lanes = <2>;
1056 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
1060 #address-cells = <3>;
1061 #size-cells = <2>;
1064 nvidia,num-lanes = <1>;
1069 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
1073 #address-cells = <3>;
1074 #size-cells = <2>;
1077 nvidia,num-lanes = <1>;
1082 compatible = "arm,mmu-500";
1149 stream-match-mask = <0x7f80>;
1150 #global-interrupts = <1>;
1151 #iommu-cells = <1>;
1155 compatible = "nvidia,tegra186-host1x";
1158 reg-names = "hypervisor", "vm";
1161 interrupt-names = "syncpt", "host1x";
1163 clock-names = "host1x";
1165 reset-names = "host1x";
1167 #address-cells = <1>;
1168 #size-cells = <1>;
1173 interconnect-names = "dma-mem";
1178 compatible = "nvidia,tegra186-dpaux";
1183 clock-names = "dpaux", "parent";
1185 reset-names = "dpaux";
1188 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1190 state_dpaux1_aux: pinmux-aux {
1191 groups = "dpaux-io";
1195 state_dpaux1_i2c: pinmux-i2c {
1196 groups = "dpaux-io";
1200 state_dpaux1_off: pinmux-off {
1201 groups = "dpaux-io";
1205 i2c-bus {
1206 #address-cells = <1>;
1207 #size-cells = <0>;
1211 display-hub@15200000 {
1212 compatible = "nvidia,tegra186-display";
1221 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1226 clock-names = "disp", "dsc", "hub";
1229 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1231 #address-cells = <1>;
1232 #size-cells = <1>;
1237 compatible = "nvidia,tegra186-dc";
1241 clock-names = "dc";
1243 reset-names = "dc";
1245 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1248 interconnect-names = "dma-mem", "read-1";
1256 compatible = "nvidia,tegra186-dc";
1260 clock-names = "dc";
1262 reset-names = "dc";
1264 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
1267 interconnect-names = "dma-mem", "read-1";
1275 compatible = "nvidia,tegra186-dc";
1279 clock-names = "dc";
1281 reset-names = "dc";
1283 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
1286 interconnect-names = "dma-mem", "read-1";
1295 compatible = "nvidia,tegra186-dsi";
1301 clock-names = "dsi", "lp", "parent";
1303 reset-names = "dsi";
1306 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1310 compatible = "nvidia,tegra186-vic";
1314 clock-names = "vic";
1316 reset-names = "vic";
1318 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
1321 interconnect-names = "dma-mem", "write";
1326 compatible = "nvidia,tegra186-dsi";
1332 clock-names = "dsi", "lp", "parent";
1334 reset-names = "dsi";
1337 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1341 compatible = "nvidia,tegra186-sor";
1350 clock-names = "sor", "out", "parent", "dp", "safe",
1353 reset-names = "sor";
1354 pinctrl-0 = <&state_dpaux_aux>;
1355 pinctrl-1 = <&state_dpaux_i2c>;
1356 pinctrl-2 = <&state_dpaux_off>;
1357 pinctrl-names = "aux", "i2c", "off";
1360 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1365 compatible = "nvidia,tegra186-sor";
1374 clock-names = "sor", "out", "parent", "dp", "safe",
1377 reset-names = "sor";
1378 pinctrl-0 = <&state_dpaux1_aux>;
1379 pinctrl-1 = <&state_dpaux1_i2c>;
1380 pinctrl-2 = <&state_dpaux1_off>;
1381 pinctrl-names = "aux", "i2c", "off";
1384 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1389 compatible = "nvidia,tegra186-dpaux";
1394 clock-names = "dpaux", "parent";
1396 reset-names = "dpaux";
1399 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1401 state_dpaux_aux: pinmux-aux {
1402 groups = "dpaux-io";
1406 state_dpaux_i2c: pinmux-i2c {
1407 groups = "dpaux-io";
1411 state_dpaux_off: pinmux-off {
1412 groups = "dpaux-io";
1416 i2c-bus {
1417 #address-cells = <1>;
1418 #size-cells = <0>;
1423 compatible = "nvidia,tegra186-dsi-padctl";
1426 reset-names = "dsi";
1431 compatible = "nvidia,tegra186-dsi";
1437 clock-names = "dsi", "lp", "parent";
1439 reset-names = "dsi";
1442 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1446 compatible = "nvidia,tegra186-dsi";
1452 clock-names = "dsi", "lp", "parent";
1454 reset-names = "dsi";
1457 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1467 interrupt-names = "stall", "nonstall";
1471 clock-names = "gpu", "pwr";
1473 reset-names = "gpu";
1476 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
1481 interconnect-names = "dma-mem", "write-0", "read-1", "write-1";
1485 compatible = "nvidia,tegra186-sysram", "mmio-sram";
1487 #address-cells = <1>;
1488 #size-cells = <1>;
1493 label = "cpu-bpmp-tx";
1499 label = "cpu-bpmp-rx";
1505 compatible = "nvidia,tegra186-bpmp";
1510 interconnect-names = "read", "write", "dma-mem", "dma-write";
1515 #clock-cells = <1>;
1516 #reset-cells = <1>;
1517 #power-domain-cells = <1>;
1520 compatible = "nvidia,tegra186-bpmp-i2c";
1521 nvidia,bpmp-bus-id = <5>;
1522 #address-cells = <1>;
1523 #size-cells = <0>;
1528 compatible = "nvidia,tegra186-bpmp-thermal";
1529 #thermal-sensor-cells = <1>;
1534 #address-cells = <1>;
1535 #size-cells = <0>;
1538 compatible = "nvidia,tegra186-denver";
1540 i-cache-size = <0x20000>;
1541 i-cache-line-size = <64>;
1542 i-cache-sets = <512>;
1543 d-cache-size = <0x10000>;
1544 d-cache-line-size = <64>;
1545 d-cache-sets = <256>;
1546 next-level-cache = <&L2_DENVER>;
1551 compatible = "nvidia,tegra186-denver";
1553 i-cache-size = <0x20000>;
1554 i-cache-line-size = <64>;
1555 i-cache-sets = <512>;
1556 d-cache-size = <0x10000>;
1557 d-cache-line-size = <64>;
1558 d-cache-sets = <256>;
1559 next-level-cache = <&L2_DENVER>;
1564 compatible = "arm,cortex-a57";
1566 i-cache-size = <0xC000>;
1567 i-cache-line-size = <64>;
1568 i-cache-sets = <256>;
1569 d-cache-size = <0x8000>;
1570 d-cache-line-size = <64>;
1571 d-cache-sets = <256>;
1572 next-level-cache = <&L2_A57>;
1577 compatible = "arm,cortex-a57";
1579 i-cache-size = <0xC000>;
1580 i-cache-line-size = <64>;
1581 i-cache-sets = <256>;
1582 d-cache-size = <0x8000>;
1583 d-cache-line-size = <64>;
1584 d-cache-sets = <256>;
1585 next-level-cache = <&L2_A57>;
1590 compatible = "arm,cortex-a57";
1592 i-cache-size = <0xC000>;
1593 i-cache-line-size = <64>;
1594 i-cache-sets = <256>;
1595 d-cache-size = <0x8000>;
1596 d-cache-line-size = <64>;
1597 d-cache-sets = <256>;
1598 next-level-cache = <&L2_A57>;
1603 compatible = "arm,cortex-a57";
1605 i-cache-size = <0xC000>;
1606 i-cache-line-size = <64>;
1607 i-cache-sets = <256>;
1608 d-cache-size = <0x8000>;
1609 d-cache-line-size = <64>;
1610 d-cache-sets = <256>;
1611 next-level-cache = <&L2_A57>;
1615 L2_DENVER: l2-cache0 {
1617 cache-unified;
1618 cache-level = <2>;
1619 cache-size = <0x200000>;
1620 cache-line-size = <64>;
1621 cache-sets = <2048>;
1624 L2_A57: l2-cache1 {
1626 cache-unified;
1627 cache-level = <2>;
1628 cache-size = <0x200000>;
1629 cache-line-size = <64>;
1630 cache-sets = <2048>;
1634 thermal-zones {
1636 polling-delay = <0>;
1637 polling-delay-passive = <1000>;
1639 thermal-sensors =
1650 cooling-maps {
1655 polling-delay = <0>;
1656 polling-delay-passive = <1000>;
1658 thermal-sensors =
1669 cooling-maps {
1674 polling-delay = <0>;
1675 polling-delay-passive = <1000>;
1677 thermal-sensors =
1688 cooling-maps {
1693 polling-delay = <0>;
1694 polling-delay-passive = <1000>;
1696 thermal-sensors =
1707 cooling-maps {
1712 polling-delay = <0>;
1713 polling-delay-passive = <1000>;
1715 thermal-sensors =
1726 cooling-maps {
1732 compatible = "arm,armv8-timer";
1741 interrupt-parent = <&gic>;
1742 always-on;