Lines Matching +full:0 +full:x17000000
20 reg = <0x0 0x00100000 0x0 0xf000>,
21 <0x0 0x0010f000 0x0 0x1000>;
27 reg = <0x0 0x2200000 0x0 0x10000>,
28 <0x0 0x2210000 0x0 0x10000>;
44 reg = <0x0 0x02490000 0x0 0x10000>;
71 snps,burst-map = <0x7>;
85 ranges = <0x02900000 0x0 0x02900000 0x200000>;
90 reg = <0x02930000 0x20000>;
92 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
135 reg = <0x02a41000 0x1000>,
136 <0x02a42000 0x2000>;
146 reg = <0x02900800 0x800>;
153 ranges = <0x02900800 0x02900800 0x11800>;
158 reg = <0x0290f000 0x1000>;
205 reg = <0x2901000 0x100>;
219 reg = <0x2901100 0x100>;
233 reg = <0x2901200 0x100>;
247 reg = <0x2901300 0x100>;
261 reg = <0x2901400 0x100>;
275 reg = <0x2901500 0x100>;
288 reg = <0x2904000 0x100>;
300 reg = <0x2904100 0x100>;
312 reg = <0x2904200 0x100>;
324 reg = <0x2904300 0x100>;
336 reg = <0x2905000 0x100>;
348 reg = <0x2905100 0x100>;
362 reg = <0x0 0x02c00000 0x0 0xb0000>;
370 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
376 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
380 reg = <0x0 0x02c60000 0x0 0x50000>;
385 #interconnect-cells = <0>;
393 reg = <0x0 0x03100000 0x0 0x40>;
405 reg = <0x0 0x03110000 0x0 0x40>;
417 reg = <0x0 0x03130000 0x0 0x40>;
429 reg = <0x0 0x03140000 0x0 0x40>;
441 reg = <0x0 0x03150000 0x0 0x40>;
453 reg = <0x0 0x03160000 0x0 0x10000>;
456 #size-cells = <0>;
466 reg = <0x0 0x03180000 0x0 0x10000>;
469 #size-cells = <0>;
480 reg = <0x0 0x03190000 0x0 0x10000>;
483 #size-cells = <0>;
489 pinctrl-0 = <&state_dpaux1_i2c>;
497 reg = <0x0 0x031a0000 0x0 0x10000>;
500 #size-cells = <0>;
511 reg = <0x0 0x031b0000 0x0 0x10000>;
514 #size-cells = <0>;
520 pinctrl-0 = <&state_dpaux_i2c>;
527 reg = <0x0 0x031c0000 0x0 0x10000>;
530 #size-cells = <0>;
540 reg = <0x0 0x031e0000 0x0 0x10000>;
543 #size-cells = <0>;
553 reg = <0x0 0x03400000 0x0 0x10000>;
565 pinctrl-0 = <&sdmmc1_3v3>;
567 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
568 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
569 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
570 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
571 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
572 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
573 nvidia,default-tap = <0x5>;
574 nvidia,default-trim = <0xb>;
583 reg = <0x0 0x03420000 0x0 0x10000>;
595 pinctrl-0 = <&sdmmc2_3v3>;
597 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
598 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
599 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
600 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
601 nvidia,default-tap = <0x5>;
602 nvidia,default-trim = <0xb>;
608 reg = <0x0 0x03440000 0x0 0x10000>;
620 pinctrl-0 = <&sdmmc3_3v3>;
622 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
623 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
624 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
625 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
626 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
627 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
628 nvidia,default-tap = <0x5>;
629 nvidia,default-trim = <0xb>;
635 reg = <0x0 0x03460000 0x0 0x10000>;
649 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
650 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
651 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
652 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
653 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
654 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
655 nvidia,default-tap = <0x9>;
656 nvidia,default-trim = <0x5>;
665 reg = <0x0 0x03510000 0x0 0x10000>;
685 reg = <0x0 0x03520000 0x0 0x1000>,
686 <0x0 0x03540000 0x0 0x1000>;
701 usb2-0 {
703 #phy-cells = <0>;
708 #phy-cells = <0>;
713 #phy-cells = <0>;
724 hsic-0 {
726 #phy-cells = <0>;
735 usb3-0 {
737 #phy-cells = <0>;
742 #phy-cells = <0>;
747 #phy-cells = <0>;
754 usb2-0 {
766 hsic-0 {
770 usb3-0 {
786 reg = <0x0 0x03530000 0x0 0x8000>,
787 <0x0 0x03538000 0x0 0x1000>;
811 #size-cells = <0>;
819 reg = <0x0 0x03550000 0x0 0x8000>,
820 <0x0 0x03558000 0x0 0x1000>;
838 reg = <0x0 0x03820000 0x0 0x10000>;
847 reg = <0x0 0x03881000 0x0 0x1000>,
848 <0x0 0x03882000 0x0 0x2000>;
856 reg = <0x0 0x03960000 0x0 0x10000>;
865 reg = <0x0 0x03c00000 0x0 0xa0000>;
874 reg = <0x0 0x0c240000 0x0 0x10000>;
877 #size-cells = <0>;
887 reg = <0x0 0x0c250000 0x0 0x10000>;
890 #size-cells = <0>;
900 reg = <0x0 0x0c280000 0x0 0x40>;
912 reg = <0x0 0x0c290000 0x0 0x40>;
924 reg = <0 0x0c2a0000 0 0x10000>;
935 reg = <0x0 0xc2f0000 0x0 0x1000>,
936 <0x0 0xc2f1000 0x0 0x1000>;
946 reg = <0 0x0c360000 0 0x10000>,
947 <0 0x0c370000 0 0x10000>,
948 <0 0x0c380000 0 0x10000>,
949 <0 0x0c390000 0 0x10000>;
988 reg = <0x0 0x0e000000 0x0 0x3fffff>;
997 reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */
998 <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */
999 <0x0 0x40000000 0x0 0x10000000>; /* configuration space */
1007 interrupt-map-mask = <0 0 0 0>;
1008 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1010 bus-range = <0x00 0xff>;
1014 ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */
1015 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */
1016 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */
1017 <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */
1018 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */
1019 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
1036 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>;
1037 iommu-map-mask = <0x0>;
1041 pci@1,0 {
1043 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
1044 reg = <0x000800 0 0 0 0>;
1054 pci@2,0 {
1056 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
1057 reg = <0x001000 0 0 0 0>;
1067 pci@3,0 {
1069 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
1070 reg = <0x001800 0 0 0 0>;
1083 reg = <0 0x12000000 0 0x800000>;
1149 stream-match-mask = <0x7f80>;
1156 reg = <0x0 0x13e00000 0x0 0x10000>,
1157 <0x0 0x13e10000 0x0 0x10000>;
1170 ranges = <0x15000000 0x0 0x15000000 0x01000000>;
1179 reg = <0x15040000 0x10000>;
1207 #size-cells = <0>;
1213 reg = <0x15200000 0x00040000>;
1234 ranges = <0x15200000 0x15200000 0x40000>;
1238 reg = <0x15200000 0x10000>;
1252 nvidia,head = <0>;
1257 reg = <0x15210000 0x10000>;
1276 reg = <0x15220000 0x10000>;
1296 reg = <0x15300000 0x10000>;
1311 reg = <0x15340000 0x40000>;
1327 reg = <0x15400000 0x10000>;
1342 reg = <0x15540000 0x10000>;
1354 pinctrl-0 = <&state_dpaux_aux>;
1361 nvidia,interface = <0>;
1366 reg = <0x15580000 0x10000>;
1378 pinctrl-0 = <&state_dpaux1_aux>;
1390 reg = <0x155c0000 0x10000>;
1418 #size-cells = <0>;
1424 reg = <0x15880000 0x10000>;
1432 reg = <0x15900000 0x10000>;
1447 reg = <0x15940000 0x10000>;
1463 reg = <0x0 0x17000000 0x0 0x1000000>,
1464 <0x0 0x18000000 0x0 0x1000000>;
1481 interconnect-names = "dma-mem", "write-0", "read-1", "write-1";
1486 reg = <0x0 0x30000000 0x0 0x50000>;
1489 ranges = <0x0 0x0 0x30000000 0x50000>;
1492 reg = <0x4e000 0x1000>;
1498 reg = <0x4f000 0x1000>;
1523 #size-cells = <0>;
1535 #size-cells = <0>;
1537 cpu@0 {
1540 i-cache-size = <0x20000>;
1543 d-cache-size = <0x10000>;
1547 reg = <0x000>;
1553 i-cache-size = <0x20000>;
1556 d-cache-size = <0x10000>;
1560 reg = <0x001>;
1566 i-cache-size = <0xC000>;
1569 d-cache-size = <0x8000>;
1573 reg = <0x100>;
1579 i-cache-size = <0xC000>;
1582 d-cache-size = <0x8000>;
1586 reg = <0x101>;
1592 i-cache-size = <0xC000>;
1595 d-cache-size = <0x8000>;
1599 reg = <0x102>;
1605 i-cache-size = <0xC000>;
1608 d-cache-size = <0x8000>;
1612 reg = <0x103>;
1619 cache-size = <0x200000>;
1628 cache-size = <0x200000>;
1636 polling-delay = <0>;
1645 hysteresis = <0>;
1655 polling-delay = <0>;
1664 hysteresis = <0>;
1674 polling-delay = <0>;
1683 hysteresis = <0>;
1693 polling-delay = <0>;
1702 hysteresis = <0>;
1712 polling-delay = <0>;
1721 hysteresis = <0>;