Lines Matching full:topckgen
58 <&topckgen CLK_TOP_MAINPLL_D2>;
71 <&topckgen CLK_TOP_MAINPLL_D2>;
84 <&topckgen CLK_TOP_MAINPLL_D2>;
97 <&topckgen CLK_TOP_MAINPLL_D2>;
182 topckgen: topckgen@10000000 { label
183 compatible = "mediatek,mt8516-topckgen", "syscon";
218 clocks = <&topckgen CLK_TOP_CLK26M_D2>,
219 <&topckgen CLK_TOP_APXGPT>;
245 clocks = <&topckgen CLK_TOP_PMICWRAP_26M>,
246 <&topckgen CLK_TOP_PMICWRAP_AP>;
277 clocks = <&topckgen CLK_TOP_UART0_SEL>,
278 <&topckgen CLK_TOP_UART0>;
288 clocks = <&topckgen CLK_TOP_UART1_SEL>,
289 <&topckgen CLK_TOP_UART1>;
299 clocks = <&topckgen CLK_TOP_UART2_SEL>,
300 <&topckgen CLK_TOP_UART2>;
311 clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>,
313 <&topckgen CLK_TOP_I2C0>,
314 <&topckgen CLK_TOP_APDMA>;
330 clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>,
332 <&topckgen CLK_TOP_I2C1>,
333 <&topckgen CLK_TOP_APDMA>;
349 clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>,
351 <&topckgen CLK_TOP_I2C2>,
352 <&topckgen CLK_TOP_APDMA>;
369 clocks = <&topckgen CLK_TOP_UNIVPLL_D12>,
370 <&topckgen CLK_TOP_SPI_SEL>,
371 <&topckgen CLK_TOP_SPI>;
380 clocks = <&topckgen CLK_TOP_MSDC0>,
381 <&topckgen CLK_TOP_AHB_INFRA_SEL>,
382 <&topckgen CLK_TOP_MSDC0_INFRA>;
391 clocks = <&topckgen CLK_TOP_MSDC1>,
392 <&topckgen CLK_TOP_AHB_INFRA_SEL>,
393 <&topckgen CLK_TOP_MSDC1_INFRA>;
402 clocks = <&topckgen CLK_TOP_MSDC2>,
403 <&topckgen CLK_TOP_RG_MSDC2>,
404 <&topckgen CLK_TOP_MSDC2_INFRA>;
414 clocks = <&topckgen CLK_TOP_RG_ETH>,
415 <&topckgen CLK_TOP_66M_ETH>,
416 <&topckgen CLK_TOP_133M_ETH>;
425 clocks = <&topckgen CLK_TOP_TRNG>;
434 clocks = <&topckgen CLK_TOP_PWM>,
435 <&topckgen CLK_TOP_PWM_B>,
436 <&topckgen CLK_TOP_PWM1_FB>,
437 <&topckgen CLK_TOP_PWM2_FB>,
438 <&topckgen CLK_TOP_PWM3_FB>,
439 <&topckgen CLK_TOP_PWM4_FB>,
440 <&topckgen CLK_TOP_PWM5_FB>;
451 clocks = <&topckgen CLK_TOP_USB>,
452 <&topckgen CLK_TOP_USBIF>,
453 <&topckgen CLK_TOP_USB_1P>;
468 clocks = <&topckgen CLK_TOP_USB_PHY48M>;