Lines Matching +full:ppi +full:- +full:partitions
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt8183-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/reset-controller/mt8183-resets.h>
12 #include <dt-bindings/phy/phy.h>
13 #include "mt8183-pinfunc.h"
17 interrupt-parent = <&sysirq>;
18 #address-cells = <2>;
19 #size-cells = <2>;
37 #address-cells = <1>;
38 #size-cells = <0>;
40 cpu-map {
74 compatible = "arm,cortex-a53";
76 enable-method = "psci";
77 capacity-dmips-mhz = <741>;
78 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
79 dynamic-power-coefficient = <84>;
80 #cooling-cells = <2>;
85 compatible = "arm,cortex-a53";
87 enable-method = "psci";
88 capacity-dmips-mhz = <741>;
89 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
90 dynamic-power-coefficient = <84>;
91 #cooling-cells = <2>;
96 compatible = "arm,cortex-a53";
98 enable-method = "psci";
99 capacity-dmips-mhz = <741>;
100 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
101 dynamic-power-coefficient = <84>;
102 #cooling-cells = <2>;
107 compatible = "arm,cortex-a53";
109 enable-method = "psci";
110 capacity-dmips-mhz = <741>;
111 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
112 dynamic-power-coefficient = <84>;
113 #cooling-cells = <2>;
118 compatible = "arm,cortex-a73";
120 enable-method = "psci";
121 capacity-dmips-mhz = <1024>;
122 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
123 dynamic-power-coefficient = <211>;
124 #cooling-cells = <2>;
129 compatible = "arm,cortex-a73";
131 enable-method = "psci";
132 capacity-dmips-mhz = <1024>;
133 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
134 dynamic-power-coefficient = <211>;
135 #cooling-cells = <2>;
140 compatible = "arm,cortex-a73";
142 enable-method = "psci";
143 capacity-dmips-mhz = <1024>;
144 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
145 dynamic-power-coefficient = <211>;
146 #cooling-cells = <2>;
151 compatible = "arm,cortex-a73";
153 enable-method = "psci";
154 capacity-dmips-mhz = <1024>;
155 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
156 dynamic-power-coefficient = <211>;
157 #cooling-cells = <2>;
160 idle-states {
161 entry-method = "psci";
163 CPU_SLEEP: cpu-sleep {
164 compatible = "arm,idle-state";
165 local-timer-stop;
166 arm,psci-suspend-param = <0x00010001>;
167 entry-latency-us = <200>;
168 exit-latency-us = <200>;
169 min-residency-us = <800>;
172 CLUSTER_SLEEP0: cluster-sleep-0 {
173 compatible = "arm,idle-state";
174 local-timer-stop;
175 arm,psci-suspend-param = <0x01010001>;
176 entry-latency-us = <250>;
177 exit-latency-us = <400>;
178 min-residency-us = <1000>;
180 CLUSTER_SLEEP1: cluster-sleep-1 {
181 compatible = "arm,idle-state";
182 local-timer-stop;
183 arm,psci-suspend-param = <0x01010001>;
184 entry-latency-us = <250>;
185 exit-latency-us = <400>;
186 min-residency-us = <1300>;
191 pmu-a53 {
192 compatible = "arm,cortex-a53-pmu";
193 interrupt-parent = <&gic>;
197 pmu-a73 {
198 compatible = "arm,cortex-a73-pmu";
199 interrupt-parent = <&gic>;
204 compatible = "arm,psci-1.0";
209 compatible = "fixed-clock";
210 #clock-cells = <0>;
211 clock-frequency = <26000000>;
212 clock-output-names = "clk26m";
216 compatible = "arm,armv8-timer";
217 interrupt-parent = <&gic>;
225 #address-cells = <2>;
226 #size-cells = <2>;
227 compatible = "simple-bus";
231 compatible = "mediatek,mt8183-efuse",
234 #address-cells = <1>;
235 #size-cells = <1>;
239 gic: interrupt-controller@c000000 {
240 compatible = "arm,gic-v3";
241 #interrupt-cells = <4>;
242 interrupt-parent = <&gic>;
243 interrupt-controller;
251 ppi-partitions {
252 ppi_cluster0: interrupt-partition-0 {
255 ppi_cluster1: interrupt-partition-1 {
262 compatible = "mediatek,mt8183-mcucfg", "syscon";
264 #clock-cells = <1>;
267 sysirq: interrupt-controller@c530a80 {
268 compatible = "mediatek,mt8183-sysirq",
269 "mediatek,mt6577-sysirq";
270 interrupt-controller;
271 #interrupt-cells = <3>;
272 interrupt-parent = <&gic>;
277 compatible = "mediatek,mt8183-topckgen", "syscon";
279 #clock-cells = <1>;
283 compatible = "mediatek,mt8183-infracfg", "syscon";
285 #clock-cells = <1>;
286 #reset-cells = <1>;
290 compatible = "mediatek,mt8183-pericfg", "syscon";
292 #clock-cells = <1>;
296 compatible = "mediatek,mt8183-pinctrl";
307 reg-names = "iocfg0", "iocfg1", "iocfg2",
311 gpio-controller;
312 #gpio-cells = <2>;
313 gpio-ranges = <&pio 0 0 192>;
314 interrupt-controller;
316 #interrupt-cells = <2>;
320 compatible = "mediatek,mt8183-wdt";
322 #reset-cells = <1>;
326 compatible = "mediatek,mt8183-apmixedsys", "syscon";
328 #clock-cells = <1>;
332 compatible = "mediatek,mt8183-pwrap";
334 reg-names = "pwrap";
338 clock-names = "spi", "wrap";
342 compatible = "mediatek,mt8183-scp";
345 reg-names = "sram", "cfg";
348 clock-names = "main";
349 memory-region = <&scp_mem_reserved>;
354 compatible = "mediatek,mt8183-timer",
355 "mediatek,mt6765-timer";
359 clock-names = "clk13m";
363 compatible = "mediatek,mt8183-gce";
366 #mbox-cells = <3>;
368 clock-names = "gce";
372 compatible = "mediatek,mt8183-auxadc",
373 "mediatek,mt8173-auxadc";
376 clock-names = "main";
377 #io-channel-cells = <1>;
382 compatible = "mediatek,mt8183-uart",
383 "mediatek,mt6577-uart";
387 clock-names = "baud", "bus";
392 compatible = "mediatek,mt8183-uart",
393 "mediatek,mt6577-uart";
397 clock-names = "baud", "bus";
402 compatible = "mediatek,mt8183-uart",
403 "mediatek,mt6577-uart";
407 clock-names = "baud", "bus";
412 compatible = "mediatek,mt8183-i2c";
418 clock-names = "main", "dma";
419 clock-div = <1>;
420 #address-cells = <1>;
421 #size-cells = <0>;
426 compatible = "mediatek,mt8183-i2c";
432 clock-names = "main", "dma";
433 clock-div = <1>;
434 #address-cells = <1>;
435 #size-cells = <0>;
440 compatible = "mediatek,mt8183-i2c";
447 clock-names = "main", "dma","arb";
448 clock-div = <1>;
449 #address-cells = <1>;
450 #size-cells = <0>;
455 compatible = "mediatek,mt8183-i2c";
462 clock-names = "main", "dma", "arb";
463 clock-div = <1>;
464 #address-cells = <1>;
465 #size-cells = <0>;
470 compatible = "mediatek,mt8183-spi";
471 #address-cells = <1>;
472 #size-cells = <0>;
478 clock-names = "parent-clk", "sel-clk", "spi-clk";
483 compatible = "mediatek,mt8183-i2c";
489 clock-names = "main", "dma";
490 clock-div = <1>;
491 #address-cells = <1>;
492 #size-cells = <0>;
497 compatible = "mediatek,mt8183-spi";
498 #address-cells = <1>;
499 #size-cells = <0>;
505 clock-names = "parent-clk", "sel-clk", "spi-clk";
510 compatible = "mediatek,mt8183-i2c";
516 clock-names = "main", "dma";
517 clock-div = <1>;
518 #address-cells = <1>;
519 #size-cells = <0>;
524 compatible = "mediatek,mt8183-spi";
525 #address-cells = <1>;
526 #size-cells = <0>;
532 clock-names = "parent-clk", "sel-clk", "spi-clk";
537 compatible = "mediatek,mt8183-spi";
538 #address-cells = <1>;
539 #size-cells = <0>;
545 clock-names = "parent-clk", "sel-clk", "spi-clk";
550 compatible = "mediatek,mt8183-i2c";
557 clock-names = "main", "dma", "arb";
558 clock-div = <1>;
559 #address-cells = <1>;
560 #size-cells = <0>;
565 compatible = "mediatek,mt8183-i2c";
572 clock-names = "main", "dma", "arb";
573 clock-div = <1>;
574 #address-cells = <1>;
575 #size-cells = <0>;
580 compatible = "mediatek,mt8183-i2c";
587 clock-names = "main", "dma", "arb";
588 clock-div = <1>;
589 #address-cells = <1>;
590 #size-cells = <0>;
595 compatible = "mediatek,mt8183-i2c";
602 clock-names = "main", "dma", "arb";
603 clock-div = <1>;
604 #address-cells = <1>;
605 #size-cells = <0>;
610 compatible = "mediatek,mt8183-spi";
611 #address-cells = <1>;
612 #size-cells = <0>;
618 clock-names = "parent-clk", "sel-clk", "spi-clk";
623 compatible = "mediatek,mt8183-spi";
624 #address-cells = <1>;
625 #size-cells = <0>;
631 clock-names = "parent-clk", "sel-clk", "spi-clk";
636 compatible = "mediatek,mt8183-i2c";
642 clock-names = "main", "dma";
643 clock-div = <1>;
644 #address-cells = <1>;
645 #size-cells = <0>;
650 compatible = "mediatek,mt8183-i2c";
656 clock-names = "main", "dma";
657 clock-div = <1>;
658 #address-cells = <1>;
659 #size-cells = <0>;
664 compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3";
667 reg-names = "mac", "ippc";
673 clock-names = "sys_ck", "ref_ck";
674 mediatek,syscon-wakeup = <&pericfg 0x400 0>;
675 #address-cells = <2>;
676 #size-cells = <2>;
681 compatible = "mediatek,mt8183-xhci",
682 "mediatek,mtk-xhci";
684 reg-names = "mac";
688 clock-names = "sys_ck", "ref_ck";
694 compatible = "mediatek,mt8183-audiosys", "syscon";
696 #clock-cells = <1>;
700 compatible = "mediatek,mt8183-mmc";
707 clock-names = "source", "hclk", "source_cg";
712 compatible = "mediatek,mt8183-mmc";
719 clock-names = "source", "hclk", "source_cg";
724 compatible = "mediatek,mt8183-efuse",
729 u3phy: usb-phy@11f40000 {
730 compatible = "mediatek,mt8183-tphy",
731 "mediatek,generic-tphy-v2";
732 #address-cells = <1>;
733 #phy-cells = <1>;
734 #size-cells = <1>;
738 u2port0: usb-phy@0 {
741 clock-names = "ref";
742 #phy-cells = <1>;
747 u3port0: usb-phy@0700 {
750 clock-names = "ref";
751 #phy-cells = <1>;
757 compatible = "mediatek,mt8183-mfgcfg", "syscon";
759 #clock-cells = <1>;
763 compatible = "mediatek,mt8183-mmsys", "syscon";
765 #clock-cells = <1>;
769 compatible = "mediatek,mt8183-imgsys", "syscon";
771 #clock-cells = <1>;
775 compatible = "mediatek,mt8183-vdecsys", "syscon";
777 #clock-cells = <1>;
781 compatible = "mediatek,mt8183-vencsys", "syscon";
783 #clock-cells = <1>;
787 compatible = "mediatek,mt8183-ipu_conn", "syscon";
789 #clock-cells = <1>;
793 compatible = "mediatek,mt8183-ipu_adl", "syscon";
795 #clock-cells = <1>;
799 compatible = "mediatek,mt8183-ipu_core0", "syscon";
801 #clock-cells = <1>;
805 compatible = "mediatek,mt8183-ipu_core1", "syscon";
807 #clock-cells = <1>;
811 compatible = "mediatek,mt8183-camsys", "syscon";
813 #clock-cells = <1>;