Lines Matching +full:mipi +full:- +full:bias
14 #include <dt-bindings/clock/mt8173-clk.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/memory/mt8173-larb-port.h>
18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/power/mt8173-power.h>
20 #include <dt-bindings/reset/mt8173-resets.h>
21 #include <dt-bindings/gce/mt8173-gce.h>
22 #include <dt-bindings/thermal/thermal.h>
23 #include "mt8173-pinfunc.h"
27 interrupt-parent = <&sysirq>;
28 #address-cells = <2>;
29 #size-cells = <2>;
46 mdp-rdma0 = &mdp_rdma0;
47 mdp-rdma1 = &mdp_rdma1;
48 mdp-rsz0 = &mdp_rsz0;
49 mdp-rsz1 = &mdp_rsz1;
50 mdp-rsz2 = &mdp_rsz2;
51 mdp-wdma0 = &mdp_wdma0;
52 mdp-wrot0 = &mdp_wrot0;
53 mdp-wrot1 = &mdp_wrot1;
61 compatible = "operating-points-v2";
62 opp-shared;
63 opp-507000000 {
64 opp-hz = /bits/ 64 <507000000>;
65 opp-microvolt = <859000>;
67 opp-702000000 {
68 opp-hz = /bits/ 64 <702000000>;
69 opp-microvolt = <908000>;
71 opp-1001000000 {
72 opp-hz = /bits/ 64 <1001000000>;
73 opp-microvolt = <983000>;
75 opp-1105000000 {
76 opp-hz = /bits/ 64 <1105000000>;
77 opp-microvolt = <1009000>;
79 opp-1209000000 {
80 opp-hz = /bits/ 64 <1209000000>;
81 opp-microvolt = <1034000>;
83 opp-1300000000 {
84 opp-hz = /bits/ 64 <1300000000>;
85 opp-microvolt = <1057000>;
87 opp-1508000000 {
88 opp-hz = /bits/ 64 <1508000000>;
89 opp-microvolt = <1109000>;
91 opp-1703000000 {
92 opp-hz = /bits/ 64 <1703000000>;
93 opp-microvolt = <1125000>;
98 compatible = "operating-points-v2";
99 opp-shared;
100 opp-507000000 {
101 opp-hz = /bits/ 64 <507000000>;
102 opp-microvolt = <828000>;
104 opp-702000000 {
105 opp-hz = /bits/ 64 <702000000>;
106 opp-microvolt = <867000>;
108 opp-1001000000 {
109 opp-hz = /bits/ 64 <1001000000>;
110 opp-microvolt = <927000>;
112 opp-1209000000 {
113 opp-hz = /bits/ 64 <1209000000>;
114 opp-microvolt = <968000>;
116 opp-1404000000 {
117 opp-hz = /bits/ 64 <1404000000>;
118 opp-microvolt = <1007000>;
120 opp-1612000000 {
121 opp-hz = /bits/ 64 <1612000000>;
122 opp-microvolt = <1049000>;
124 opp-1807000000 {
125 opp-hz = /bits/ 64 <1807000000>;
126 opp-microvolt = <1089000>;
128 opp-2106000000 {
129 opp-hz = /bits/ 64 <2106000000>;
130 opp-microvolt = <1125000>;
135 #address-cells = <1>;
136 #size-cells = <0>;
138 cpu-map {
160 compatible = "arm,cortex-a53";
162 enable-method = "psci";
163 cpu-idle-states = <&CPU_SLEEP_0>;
164 #cooling-cells = <2>;
165 dynamic-power-coefficient = <263>;
168 clock-names = "cpu", "intermediate";
169 operating-points-v2 = <&cluster0_opp>;
170 capacity-dmips-mhz = <740>;
175 compatible = "arm,cortex-a53";
177 enable-method = "psci";
178 cpu-idle-states = <&CPU_SLEEP_0>;
179 #cooling-cells = <2>;
180 dynamic-power-coefficient = <263>;
183 clock-names = "cpu", "intermediate";
184 operating-points-v2 = <&cluster0_opp>;
185 capacity-dmips-mhz = <740>;
190 compatible = "arm,cortex-a72";
192 enable-method = "psci";
193 cpu-idle-states = <&CPU_SLEEP_0>;
194 #cooling-cells = <2>;
195 dynamic-power-coefficient = <530>;
198 clock-names = "cpu", "intermediate";
199 operating-points-v2 = <&cluster1_opp>;
200 capacity-dmips-mhz = <1024>;
205 compatible = "arm,cortex-a72";
207 enable-method = "psci";
208 cpu-idle-states = <&CPU_SLEEP_0>;
209 #cooling-cells = <2>;
210 dynamic-power-coefficient = <530>;
213 clock-names = "cpu", "intermediate";
214 operating-points-v2 = <&cluster1_opp>;
215 capacity-dmips-mhz = <1024>;
218 idle-states {
219 entry-method = "psci";
221 CPU_SLEEP_0: cpu-sleep-0 {
222 compatible = "arm,idle-state";
223 local-timer-stop;
224 entry-latency-us = <639>;
225 exit-latency-us = <680>;
226 min-residency-us = <1088>;
227 arm,psci-suspend-param = <0x0010000>;
233 compatible = "arm,cortex-a53-pmu";
236 interrupt-affinity = <&cpu0>, <&cpu1>;
240 compatible = "arm,cortex-a72-pmu";
243 interrupt-affinity = <&cpu2>, <&cpu3>;
247 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
255 compatible = "fixed-clock";
256 #clock-cells = <0>;
257 clock-frequency = <26000000>;
258 clock-output-names = "clk26m";
262 compatible = "fixed-clock";
263 #clock-cells = <0>;
264 clock-frequency = <32000>;
265 clock-output-names = "clk32k";
269 compatible = "fixed-clock";
270 #clock-cells = <0>;
271 clock-frequency = <0>;
272 clock-output-names = "cpum_ck";
275 thermal-zones {
277 polling-delay-passive = <1000>; /* milliseconds */
278 polling-delay = <1000>; /* milliseconds */
280 thermal-sensors = <&thermal>;
281 sustainable-power = <1500>; /* milliwatts */
284 threshold: trip-point0 {
290 target: trip-point1 {
303 cooling-maps {
306 cooling-device = <&cpu0 THERMAL_NO_LIMIT
314 cooling-device = <&cpu2 THERMAL_NO_LIMIT
324 reserved-memory {
325 #address-cells = <2>;
326 #size-cells = <2>;
329 compatible = "shared-dma-pool";
332 no-map;
337 compatible = "arm,armv8-timer";
338 interrupt-parent = <&gic>;
347 arm,no-tick-in-suspend;
351 #address-cells = <2>;
352 #size-cells = <2>;
353 compatible = "simple-bus";
356 topckgen: clock-controller@10000000 {
357 compatible = "mediatek,mt8173-topckgen";
359 #clock-cells = <1>;
362 infracfg: power-controller@10001000 {
363 compatible = "mediatek,mt8173-infracfg", "syscon";
365 #clock-cells = <1>;
366 #reset-cells = <1>;
369 pericfg: power-controller@10003000 {
370 compatible = "mediatek,mt8173-pericfg", "syscon";
372 #clock-cells = <1>;
373 #reset-cells = <1>;
377 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
382 compatible = "mediatek,mt8173-pinctrl";
384 mediatek,pctl-regmap = <&syscfg_pctl_a>;
385 pins-are-numbered;
386 gpio-controller;
387 #gpio-cells = <2>;
388 interrupt-controller;
389 #interrupt-cells = <2>;
399 input-enable;
400 bias-pull-down;
408 bias-disable;
416 bias-disable;
424 bias-disable;
432 bias-disable;
440 bias-disable;
448 bias-disable;
453 scpsys: power-controller@10006000 {
454 compatible = "mediatek,mt8173-scpsys";
455 #power-domain-cells = <1>;
461 clock-names = "mfg", "mm", "venc", "venc_lt";
466 compatible = "mediatek,mt8173-wdt",
467 "mediatek,mt6589-wdt";
472 compatible = "mediatek,mt8173-timer",
473 "mediatek,mt6577-timer";
481 compatible = "mediatek,mt8173-pwrap";
483 reg-names = "pwrap";
486 reset-names = "pwrap";
488 clock-names = "spi", "wrap";
492 compatible = "mediatek,mt8173-cec";
500 compatible = "mediatek,mt8173-vpu";
503 reg-names = "tcm", "cfg_reg";
506 clock-names = "main";
507 memory-region = <&vpu_dma_reserved>;
510 sysirq: intpol-controller@10200620 {
511 compatible = "mediatek,mt8173-sysirq",
512 "mediatek,mt6577-sysirq";
513 interrupt-controller;
514 #interrupt-cells = <3>;
515 interrupt-parent = <&gic>;
520 compatible = "mediatek,mt8173-m4u";
524 clock-names = "bclk";
527 #iommu-cells = <1>;
531 compatible = "mediatek,mt8173-efuse";
533 #address-cells = <1>;
534 #size-cells = <1>;
540 apmixedsys: clock-controller@10209000 {
541 compatible = "mediatek,mt8173-apmixedsys";
543 #clock-cells = <1>;
546 hdmi_phy: hdmi-phy@10209100 {
547 compatible = "mediatek,mt8173-hdmi-phy";
550 clock-names = "pll_ref";
551 clock-output-names = "hdmitx_dig_cts";
554 #clock-cells = <0>;
555 #phy-cells = <0>;
560 compatible = "mediatek,mt8173-gce";
564 clock-names = "gce";
565 #mbox-cells = <2>;
568 mipi_tx0: mipi-dphy@10215000 {
569 compatible = "mediatek,mt8173-mipi-tx";
572 clock-output-names = "mipi_tx0_pll";
573 #clock-cells = <0>;
574 #phy-cells = <0>;
578 mipi_tx1: mipi-dphy@10216000 {
579 compatible = "mediatek,mt8173-mipi-tx";
582 clock-output-names = "mipi_tx1_pll";
583 #clock-cells = <0>;
584 #phy-cells = <0>;
588 gic: interrupt-controller@10221000 {
589 compatible = "arm,gic-400";
590 #interrupt-cells = <3>;
591 interrupt-parent = <&gic>;
592 interrupt-controller;
602 compatible = "mediatek,mt8173-auxadc";
605 clock-names = "main";
606 #io-channel-cells = <1>;
610 compatible = "mediatek,mt8173-uart",
611 "mediatek,mt6577-uart";
615 clock-names = "baud", "bus";
620 compatible = "mediatek,mt8173-uart",
621 "mediatek,mt6577-uart";
625 clock-names = "baud", "bus";
630 compatible = "mediatek,mt8173-uart",
631 "mediatek,mt6577-uart";
635 clock-names = "baud", "bus";
640 compatible = "mediatek,mt8173-uart",
641 "mediatek,mt6577-uart";
645 clock-names = "baud", "bus";
650 compatible = "mediatek,mt8173-i2c";
654 clock-div = <16>;
657 clock-names = "main", "dma";
658 pinctrl-names = "default";
659 pinctrl-0 = <&i2c0_pins_a>;
660 #address-cells = <1>;
661 #size-cells = <0>;
666 compatible = "mediatek,mt8173-i2c";
670 clock-div = <16>;
673 clock-names = "main", "dma";
674 pinctrl-names = "default";
675 pinctrl-0 = <&i2c1_pins_a>;
676 #address-cells = <1>;
677 #size-cells = <0>;
682 compatible = "mediatek,mt8173-i2c";
686 clock-div = <16>;
689 clock-names = "main", "dma";
690 pinctrl-names = "default";
691 pinctrl-0 = <&i2c2_pins_a>;
692 #address-cells = <1>;
693 #size-cells = <0>;
698 compatible = "mediatek,mt8173-spi";
699 #address-cells = <1>;
700 #size-cells = <0>;
706 clock-names = "parent-clk", "sel-clk", "spi-clk";
711 #thermal-sensor-cells = <0>;
712 compatible = "mediatek,mt8173-thermal";
716 clock-names = "therm", "auxadc";
720 nvmem-cells = <&thermal_calibration>;
721 nvmem-cell-names = "calibration-data";
725 compatible = "mediatek,mt8173-nor";
729 clock-names = "spi", "sf";
730 #address-cells = <1>;
731 #size-cells = <0>;
736 compatible = "mediatek,mt8173-i2c";
740 clock-div = <16>;
743 clock-names = "main", "dma";
744 pinctrl-names = "default";
745 pinctrl-0 = <&i2c3_pins_a>;
746 #address-cells = <1>;
747 #size-cells = <0>;
752 compatible = "mediatek,mt8173-i2c";
756 clock-div = <16>;
759 clock-names = "main", "dma";
760 pinctrl-names = "default";
761 pinctrl-0 = <&i2c4_pins_a>;
762 #address-cells = <1>;
763 #size-cells = <0>;
768 compatible = "mediatek,mt8173-hdmi-ddc";
772 clock-names = "ddc-i2c";
776 compatible = "mediatek,mt8173-i2c";
780 clock-div = <16>;
783 clock-names = "main", "dma";
784 pinctrl-names = "default";
785 pinctrl-0 = <&i2c6_pins_a>;
786 #address-cells = <1>;
787 #size-cells = <0>;
791 afe: audio-controller@11220000 {
792 compatible = "mediatek,mt8173-afe-pcm";
795 power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
806 clock-names = "infra_sys_audio_clk",
816 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
818 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
823 compatible = "mediatek,mt8173-mmc";
828 clock-names = "source", "hclk";
833 compatible = "mediatek,mt8173-mmc";
838 clock-names = "source", "hclk";
843 compatible = "mediatek,mt8173-mmc";
848 clock-names = "source", "hclk";
853 compatible = "mediatek,mt8173-mmc";
858 clock-names = "source", "hclk";
863 compatible = "mediatek,mt8173-mtu3";
866 reg-names = "mac", "ippc";
871 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
873 clock-names = "sys_ck", "ref_ck";
874 mediatek,syscon-wakeup = <&pericfg 0x400 1>;
875 #address-cells = <2>;
876 #size-cells = <2>;
881 compatible = "mediatek,mt8173-xhci";
883 reg-names = "mac";
885 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
887 clock-names = "sys_ck", "ref_ck";
892 u3phy: usb-phy@11290000 {
893 compatible = "mediatek,mt8173-u3phy";
895 #address-cells = <2>;
896 #size-cells = <2>;
900 u2port0: usb-phy@11290800 {
903 clock-names = "ref";
904 #phy-cells = <1>;
908 u3port0: usb-phy@11290900 {
911 clock-names = "ref";
912 #phy-cells = <1>;
916 u2port1: usb-phy@11291000 {
919 clock-names = "ref";
920 #phy-cells = <1>;
926 compatible = "mediatek,mt8173-mmsys", "syscon";
928 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
929 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
930 assigned-clock-rates = <400000000>;
931 #clock-cells = <1>;
934 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
938 compatible = "mediatek,mt8173-mdp-rdma",
939 "mediatek,mt8173-mdp";
943 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
950 compatible = "mediatek,mt8173-mdp-rdma";
954 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
960 compatible = "mediatek,mt8173-mdp-rsz";
963 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
967 compatible = "mediatek,mt8173-mdp-rsz";
970 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
974 compatible = "mediatek,mt8173-mdp-rsz";
977 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
981 compatible = "mediatek,mt8173-mdp-wdma";
984 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
990 compatible = "mediatek,mt8173-mdp-wrot";
993 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
999 compatible = "mediatek,mt8173-mdp-wrot";
1002 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1008 compatible = "mediatek,mt8173-disp-ovl";
1011 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1015 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1019 compatible = "mediatek,mt8173-disp-ovl";
1022 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1026 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1030 compatible = "mediatek,mt8173-disp-rdma";
1033 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1037 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1041 compatible = "mediatek,mt8173-disp-rdma";
1044 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1048 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1052 compatible = "mediatek,mt8173-disp-rdma";
1055 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1059 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
1063 compatible = "mediatek,mt8173-disp-wdma";
1066 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1070 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1074 compatible = "mediatek,mt8173-disp-wdma";
1077 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1081 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
1085 compatible = "mediatek,mt8173-disp-color";
1088 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1090 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
1094 compatible = "mediatek,mt8173-disp-color";
1097 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1099 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
1103 compatible = "mediatek,mt8173-disp-aal";
1106 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1108 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
1112 compatible = "mediatek,mt8173-disp-gamma";
1115 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1117 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
1121 compatible = "mediatek,mt8173-disp-merge";
1123 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1128 compatible = "mediatek,mt8173-disp-split";
1130 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1135 compatible = "mediatek,mt8173-disp-split";
1137 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1142 compatible = "mediatek,mt8173-disp-ufoe";
1145 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1150 compatible = "mediatek,mt8173-dsi";
1153 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1157 clock-names = "engine", "digital", "hs";
1159 phy-names = "dphy";
1164 compatible = "mediatek,mt8173-dsi";
1167 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1171 clock-names = "engine", "digital", "hs";
1173 phy-names = "dphy";
1178 compatible = "mediatek,mt8173-dpi";
1181 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1185 clock-names = "pixel", "engine", "pll";
1190 remote-endpoint = <&hdmi0_in>;
1196 compatible = "mediatek,mt8173-disp-pwm",
1197 "mediatek,mt6595-disp-pwm";
1199 #pwm-cells = <2>;
1202 clock-names = "main", "mm";
1207 compatible = "mediatek,mt8173-disp-pwm",
1208 "mediatek,mt6595-disp-pwm";
1210 #pwm-cells = <2>;
1213 clock-names = "main", "mm";
1218 compatible = "mediatek,mt8173-disp-mutex";
1221 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1223 mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
1228 compatible = "mediatek,mt8173-smi-larb";
1231 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1234 clock-names = "apb", "smi";
1238 compatible = "mediatek,mt8173-smi-common";
1240 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1243 clock-names = "apb", "smi";
1247 compatible = "mediatek,mt8173-disp-od";
1253 compatible = "mediatek,mt8173-hdmi";
1260 clock-names = "pixel", "pll", "bclk", "spdif";
1261 pinctrl-names = "default";
1262 pinctrl-0 = <&hdmi_pin>;
1264 phy-names = "hdmi";
1265 mediatek,syscon-hdmi = <&mmsys 0x900>;
1266 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
1267 assigned-clock-parents = <&hdmi_phy>;
1271 #address-cells = <1>;
1272 #size-cells = <0>;
1278 remote-endpoint = <&dpi0_out>;
1285 compatible = "mediatek,mt8173-smi-larb";
1288 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1291 clock-names = "apb", "smi";
1294 imgsys: clock-controller@15000000 {
1295 compatible = "mediatek,mt8173-imgsys", "syscon";
1297 #clock-cells = <1>;
1301 compatible = "mediatek,mt8173-smi-larb";
1304 power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>;
1307 clock-names = "apb", "smi";
1310 vdecsys: clock-controller@16000000 {
1311 compatible = "mediatek,mt8173-vdecsys", "syscon";
1313 #clock-cells = <1>;
1317 compatible = "mediatek,mt8173-vcodec-dec";
1341 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
1350 clock-names = "vcodecpll",
1358 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
1363 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
1366 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
1370 compatible = "mediatek,mt8173-smi-larb";
1373 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
1376 clock-names = "apb", "smi";
1379 vencsys: clock-controller@18000000 {
1380 compatible = "mediatek,mt8173-vencsys", "syscon";
1382 #clock-cells = <1>;
1386 compatible = "mediatek,mt8173-smi-larb";
1389 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
1392 clock-names = "apb", "smi";
1396 compatible = "mediatek,mt8173-vcodec-enc";
1428 clock-names = "venc_sel_src",
1432 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
1434 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>,
1439 compatible = "mediatek,mt8173-jpgdec";
1444 clock-names = "jpgdec-smi",
1446 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
1452 vencltsys: clock-controller@19000000 {
1453 compatible = "mediatek,mt8173-vencltsys", "syscon";
1455 #clock-cells = <1>;
1459 compatible = "mediatek,mt8173-smi-larb";
1462 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;
1465 clock-names = "apb", "smi";