Lines Matching +full:syscon +full:- +full:efuse
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt7622-clk.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt7622-power.h>
14 #include <dt-bindings/reset/mt7622-reset.h>
15 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
21 #size-cells = <2>;
23 cpu_opp_table: opp-table {
24 compatible = "operating-points-v2";
25 opp-shared;
26 opp-300000000 {
27 opp-hz = /bits/ 64 <30000000>;
28 opp-microvolt = <950000>;
31 opp-437500000 {
32 opp-hz = /bits/ 64 <437500000>;
33 opp-microvolt = <1000000>;
36 opp-600000000 {
37 opp-hz = /bits/ 64 <600000000>;
38 opp-microvolt = <1050000>;
41 opp-812500000 {
42 opp-hz = /bits/ 64 <812500000>;
43 opp-microvolt = <1100000>;
46 opp-1025000000 {
47 opp-hz = /bits/ 64 <1025000000>;
48 opp-microvolt = <1150000>;
51 opp-1137500000 {
52 opp-hz = /bits/ 64 <1137500000>;
53 opp-microvolt = <1200000>;
56 opp-1262500000 {
57 opp-hz = /bits/ 64 <1262500000>;
58 opp-microvolt = <1250000>;
61 opp-1350000000 {
62 opp-hz = /bits/ 64 <1350000000>;
63 opp-microvolt = <1310000>;
68 #address-cells = <2>;
69 #size-cells = <0>;
73 compatible = "arm,cortex-a53";
77 clock-names = "cpu", "intermediate";
78 operating-points-v2 = <&cpu_opp_table>;
79 #cooling-cells = <2>;
80 enable-method = "psci";
81 clock-frequency = <1300000000>;
82 cci-control-port = <&cci_control2>;
87 compatible = "arm,cortex-a53";
91 clock-names = "cpu", "intermediate";
92 operating-points-v2 = <&cpu_opp_table>;
93 #cooling-cells = <2>;
94 enable-method = "psci";
95 clock-frequency = <1300000000>;
96 cci-control-port = <&cci_control2>;
101 compatible = "fixed-clock";
102 clock-frequency = <40000000>;
103 #clock-cells = <0>;
107 compatible = "fixed-clock";
108 #clock-cells = <0>;
109 clock-frequency = <25000000>;
110 clock-output-names = "clkxtal";
114 compatible = "arm,psci-0.2";
119 compatible = "arm,cortex-a53-pmu";
122 interrupt-affinity = <&cpu0>, <&cpu1>;
125 reserved-memory {
126 #address-cells = <2>;
127 #size-cells = <2>;
133 no-map;
137 thermal-zones {
138 cpu_thermal: cpu-thermal {
139 polling-delay-passive = <1000>;
140 polling-delay = <1000>;
142 thermal-sensors = <&thermal 0>;
145 cpu_passive: cpu-passive {
151 cpu_active: cpu-active {
157 cpu_hot: cpu-hot {
163 cpu-crit {
170 cooling-maps {
173 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
179 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
185 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
193 compatible = "arm,armv8-timer";
194 interrupt-parent = <&gic>;
206 compatible = "mediatek,mt7622-infracfg",
207 "syscon";
209 #clock-cells = <1>;
210 #reset-cells = <1>;
214 compatible = "mediatek,mt7622-pwrap";
216 reg-names = "pwrap";
218 clock-names = "spi", "wrap";
220 reset-names = "pwrap";
226 compatible = "mediatek,mt7622-pericfg",
227 "syscon";
229 #clock-cells = <1>;
230 #reset-cells = <1>;
233 scpsys: power-controller@10006000 {
234 compatible = "mediatek,mt7622-scpsys",
235 "syscon";
236 #power-domain-cells = <1>;
244 clock-names = "hif_sel";
248 compatible = "mediatek,mt7622-cir";
253 clock-names = "clk", "bus";
257 sysirq: interrupt-controller@10200620 {
258 compatible = "mediatek,mt7622-sysirq",
259 "mediatek,mt6577-sysirq";
260 interrupt-controller;
261 #interrupt-cells = <3>;
262 interrupt-parent = <&gic>;
266 efuse: efuse@10206000 { label
267 compatible = "mediatek,mt7622-efuse",
268 "mediatek,efuse";
270 #address-cells = <1>;
271 #size-cells = <1>;
279 compatible = "mediatek,mt7622-apmixedsys",
280 "syscon";
282 #clock-cells = <1>;
286 compatible = "mediatek,mt7622-topckgen",
287 "syscon";
289 #clock-cells = <1>;
293 compatible = "mediatek,mt7622-rng",
294 "mediatek,mt7623-rng";
297 clock-names = "rng";
301 compatible = "mediatek,mt7622-pinctrl";
304 reg-names = "base", "eint";
305 gpio-controller;
306 #gpio-cells = <2>;
307 gpio-ranges = <&pio 0 0 103>;
308 interrupt-controller;
310 interrupt-parent = <&gic>;
311 #interrupt-cells = <2>;
315 compatible = "mediatek,mt7622-wdt",
316 "mediatek,mt6589-wdt";
321 compatible = "mediatek,mt7622-rtc",
322 "mediatek,soc-rtc";
326 clock-names = "rtc";
329 gic: interrupt-controller@10300000 {
330 compatible = "arm,gic-400";
331 interrupt-controller;
332 #interrupt-cells = <3>;
333 interrupt-parent = <&gic>;
341 compatible = "arm,cci-400";
342 #address-cells = <1>;
343 #size-cells = <1>;
347 cci_control0: slave-if@1000 {
348 compatible = "arm,cci-400-ctrl-if";
349 interface-type = "ace-lite";
353 cci_control1: slave-if@4000 {
354 compatible = "arm,cci-400-ctrl-if";
355 interface-type = "ace";
359 cci_control2: slave-if@5000 {
360 compatible = "arm,cci-400-ctrl-if";
361 interface-type = "ace";
366 compatible = "arm,cci-400-pmu,r1";
377 compatible = "mediatek,mt7622-auxadc";
380 clock-names = "main";
381 #io-channel-cells = <1>;
385 compatible = "mediatek,mt7622-uart",
386 "mediatek,mt6577-uart";
391 clock-names = "baud", "bus";
396 compatible = "mediatek,mt7622-uart",
397 "mediatek,mt6577-uart";
402 clock-names = "baud", "bus";
407 compatible = "mediatek,mt7622-uart",
408 "mediatek,mt6577-uart";
413 clock-names = "baud", "bus";
418 compatible = "mediatek,mt7622-uart",
419 "mediatek,mt6577-uart";
424 clock-names = "baud", "bus";
429 compatible = "mediatek,mt7622-pwm";
440 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
446 compatible = "mediatek,mt7622-i2c";
450 clock-div = <16>;
453 clock-names = "main", "dma";
454 #address-cells = <1>;
455 #size-cells = <0>;
460 compatible = "mediatek,mt7622-i2c";
464 clock-div = <16>;
467 clock-names = "main", "dma";
468 #address-cells = <1>;
469 #size-cells = <0>;
474 compatible = "mediatek,mt7622-i2c";
478 clock-div = <16>;
481 clock-names = "main", "dma";
482 #address-cells = <1>;
483 #size-cells = <0>;
488 compatible = "mediatek,mt7622-spi";
494 clock-names = "parent-clk", "sel-clk", "spi-clk";
495 #address-cells = <1>;
496 #size-cells = <0>;
501 #thermal-sensor-cells = <1>;
502 compatible = "mediatek,mt7622-thermal";
507 clock-names = "therm", "auxadc";
509 reset-names = "therm";
512 nvmem-cells = <&thermal_calibration>;
513 nvmem-cell-names = "calibration-data";
517 compatible = "mediatek,mt7622-btif",
518 "mediatek,mtk-btif";
522 clock-names = "main";
523 reg-shift = <2>;
524 reg-io-width = <4>;
528 compatible = "mediatek,mt7622-bluetooth";
529 power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
531 clock-names = "ref";
536 compatible = "mediatek,mt7622-nfc";
541 clock-names = "nfi_clk", "pad_clk";
542 ecc-engine = <&bch>;
543 #address-cells = <1>;
544 #size-cells = <0>;
549 compatible = "mediatek,mt7622-ecc";
553 clock-names = "nfiecc_clk";
558 compatible = "mediatek,mt7622-nor",
559 "mediatek,mt8173-nor";
563 clock-names = "spi", "sf";
564 #address-cells = <1>;
565 #size-cells = <0>;
570 compatible = "mediatek,mt7622-spi";
576 clock-names = "parent-clk", "sel-clk", "spi-clk";
577 #address-cells = <1>;
578 #size-cells = <0>;
583 compatible = "mediatek,mt7622-uart",
584 "mediatek,mt6577-uart";
589 clock-names = "baud", "bus";
593 audsys: clock-controller@11220000 {
594 compatible = "mediatek,mt7622-audsys", "syscon";
596 #clock-cells = <1>;
598 afe: audio-controller {
599 compatible = "mediatek,mt7622-audio";
602 interrupt-names = "afe", "asys";
638 clock-names = "infra_sys_audio_clk",
672 assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,
676 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>,
678 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
683 compatible = "mediatek,mt7622-mmc";
688 clock-names = "source", "hclk";
690 reset-names = "hrst";
695 compatible = "mediatek,mt7622-mmc";
700 clock-names = "source", "hclk";
705 compatible = "mediatek,mt7622-wmac";
712 power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
716 compatible = "mediatek,mt7622-ssusbsys",
717 "syscon";
719 #clock-cells = <1>;
720 #reset-cells = <1>;
724 compatible = "mediatek,mt7622-xhci",
725 "mediatek,mtk-xhci";
728 reg-names = "mac", "ippc";
730 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
735 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
743 u3phy: usb-phy@1a0c4000 {
744 compatible = "mediatek,mt7622-u3phy",
745 "mediatek,generic-tphy-v1";
747 #address-cells = <2>;
748 #size-cells = <2>;
752 u2port0: usb-phy@1a0c4800 {
754 #phy-cells = <1>;
756 clock-names = "ref";
759 u3port0: usb-phy@1a0c4900 {
761 #phy-cells = <1>;
763 clock-names = "ref";
766 u2port1: usb-phy@1a0c5000 {
768 #phy-cells = <1>;
770 clock-names = "ref";
775 compatible = "mediatek,mt7622-pciesys",
776 "syscon";
778 #clock-cells = <1>;
779 #reset-cells = <1>;
783 compatible = "mediatek,mt7622-pcie";
788 reg-names = "subsys", "port0", "port1";
789 #address-cells = <3>;
790 #size-cells = <2>;
805 clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
808 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
809 bus-range = <0x00 0xff>;
815 #address-cells = <3>;
816 #size-cells = <2>;
817 #interrupt-cells = <1>;
821 interrupt-map-mask = <0 0 0 7>;
822 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
826 pcie_intc0: interrupt-controller {
827 interrupt-controller;
828 #address-cells = <0>;
829 #interrupt-cells = <1>;
835 #address-cells = <3>;
836 #size-cells = <2>;
837 #interrupt-cells = <1>;
841 interrupt-map-mask = <0 0 0 7>;
842 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
846 pcie_intc1: interrupt-controller {
847 interrupt-controller;
848 #address-cells = <0>;
849 #interrupt-cells = <1>;
855 compatible = "mediatek,mt7622-ahci",
856 "mediatek,mtk-ahci";
859 interrupt-names = "hostc";
865 clock-names = "ahb", "axi", "asic", "rbc", "pm";
867 phy-names = "sata-phy";
868 ports-implemented = <0x1>;
869 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
873 reset-names = "axi", "sw", "reg";
874 mediatek,phy-mode = <&pciesys>;
878 sata_phy: sata-phy@1a243000 {
879 compatible = "mediatek,generic-tphy-v1";
880 #address-cells = <2>;
881 #size-cells = <2>;
885 sata_port: sata-phy@1a243000 {
888 clock-names = "ref";
889 #phy-cells = <1>;
893 ethsys: syscon@1b000000 {
894 compatible = "mediatek,mt7622-ethsys",
895 "syscon";
897 #clock-cells = <1>;
898 #reset-cells = <1>;
901 hsdma: dma-controller@1b007000 {
902 compatible = "mediatek,mt7622-hsdma";
906 clock-names = "hsdma";
907 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
908 #dma-cells = <1>;
912 compatible = "mediatek,mt7622-eth",
913 "mediatek,mt2701-eth",
914 "syscon";
930 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
934 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
937 #address-cells = <1>;
938 #size-cells = <0>;
943 compatible = "mediatek,mt7622-sgmiisys",
944 "syscon";
946 #clock-cells = <1>;