Lines Matching full:pericfg
225 pericfg: pericfg@10002000 { label
226 compatible = "mediatek,mt7622-pericfg",
379 clocks = <&pericfg CLK_PERI_AUXADC_PD>;
390 <&pericfg CLK_PERI_UART0_PD>;
401 <&pericfg CLK_PERI_UART1_PD>;
412 <&pericfg CLK_PERI_UART2_PD>;
423 <&pericfg CLK_PERI_UART3_PD>;
433 <&pericfg CLK_PERI_PWM_PD>,
434 <&pericfg CLK_PERI_PWM1_PD>,
435 <&pericfg CLK_PERI_PWM2_PD>,
436 <&pericfg CLK_PERI_PWM3_PD>,
437 <&pericfg CLK_PERI_PWM4_PD>,
438 <&pericfg CLK_PERI_PWM5_PD>,
439 <&pericfg CLK_PERI_PWM6_PD>;
451 clocks = <&pericfg CLK_PERI_I2C0_PD>,
452 <&pericfg CLK_PERI_AP_DMA_PD>;
465 clocks = <&pericfg CLK_PERI_I2C1_PD>,
466 <&pericfg CLK_PERI_AP_DMA_PD>;
479 clocks = <&pericfg CLK_PERI_I2C2_PD>,
480 <&pericfg CLK_PERI_AP_DMA_PD>;
493 <&pericfg CLK_PERI_SPI0_PD>;
505 clocks = <&pericfg CLK_PERI_THERM_PD>,
506 <&pericfg CLK_PERI_AUXADC_PD>;
508 resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
521 clocks = <&pericfg CLK_PERI_BTIF_PD>;
539 clocks = <&pericfg CLK_PERI_NFI_PD>,
540 <&pericfg CLK_PERI_SNFI_PD>;
552 clocks = <&pericfg CLK_PERI_NFIECC_PD>;
561 clocks = <&pericfg CLK_PERI_FLASH_PD>,
575 <&pericfg CLK_PERI_SPI1_PD>;
588 <&pericfg CLK_PERI_UART4_PD>;
686 clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
689 resets = <&pericfg MT7622_PERI_MSDC0_SW_RST>;
698 clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,