Lines Matching +full:serial +full:- +full:pins
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
18 compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
25 stdout-path = "serial0:115200n8";
31 proc-supply = <&mt6380_vcpu_reg>;
32 sram-supply = <&mt6380_vm_reg>;
36 proc-supply = <&mt6380_vcpu_reg>;
37 sram-supply = <&mt6380_vm_reg>;
41 gpio-keys {
42 compatible = "gpio-keys";
43 poll-interval = <100>;
62 reg_1p8v: regulator-1p8v {
63 compatible = "regulator-fixed";
64 regulator-name = "fixed-1.8V";
65 regulator-min-microvolt = <1800000>;
66 regulator-max-microvolt = <1800000>;
67 regulator-always-on;
70 reg_3p3v: regulator-3p3v {
71 compatible = "regulator-fixed";
72 regulator-name = "fixed-3.3V";
73 regulator-min-microvolt = <3300000>;
74 regulator-max-microvolt = <3300000>;
75 regulator-boot-on;
76 regulator-always-on;
79 reg_5v: regulator-5v {
80 compatible = "regulator-fixed";
81 regulator-name = "fixed-5V";
82 regulator-min-microvolt = <5000000>;
83 regulator-max-microvolt = <5000000>;
84 regulator-boot-on;
85 regulator-always-on;
98 pinctrl-names = "default";
99 pinctrl-0 = <&irrx_pins>;
104 pinctrl-names = "default";
105 pinctrl-0 = <ð_pins>;
109 compatible = "mediatek,eth-mac";
111 phy-mode = "2500base-x";
113 fixed-link {
115 full-duplex;
120 mdio-bus {
121 #address-cells = <1>;
122 #size-cells = <0>;
127 reset-gpios = <&pio 54 0>;
130 #address-cells = <1>;
131 #size-cells = <0>;
162 phy-mode = "2500base-x";
164 fixed-link {
166 full-duplex;
177 pinctrl-names = "default";
178 pinctrl-0 = <&i2c1_pins>;
183 pinctrl-names = "default";
184 pinctrl-0 = <&i2c2_pins>;
189 pinctrl-names = "default", "state_uhs";
190 pinctrl-0 = <&emmc_pins_default>;
191 pinctrl-1 = <&emmc_pins_uhs>;
193 bus-width = <8>;
194 max-frequency = <50000000>;
195 cap-mmc-highspeed;
196 mmc-hs200-1_8v;
197 vmmc-supply = <®_3p3v>;
198 vqmmc-supply = <®_1p8v>;
199 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
200 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
201 non-removable;
205 pinctrl-names = "default", "state_uhs";
206 pinctrl-0 = <&sd0_pins_default>;
207 pinctrl-1 = <&sd0_pins_uhs>;
209 bus-width = <4>;
210 max-frequency = <50000000>;
211 cap-sd-highspeed;
213 cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
214 vmmc-supply = <®_3p3v>;
215 vqmmc-supply = <®_3p3v>;
216 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
217 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
221 pinctrl-names = "default";
222 pinctrl-0 = <¶llel_nand_pins>;
227 pinctrl-names = "default";
228 pinctrl-0 = <&spi_nor_pins>;
232 compatible = "jedec,spi-nor";
238 pinctrl-names = "default";
239 pinctrl-0 = <&pcie0_pins>;
249 emmc_pins_default: emmc-pins-default {
256 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
259 conf-cmd-dat {
260 pins = "NDL0", "NDL1", "NDL2",
263 input-enable;
264 bias-pull-up;
267 conf-clk {
268 pins = "NCLE";
269 bias-pull-down;
273 emmc_pins_uhs: emmc-pins-uhs {
279 conf-cmd-dat {
280 pins = "NDL0", "NDL1", "NDL2",
283 input-enable;
284 drive-strength = <4>;
285 bias-pull-up;
288 conf-clk {
289 pins = "NCLE";
290 drive-strength = <4>;
291 bias-pull-down;
295 eth_pins: eth-pins {
302 i2c1_pins: i2c1-pins {
309 i2c2_pins: i2c2-pins {
316 i2s1_pins: i2s1-pins {
325 pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
327 drive-strength = <12>;
328 bias-pull-down;
332 irrx_pins: irrx-pins {
339 irtx_pins: irtx-pins {
347 parallel_nand_pins: parallel-nand-pins {
354 pcie0_pins: pcie0-pins {
363 pcie1_pins: pcie1-pins {
372 pmic_bus_pins: pmic-bus-pins {
379 pwm7_pins: pwm1-2-pins {
386 wled_pins: wled-pins {
393 sd0_pins_default: sd0-pins-default {
403 conf-cmd-data {
404 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
406 input-enable;
407 drive-strength = <8>;
408 bias-pull-up;
410 conf-clk {
411 pins = "I2S3_OUT";
412 drive-strength = <12>;
413 bias-pull-down;
415 conf-cd {
416 pins = "TXD3";
417 bias-pull-up;
421 sd0_pins_uhs: sd0-pins-uhs {
427 conf-cmd-data {
428 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
430 input-enable;
431 bias-pull-up;
434 conf-clk {
435 pins = "I2S3_OUT";
436 bias-pull-down;
440 /* Serial NAND is shared pin with SPI-NOR */
441 serial_nand_pins: serial-nand-pins {
448 spic0_pins: spic0-pins {
455 spic1_pins: spic1-pins {
462 /* SPI-NOR is shared pin with serial NAND */
463 spi_nor_pins: spi-nor-pins {
470 /* serial NAND is shared pin with SPI-NOR */
471 serial_nand_pins: serial-nand-pins {
478 uart0_pins: uart0-pins {
485 uart2_pins: uart2-pins {
492 watchdog_pins: watchdog-pins {
501 pinctrl-names = "default";
502 pinctrl-0 = <&pwm7_pins>;
507 pinctrl-names = "default";
508 pinctrl-0 = <&pmic_bus_pins>;
522 pinctrl-names = "default";
523 pinctrl-0 = <&spic0_pins>;
528 pinctrl-names = "default";
529 pinctrl-0 = <&spic1_pins>;
534 vusb33-supply = <®_3p3v>;
535 vbus-supply = <®_5v>;
544 pinctrl-names = "default";
545 pinctrl-0 = <&uart0_pins>;
550 pinctrl-names = "default";
551 pinctrl-0 = <&uart2_pins>;
556 pinctrl-names = "default";
557 pinctrl-0 = <&watchdog_pins>;