Lines Matching +full:mtl +full:- +full:rx +full:- +full:config
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt2712-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/memory/mt2712-larb-port.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt2712-power.h>
14 #include "mt2712-pinfunc.h"
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
20 #size-cells = <2>;
23 compatible = "operating-points-v2";
24 opp-shared;
26 opp-hz = /bits/ 64 <598000000>;
27 opp-microvolt = <1000000>;
30 opp-hz = /bits/ 64 <702000000>;
31 opp-microvolt = <1000000>;
34 opp-hz = /bits/ 64 <793000000>;
35 opp-microvolt = <1000000>;
40 compatible = "operating-points-v2";
41 opp-shared;
43 opp-hz = /bits/ 64 <598000000>;
44 opp-microvolt = <1000000>;
47 opp-hz = /bits/ 64 <702000000>;
48 opp-microvolt = <1000000>;
51 opp-hz = /bits/ 64 <793000000>;
52 opp-microvolt = <1000000>;
55 opp-hz = /bits/ 64 <897000000>;
56 opp-microvolt = <1000000>;
59 opp-hz = /bits/ 64 <1001000000>;
60 opp-microvolt = <1000000>;
65 #address-cells = <1>;
66 #size-cells = <0>;
68 cpu-map {
87 compatible = "arm,cortex-a35";
91 clock-names = "cpu", "intermediate";
92 proc-supply = <&cpus_fixed_vproc0>;
93 operating-points-v2 = <&cluster0_opp>;
94 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
99 compatible = "arm,cortex-a35";
101 enable-method = "psci";
104 clock-names = "cpu", "intermediate";
105 proc-supply = <&cpus_fixed_vproc0>;
106 operating-points-v2 = <&cluster0_opp>;
107 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
112 compatible = "arm,cortex-a72";
114 enable-method = "psci";
117 clock-names = "cpu", "intermediate";
118 proc-supply = <&cpus_fixed_vproc1>;
119 operating-points-v2 = <&cluster1_opp>;
120 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
123 idle-states {
124 entry-method = "psci";
126 CPU_SLEEP_0: cpu-sleep-0 {
127 compatible = "arm,idle-state";
128 local-timer-stop;
129 entry-latency-us = <100>;
130 exit-latency-us = <80>;
131 min-residency-us = <2000>;
132 arm,psci-suspend-param = <0x0010000>;
135 CLUSTER_SLEEP_0: cluster-sleep-0 {
136 compatible = "arm,idle-state";
137 local-timer-stop;
138 entry-latency-us = <350>;
139 exit-latency-us = <80>;
140 min-residency-us = <3000>;
141 arm,psci-suspend-param = <0x1010000>;
147 compatible = "arm,psci-0.2";
152 compatible = "fixed-clock";
153 clock-frequency = <26000000>;
154 #clock-cells = <0>;
158 compatible = "fixed-clock";
159 clock-frequency = <26000000>;
160 #clock-cells = <0>;
164 compatible = "fixed-clock";
165 #clock-cells = <0>;
166 clock-frequency = <26000000>;
167 clock-output-names = "clk26m";
171 compatible = "fixed-clock";
172 #clock-cells = <0>;
173 clock-frequency = <32768>;
174 clock-output-names = "clk32k";
178 compatible = "fixed-clock";
179 #clock-cells = <0>;
180 clock-frequency = <50000000>;
181 clock-output-names = "clkfpc";
185 compatible = "fixed-clock";
186 #clock-cells = <0>;
187 clock-frequency = <6500000>;
188 clock-output-names = "clkaud_ext_i_0";
192 compatible = "fixed-clock";
193 #clock-cells = <0>;
194 clock-frequency = <196608000>;
195 clock-output-names = "clkaud_ext_i_1";
199 compatible = "fixed-clock";
200 #clock-cells = <0>;
201 clock-frequency = <180633600>;
202 clock-output-names = "clkaud_ext_i_2";
206 compatible = "fixed-clock";
207 #clock-cells = <0>;
208 clock-frequency = <30000000>;
209 clock-output-names = "clki2si0_mck_i";
213 compatible = "fixed-clock";
214 #clock-cells = <0>;
215 clock-frequency = <30000000>;
216 clock-output-names = "clki2si1_mck_i";
220 compatible = "fixed-clock";
221 #clock-cells = <0>;
222 clock-frequency = <30000000>;
223 clock-output-names = "clki2si2_mck_i";
227 compatible = "fixed-clock";
228 #clock-cells = <0>;
229 clock-frequency = <30000000>;
230 clock-output-names = "clktdmin_mclk_i";
234 compatible = "arm,armv8-timer";
235 interrupt-parent = <&gic>;
247 compatible = "mediatek,mt2712-topckgen", "syscon";
249 #clock-cells = <1>;
253 compatible = "mediatek,mt2712-infracfg", "syscon";
255 #clock-cells = <1>;
259 compatible = "mediatek,mt2712-pericfg", "syscon";
261 #clock-cells = <1>;
265 compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon";
270 compatible = "mediatek,mt2712-pinctrl";
272 mediatek,pctl-regmap = <&syscfg_pctl_a>;
273 pins-are-numbered;
274 gpio-controller;
275 #gpio-cells = <2>;
276 interrupt-controller;
277 #interrupt-cells = <2>;
281 scpsys: power-controller@10006000 {
282 compatible = "mediatek,mt2712-scpsys", "syscon";
283 #power-domain-cells = <1>;
291 clock-names = "mm", "mfg", "venc",
297 compatible = "mediatek,mt2712-uart",
298 "mediatek,mt6577-uart";
302 clock-names = "baud", "bus";
305 dma-names = "tx", "rx";
310 compatible = "mediatek,mt2712-rtc";
316 compatible = "mediatek,mt2712-spi-slave";
320 clock-names = "spi";
321 assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
322 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
327 compatible = "mediatek,mt2712-m4u";
331 clock-names = "bclk";
334 #iommu-cells = <1>;
338 compatible = "mediatek,mt2712-apmixedsys", "syscon";
340 #clock-cells = <1>;
344 compatible = "mediatek,mt2712-m4u";
348 clock-names = "bclk";
350 #iommu-cells = <1>;
354 compatible = "mediatek,mt2712-mcucfg", "syscon";
356 #clock-cells = <1>;
359 sysirq: interrupt-controller@10220a80 {
360 compatible = "mediatek,mt2712-sysirq",
361 "mediatek,mt6577-sysirq";
362 interrupt-controller;
363 #interrupt-cells = <3>;
364 interrupt-parent = <&gic>;
368 gic: interrupt-controller@10510000 {
369 compatible = "arm,gic-400";
370 #interrupt-cells = <3>;
371 interrupt-parent = <&gic>;
372 interrupt-controller;
381 apdma: dma-controller@11000400 {
382 compatible = "mediatek,mt2712-uart-dma",
383 "mediatek,mt6577-uart-dma";
408 dma-requests = <12>;
410 clock-names = "apdma";
411 #dma-cells = <1>;
415 compatible = "mediatek,mt2712-auxadc";
418 clock-names = "main";
419 #io-channel-cells = <1>;
424 compatible = "mediatek,mt2712-uart",
425 "mediatek,mt6577-uart";
429 clock-names = "baud", "bus";
432 dma-names = "tx", "rx";
437 compatible = "mediatek,mt2712-uart",
438 "mediatek,mt6577-uart";
442 clock-names = "baud", "bus";
445 dma-names = "tx", "rx";
450 compatible = "mediatek,mt2712-uart",
451 "mediatek,mt6577-uart";
455 clock-names = "baud", "bus";
458 dma-names = "tx", "rx";
463 compatible = "mediatek,mt2712-uart",
464 "mediatek,mt6577-uart";
468 clock-names = "baud", "bus";
471 dma-names = "tx", "rx";
476 compatible = "mediatek,mt2712-pwm";
478 #pwm-cells = <2>;
490 clock-names = "top",
504 compatible = "mediatek,mt2712-i2c";
508 clock-div = <4>;
511 clock-names = "main",
513 #address-cells = <1>;
514 #size-cells = <0>;
519 compatible = "mediatek,mt2712-i2c";
523 clock-div = <4>;
526 clock-names = "main",
528 #address-cells = <1>;
529 #size-cells = <0>;
534 compatible = "mediatek,mt2712-i2c";
538 clock-div = <4>;
541 clock-names = "main",
543 #address-cells = <1>;
544 #size-cells = <0>;
549 compatible = "mediatek,mt2712-spi";
550 #address-cells = <1>;
551 #size-cells = <0>;
557 clock-names = "parent-clk", "sel-clk", "spi-clk";
562 compatible = "mediatek,mt2712-nfc";
566 clock-names = "nfi_clk", "pad_clk";
567 ecc-engine = <&bch>;
568 #address-cells = <1>;
569 #size-cells = <0>;
574 compatible = "mediatek,mt2712-ecc";
578 clock-names = "nfiecc_clk";
583 compatible = "mediatek,mt2712-i2c";
587 clock-div = <4>;
590 clock-names = "main",
592 #address-cells = <1>;
593 #size-cells = <0>;
598 compatible = "mediatek,mt2712-i2c";
602 clock-div = <4>;
605 clock-names = "main",
607 #address-cells = <1>;
608 #size-cells = <0>;
613 compatible = "mediatek,mt2712-i2c";
617 clock-div = <4>;
620 clock-names = "main",
622 #address-cells = <1>;
623 #size-cells = <0>;
628 compatible = "mediatek,mt2712-spi";
629 #address-cells = <1>;
630 #size-cells = <0>;
636 clock-names = "parent-clk", "sel-clk", "spi-clk";
641 compatible = "mediatek,mt2712-spi";
642 #address-cells = <1>;
643 #size-cells = <0>;
649 clock-names = "parent-clk", "sel-clk", "spi-clk";
654 compatible = "mediatek,mt2712-spi";
655 #address-cells = <1>;
656 #size-cells = <0>;
662 clock-names = "parent-clk", "sel-clk", "spi-clk";
667 compatible = "mediatek,mt2712-spi";
668 #address-cells = <1>;
669 #size-cells = <0>;
675 clock-names = "parent-clk", "sel-clk", "spi-clk";
680 compatible = "mediatek,mt2712-uart",
681 "mediatek,mt6577-uart";
685 clock-names = "baud", "bus";
688 dma-names = "tx", "rx";
692 stmmac_axi_setup: stmmac-axi-config {
698 mtl_rx_setup: rx-queues-config {
699 snps,rx-queues-to-use = <1>;
700 snps,rx-sched-sp;
702 snps,dcb-algorithm;
703 snps,map-to-dma-channel = <0x0>;
708 mtl_tx_setup: tx-queues-config {
709 snps,tx-queues-to-use = <3>;
710 snps,tx-sched-wrr;
713 snps,dcb-algorithm;
718 snps,dcb-algorithm;
723 snps,dcb-algorithm;
729 compatible = "mediatek,mt2712-gmac";
732 interrupt-names = "macirq";
733 mac-address = [00 55 7b b5 7d f7];
734 clock-names = "axi",
742 assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
744 assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
746 power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;
748 snps,axi-config = <&stmmac_axi_setup>;
749 snps,mtl-rx-config = <&mtl_rx_setup>;
750 snps,mtl-tx-config = <&mtl_tx_setup>;
758 compatible = "mediatek,mt2712-mmc";
765 clock-names = "source", "hclk", "bus_clk", "source_cg";
770 compatible = "mediatek,mt2712-mmc";
776 clock-names = "source", "hclk", "source_cg";
781 compatible = "mediatek,mt2712-mmc";
787 clock-names = "source", "hclk", "source_cg";
792 compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3";
795 reg-names = "mac", "ippc";
799 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>;
801 clock-names = "sys_ck";
802 mediatek,syscon-wakeup = <&pericfg 0x510 2>;
803 #address-cells = <2>;
804 #size-cells = <2>;
809 compatible = "mediatek,mt2712-xhci",
810 "mediatek,mtk-xhci";
812 reg-names = "mac";
814 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>;
816 clock-names = "sys_ck", "ref_ck";
821 u3phy0: usb-phy@11290000 {
822 compatible = "mediatek,mt2712-tphy",
823 "mediatek,generic-tphy-v2";
824 #address-cells = <1>;
825 #size-cells = <1>;
829 u2port0: usb-phy@0 {
832 clock-names = "ref";
833 #phy-cells = <1>;
837 u2port1: usb-phy@8000 {
840 clock-names = "ref";
841 #phy-cells = <1>;
845 u3port0: usb-phy@8700 {
848 clock-names = "ref";
849 #phy-cells = <1>;
855 compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3";
858 reg-names = "mac", "ippc";
863 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>;
865 clock-names = "sys_ck";
866 mediatek,syscon-wakeup = <&pericfg 0x514 2>;
867 #address-cells = <2>;
868 #size-cells = <2>;
873 compatible = "mediatek,mt2712-xhci",
874 "mediatek,mtk-xhci";
876 reg-names = "mac";
878 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>;
880 clock-names = "sys_ck", "ref_ck";
885 u3phy1: usb-phy@112e0000 {
886 compatible = "mediatek,mt2712-tphy",
887 "mediatek,generic-tphy-v2";
888 #address-cells = <1>;
889 #size-cells = <1>;
893 u2port2: usb-phy@0 {
896 clock-names = "ref";
897 #phy-cells = <1>;
901 u2port3: usb-phy@8000 {
904 clock-names = "ref";
905 #phy-cells = <1>;
909 u3port1: usb-phy@8700 {
912 clock-names = "ref";
913 #phy-cells = <1>;
919 compatible = "mediatek,mt2712-pcie";
923 reg-names = "port0", "port1";
924 #address-cells = <3>;
925 #size-cells = <2>;
932 clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
934 phy-names = "pcie-phy0", "pcie-phy1";
935 bus-range = <0x00 0xff>;
942 #address-cells = <3>;
943 #size-cells = <2>;
944 #interrupt-cells = <1>;
946 interrupt-map-mask = <0 0 0 7>;
947 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
951 pcie_intc0: interrupt-controller {
952 interrupt-controller;
953 #address-cells = <0>;
954 #interrupt-cells = <1>;
962 #address-cells = <3>;
963 #size-cells = <2>;
964 #interrupt-cells = <1>;
966 interrupt-map-mask = <0 0 0 7>;
967 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
971 pcie_intc1: interrupt-controller {
972 interrupt-controller;
973 #address-cells = <0>;
974 #interrupt-cells = <1>;
980 compatible = "mediatek,mt2712-mfgcfg", "syscon";
982 #clock-cells = <1>;
986 compatible = "mediatek,mt2712-mmsys", "syscon";
988 #clock-cells = <1>;
992 compatible = "mediatek,mt2712-smi-larb";
995 mediatek,larb-id = <0>;
996 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
999 clock-names = "apb", "smi";
1003 compatible = "mediatek,mt2712-smi-common";
1005 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1008 clock-names = "apb", "smi";
1012 compatible = "mediatek,mt2712-smi-larb";
1015 mediatek,larb-id = <4>;
1016 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1019 clock-names = "apb", "smi";
1023 compatible = "mediatek,mt2712-smi-larb";
1026 mediatek,larb-id = <5>;
1027 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1030 clock-names = "apb", "smi";
1034 compatible = "mediatek,mt2712-smi-common";
1036 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1039 clock-names = "apb", "smi";
1043 compatible = "mediatek,mt2712-smi-larb";
1046 mediatek,larb-id = <7>;
1047 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1050 clock-names = "apb", "smi";
1054 compatible = "mediatek,mt2712-imgsys", "syscon";
1056 #clock-cells = <1>;
1060 compatible = "mediatek,mt2712-smi-larb";
1063 mediatek,larb-id = <2>;
1064 power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>;
1067 clock-names = "apb", "smi";
1071 compatible = "mediatek,mt2712-bdpsys", "syscon";
1073 #clock-cells = <1>;
1077 compatible = "mediatek,mt2712-vdecsys", "syscon";
1079 #clock-cells = <1>;
1083 compatible = "mediatek,mt2712-smi-larb";
1086 mediatek,larb-id = <1>;
1087 power-domains = <&scpsys MT2712_POWER_DOMAIN_VDEC>;
1090 clock-names = "apb", "smi";
1094 compatible = "mediatek,mt2712-vencsys", "syscon";
1096 #clock-cells = <1>;
1100 compatible = "mediatek,mt2712-smi-larb";
1103 mediatek,larb-id = <3>;
1104 power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>;
1107 clock-names = "apb", "smi";
1111 compatible = "mediatek,mt2712-smi-larb";
1114 mediatek,larb-id = <6>;
1115 power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>;
1118 clock-names = "apb", "smi";
1122 compatible = "mediatek,mt2712-jpgdecsys", "syscon";
1124 #clock-cells = <1>;