Lines Matching +full:fixed +full:- +full:partitions
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Device tree for the CN9130-DB board.
10 #include <dt-bindings/gpio/gpio.h>
13 model = "Marvell Armada CN9130-DB";
16 stdout-path = "serial0:115200n8";
36 compatible = "regulator-gpio";
37 regulator-name = "ap0_sd_vccq";
38 regulator-min-microvolt = <1800000>;
39 regulator-max-microvolt = <3300000>;
45 compatible = "regulator-fixed";
46 regulator-name = "cp0-xhci0-vbus";
47 regulator-min-microvolt = <5000000>;
48 regulator-max-microvolt = <5000000>;
49 enable-active-high;
54 compatible = "usb-nop-xceiv";
55 vcc-supply = <&cp0_reg_usb3_vbus0>;
59 compatible = "regulator-fixed";
60 regulator-name = "cp0-xhci1-vbus";
61 regulator-min-microvolt = <5000000>;
62 regulator-max-microvolt = <5000000>;
63 enable-active-high;
68 compatible = "usb-nop-xceiv";
69 vcc-supply = <&cp0_reg_usb3_vbus1>;
73 compatible = "regulator-gpio";
74 regulator-name = "cp0_sd_vccq";
75 regulator-min-microvolt = <1800000>;
76 regulator-max-microvolt = <3300000>;
83 compatible = "regulator-fixed";
84 regulator-name = "cp0_sd_vcc";
85 regulator-min-microvolt = <3300000>;
86 regulator-max-microvolt = <3300000>;
88 enable-active-high;
89 regulator-always-on;
92 cp0_sfp_eth0: sfp-eth@0 {
94 i2c-bus = <&cp0_sfpp0_i2c>;
95 los-gpio = <&cp0_module_expander1 11 GPIO_ACTIVE_HIGH>;
96 mod-def0-gpio = <&cp0_module_expander1 10 GPIO_ACTIVE_LOW>;
97 tx-disable-gpio = <&cp0_module_expander1 9 GPIO_ACTIVE_HIGH>;
98 tx-fault-gpio = <&cp0_module_expander1 8 GPIO_ACTIVE_HIGH>;
112 /* on-board eMMC - U9 */
114 pinctrl-names = "default";
115 bus-width = <8>;
116 vqmmc-supply = <&ap0_reg_sd_vccq>;
128 /* SLM-1521-V2, CON9 */
131 phy-mode = "10gbase-kr";
134 managed = "in-band-status";
142 phy-mode = "rgmii-id";
149 phy-mode = "rgmii-id";
162 pinctrl-names = "default";
163 pinctrl-0 = <&cp0_i2c0_pins>;
164 clock-frequency = <100000>;
169 pinctrl-names = "default";
170 gpio-controller;
171 #gpio-cells = <2>;
193 clock-frequency = <100000>;
195 /* SLM-1521-V2 - U3 */
196 i2c-mux@72 { /* verify address - depends on dpr */
198 #address-cells = <1>;
199 #size-cells = <0>;
202 #address-cells = <1>;
203 #size-cells = <0>;
208 #address-cells = <1>;
209 #size-cells = <0>;
214 pinctrl-names = "default";
215 gpio-controller;
216 #gpio-cells = <2>;
227 phy0: ethernet-phy@0 {
231 phy1: ethernet-phy@1 {
238 pinctrl-names = "default";
239 pinctrl-0 = <&nand_pins &nand_rb>;
243 label = "main-storage";
244 nand-rb = <0>;
245 nand-ecc-mode = "hw";
246 nand-on-flash-bbt;
247 nand-ecc-strength = <8>;
248 nand-ecc-step-size = <512>;
250 partitions {
251 compatible = "fixed-partitions";
252 #address-cells = <1>;
253 #size-cells = <1>;
256 label = "U-Boot";
271 /* SLM-1521-V2, CON6 */
274 num-lanes = <4>;
275 num-viewport = <8>;
286 /* SLM-1521-V2, CON2 */
287 sata-port@1 {
297 pinctrl-names = "default";
298 pinctrl-0 = <&cp0_sdhci_pins
300 bus-width = <4>;
301 cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
302 no-1-8-v;
303 vqmmc-supply = <&cp0_reg_sd_vccq>;
304 vmmc-supply = <&cp0_reg_sd_vcc>;
310 pinctrl-names = "default";
311 pinctrl-0 = <&cp0_spi0_pins>;
314 spi-flash@0 {
315 #address-cells = <0x1>;
316 #size-cells = <0x1>;
317 compatible = "jedec,spi-nor";
319 /* On-board MUX does not allow higher frequencies */
320 spi-max-frequency = <40000000>;
322 partitions {
323 compatible = "fixed-partitions";
324 #address-cells = <1>;
325 #size-cells = <1>;
328 label = "U-Boot-0";
333 label = "Filesystem-0";
342 compatible = "marvell,cp115-standalone-pinctrl";
344 cp0_i2c0_pins: cp0-i2c-pins-0 {
348 cp0_i2c1_pins: cp0-i2c-pins-1 {
352 cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
359 cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
366 cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
370 cp0_sdhci_pins: cp0-sdhi-pins-0 {
375 cp0_spi0_pins: cp0-spi-pins-0 {
379 nand_pins: nand-pins {
386 nand_rb: nand-rb {
395 usb-phy = <&cp0_usb3_0_phy0>;
396 phy-names = "usb";
401 usb-phy = <&cp0_usb3_0_phy1>;
402 phy-names = "usb";