Lines Matching +full:agilex +full:- +full:clkmgr
1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/agilex-clock.h>
12 compatible = "intel,socfpga-agilex";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
18 #size-cells = <2>;
22 compatible = "shared-dma-pool";
25 no-map;
30 #address-cells = <1>;
31 #size-cells = <0>;
34 compatible = "arm,cortex-a53";
36 enable-method = "psci";
41 compatible = "arm,cortex-a53";
43 enable-method = "psci";
48 compatible = "arm,cortex-a53";
50 enable-method = "psci";
55 compatible = "arm,cortex-a53";
57 enable-method = "psci";
63 compatible = "arm,armv8-pmuv3";
68 interrupt-affinity = <&cpu0>,
72 interrupt-parent = <&intc>;
76 compatible = "arm,psci-0.2";
81 compatible = "arm,gic-400", "arm,cortex-a15-gic";
82 #interrupt-cells = <3>;
83 interrupt-controller;
91 #address-cells = <1>;
92 #size-cells = <1>;
93 compatible = "simple-bus";
95 interrupt-parent = <&intc>;
99 #address-cells = <0x1>;
100 #size-cells = <0x1>;
101 compatible = "fpga-region";
102 fpga-mgr = <&fpga_mgr>;
105 clkmgr: clock-controller@ffd10000 { label
106 compatible = "intel,agilex-clkmgr";
108 #clock-cells = <1>;
112 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
113 #clock-cells = <0>;
114 compatible = "fixed-clock";
117 cb_intosc_ls_clk: cb-intosc-ls-clk {
118 #clock-cells = <0>;
119 compatible = "fixed-clock";
122 f2s_free_clk: f2s-free-clk {
123 #clock-cells = <0>;
124 compatible = "fixed-clock";
128 #clock-cells = <0>;
129 compatible = "fixed-clock";
132 qspi_clk: qspi-clk {
133 #clock-cells = <0>;
134 compatible = "fixed-clock";
135 clock-frequency = <200000000>;
140 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
143 interrupt-names = "macirq";
144 mac-address = [00 00 00 00 00 00];
146 reset-names = "stmmaceth", "stmmaceth-ocp";
147 tx-fifo-depth = <16384>;
148 rx-fifo-depth = <16384>;
149 snps,multicast-filter-bins = <256>;
151 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
152 clocks = <&clkmgr AGILEX_EMAC0_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
153 clock-names = "stmmaceth", "ptp_ref";
158 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
161 interrupt-names = "macirq";
162 mac-address = [00 00 00 00 00 00];
164 reset-names = "stmmaceth", "stmmaceth-ocp";
165 tx-fifo-depth = <16384>;
166 rx-fifo-depth = <16384>;
167 snps,multicast-filter-bins = <256>;
169 altr,sysmgr-syscon = <&sysmgr 0x48 8>;
170 clocks = <&clkmgr AGILEX_EMAC1_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
171 clock-names = "stmmaceth", "ptp_ref";
176 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
179 interrupt-names = "macirq";
180 mac-address = [00 00 00 00 00 00];
182 reset-names = "stmmaceth", "stmmaceth-ocp";
183 tx-fifo-depth = <16384>;
184 rx-fifo-depth = <16384>;
185 snps,multicast-filter-bins = <256>;
187 altr,sysmgr-syscon = <&sysmgr 0x4c 16>;
188 clocks = <&clkmgr AGILEX_EMAC2_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
189 clock-names = "stmmaceth", "ptp_ref";
194 #address-cells = <1>;
195 #size-cells = <0>;
196 compatible = "snps,dw-apb-gpio";
201 porta: gpio-controller@0 {
202 compatible = "snps,dw-apb-gpio-port";
203 gpio-controller;
204 #gpio-cells = <2>;
205 snps,nr-gpios = <24>;
207 interrupt-controller;
208 #interrupt-cells = <2>;
214 #address-cells = <1>;
215 #size-cells = <0>;
216 compatible = "snps,dw-apb-gpio";
221 portb: gpio-controller@0 {
222 compatible = "snps,dw-apb-gpio-port";
223 gpio-controller;
224 #gpio-cells = <2>;
225 snps,nr-gpios = <24>;
227 interrupt-controller;
228 #interrupt-cells = <2>;
234 #address-cells = <1>;
235 #size-cells = <0>;
236 compatible = "snps,designware-i2c";
240 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
245 #address-cells = <1>;
246 #size-cells = <0>;
247 compatible = "snps,designware-i2c";
251 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
256 #address-cells = <1>;
257 #size-cells = <0>;
258 compatible = "snps,designware-i2c";
262 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
267 #address-cells = <1>;
268 #size-cells = <0>;
269 compatible = "snps,designware-i2c";
273 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
278 #address-cells = <1>;
279 #size-cells = <0>;
280 compatible = "snps,designware-i2c";
284 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
289 #address-cells = <1>;
290 #size-cells = <0>;
291 compatible = "altr,socfpga-dw-mshc";
294 fifo-depth = <0x400>;
296 reset-names = "reset";
297 clocks = <&clkmgr AGILEX_L4_MP_CLK>,
298 <&clkmgr AGILEX_SDMMC_CLK>;
299 clock-names = "biu", "ciu";
305 #address-cells = <1>;
306 #size-cells = <0>;
307 compatible = "altr,socfpga-denali-nand";
310 reg-names = "nand_data", "denali_reg";
312 clocks = <&clkmgr AGILEX_NAND_CLK>,
313 <&clkmgr AGILEX_NAND_X_CLK>,
314 <&clkmgr AGILEX_NAND_ECC_CLK>;
315 clock-names = "nand", "nand_x", "ecc";
321 compatible = "mmio-sram";
337 #dma-cells = <1>;
338 #dma-channels = <8>;
339 #dma-requests = <32>;
341 reset-names = "dma", "dma-ocp";
342 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
343 clock-names = "apb_pclk";
347 #reset-cells = <1>;
348 compatible = "altr,stratix10-rst-mgr";
353 compatible = "arm,mmu-500", "arm,smmu-v2";
355 #global-interrupts = <2>;
356 #iommu-cells = <1>;
357 interrupt-parent = <&intc>;
359 <0 129 4>, /* Global Non-secure Fault */
360 /* Non-secure Context Interrupts (32) */
369 stream-match-mask = <0x7ff0>;
370 clocks = <&clkmgr AGILEX_MPU_CCU_CLK>,
371 <&clkmgr AGILEX_L3_MAIN_FREE_CLK>,
372 <&clkmgr AGILEX_L4_MAIN_CLK>;
377 compatible = "snps,dw-apb-ssi";
378 #address-cells = <1>;
379 #size-cells = <0>;
383 reset-names = "spi";
384 reg-io-width = <4>;
385 num-cs = <4>;
386 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
391 compatible = "snps,dw-apb-ssi";
392 #address-cells = <1>;
393 #size-cells = <0>;
397 reset-names = "spi";
398 reg-io-width = <4>;
399 num-cs = <4>;
400 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
405 compatible = "altr,sys-mgr-s10","altr,sys-mgr";
411 compatible = "arm,armv8-timer";
419 compatible = "snps,dw-apb-timer";
422 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
423 clock-names = "timer";
427 compatible = "snps,dw-apb-timer";
430 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
431 clock-names = "timer";
435 compatible = "snps,dw-apb-timer";
438 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
439 clock-names = "timer";
443 compatible = "snps,dw-apb-timer";
446 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
447 clock-names = "timer";
451 compatible = "snps,dw-apb-uart";
454 reg-shift = <2>;
455 reg-io-width = <4>;
458 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
462 compatible = "snps,dw-apb-uart";
465 reg-shift = <2>;
466 reg-io-width = <4>;
468 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
473 #phy-cells = <0>;
474 compatible = "usb-nop-xceiv";
483 phy-names = "usb2-phy";
485 reset-names = "dwc2", "dwc2-ecc";
486 clocks = <&clkmgr AGILEX_USB_CLK>;
496 phy-names = "usb2-phy";
498 reset-names = "dwc2", "dwc2-ecc";
500 clocks = <&clkmgr AGILEX_USB_CLK>;
505 compatible = "snps,dw-wdt";
509 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
514 compatible = "snps,dw-wdt";
518 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
523 compatible = "snps,dw-wdt";
527 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
532 compatible = "snps,dw-wdt";
536 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
541 compatible = "altr,sdr-ctl", "syscon";
546 compatible = "altr,socfpga-s10-ecc-manager",
547 "altr,socfpga-a10-ecc-manager";
548 altr,sysmgr-syscon = <&sysmgr>;
549 #address-cells = <1>;
550 #size-cells = <1>;
552 interrupt-controller;
553 #interrupt-cells = <2>;
557 compatible = "altr,sdram-edac-s10";
558 altr,sdr-syscon = <&sdr>;
562 ocram-ecc@ff8cc000 {
563 compatible = "altr,socfpga-s10-ocram-ecc",
564 "altr,socfpga-a10-ocram-ecc";
566 altr,ecc-parent = <&ocram>;
570 usb0-ecc@ff8c4000 {
571 compatible = "altr,socfpga-s10-usb-ecc",
572 "altr,socfpga-usb-ecc";
574 altr,ecc-parent = <&usb0>;
578 emac0-rx-ecc@ff8c0000 {
579 compatible = "altr,socfpga-s10-eth-mac-ecc",
580 "altr,socfpga-eth-mac-ecc";
582 altr,ecc-parent = <&gmac0>;
586 emac0-tx-ecc@ff8c0400 {
587 compatible = "altr,socfpga-s10-eth-mac-ecc",
588 "altr,socfpga-eth-mac-ecc";
590 altr,ecc-parent = <&gmac0>;
594 sdmmca-ecc@ff8c8c00 {
595 compatible = "altr,socfpga-s10-sdmmc-ecc",
596 "altr,socfpga-sdmmc-ecc";
598 altr,ecc-parent = <&mmc>;
605 compatible = "cdns,qspi-nor";
606 #address-cells = <1>;
607 #size-cells = <0>;
611 cdns,fifo-depth = <128>;
612 cdns,fifo-width = <4>;
613 cdns,trigger-address = <0x00000000>;
621 compatible = "intel,agilex-svc";
623 memory-region = <&service_reserved>;
625 fpga_mgr: fpga-mgr {
626 compatible = "intel,agilex-soc-fpga-mgr";